From 88a17ffa07b25e06184a0011b4b41fac4b7a070f Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 5 Jan 2024 15:58:06 -0700 Subject: [PATCH 1/2] dt-bindings: Add soccp controller property This is needed to vote for soccp boot/slumber sequence for hardware fence feature. Change-Id: I169d83ed9d5acf66027194bf5fee0825bb5602d2 Signed-off-by: Harshdeep Dhatt --- bindings/adreno-gmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/adreno-gmu.txt b/bindings/adreno-gmu.txt index a5544793..08173ede 100644 --- a/bindings/adreno-gmu.txt +++ b/bindings/adreno-gmu.txt @@ -66,6 +66,7 @@ GMU GDSC/regulators: baseAddr - base address of the IPC region size - size of the IPC region +- qcom,soccp-controller: Phandle of the soccp controller Example: From 65f3e20c5fc25d88740f398962aaa322dd5ee725 Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 5 Jan 2024 15:59:46 -0700 Subject: [PATCH 2/2] ARM: dts: msm: Add soccp controller phandle for sun Hardware fence feature requires that we keep soccp from power collapsing as long as GMU is active. Change-Id: I3721aefd8cb34edfeba846115132002defa8f385 Signed-off-by: Harshdeep Dhatt --- gpu/sun-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..4d34e4e4 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -177,5 +177,6 @@ qcom,iommu-dma = "disabled"; qcom,ipc-core = <0x00400000 0x140000>; + qcom,soccp-controller = <&soccp_pas>; }; };