diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi
index 03774135..c779d0fd 100644
--- a/display/sun-sde-display.dtsi
+++ b/display/sun-sde-display.dtsi
@@ -92,17 +92,10 @@
 		  * MDP clock nodes, no actual vote shall be added and this
 		  * change is done just to satisfy sync state requirements.
 		  */
-		 <&dispcc DISP_CC_MDSS_MDP_CLK>,
-		 /*
-		  * The esync clk RCG is only necessary here to set its parent
-		  * to the pll dsi clk, which also needs to be available at the
-		  * point that its known whether the clock will be used. After
-		  * updating the parent, this clock handle is no longer needed.
-		  */
-		 <&dispcc DISP_CC_ESYNC0_CLK_SRC>;
+		 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
 		      "pll_byte_clk1", "pll_dsi_clk1",
-		      "mdp_core_clk", "esync_clk_rcg";
+		      "mdp_core_clk";
 	vddio-supply = <&L12B>;
 	vci-supply = <&L13B>;
 	vdd-supply = <&L11B>;
@@ -128,17 +121,10 @@
 		  * MDP clock nodes, no actual vote shall be added and this
 		  * change is done just to satisfy sync state requirements.
 		  */
-		 <&dispcc DISP_CC_MDSS_MDP_CLK>,
-		 /*
-		  * The esync clk RCG is only necessary here to set its parent
-		  * to the pll dsi clk, which also needs to be available at the
-		  * point that its known whether the clock will be used. After
-		  * updating the parent, this clock handle is no longer needed.
-		  */
-		 <&dispcc DISP_CC_ESYNC1_CLK_SRC>;
+		 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
 		      "pll_byte_clk1", "pll_dsi_clk1",
-		      "mdp_core_clk", "esync_clk_rcg";
+		      "mdp_core_clk";
 	vddio-supply = <&L12B>;
 	vci-supply = <&L13B>;
 	vdd-supply = <&L11B>;
diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi
index 3c3f1462..f0d8064c 100644
--- a/display/sun-sde.dtsi
+++ b/display/sun-sde.dtsi
@@ -313,13 +313,15 @@
 		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+		<&mdss_dsi_phy0 1>,
 		<&dispcc DISP_CC_ESYNC0_CLK>,
+		<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
 		<&dispcc DISP_CC_OSC_CLK>,
 		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
 		<&rpmhcc RPMH_CXO_CLK>;
 	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
-			"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
-			"esc_clk", "xo";
+			"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
+			"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
 };
 
 &mdss_dsi1 {
@@ -330,13 +332,15 @@
 		<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+		<&mdss_dsi_phy1 1>,
 		<&dispcc DISP_CC_ESYNC1_CLK>,
+		<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
 		<&dispcc DISP_CC_OSC_CLK>,
 		<&dispcc DISP_CC_MDSS_ESC1_CLK>,
 		<&rpmhcc RPMH_CXO_CLK>;
 	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
-			"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
-			"esc_clk", "xo";
+			"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
+			"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
 };
 
 &mdss_dsi_phy0 {