From 4b542168bb295ec2d05a0372f358f4b70e3a5a7d Mon Sep 17 00:00:00 2001
From: Mike Tipton <quic_mdtipton@quicinc.com>
Date: Tue, 5 Dec 2023 15:56:17 -0800
Subject: [PATCH] ARM: dts: msm: Add SCMI RX notification support for Sun

The CPUCP SCMI notifications are used for thermal limits. Add the
mailbox used for them.

Change-Id: I51eadabe997670190414b9b767439be5064046c7
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
---
 qcom/sun.dtsi | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 61a7b6c0..2f4df3ad 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -2874,7 +2874,12 @@
 
 		cpu_scp_lpri: scmi-shmem@0 {
 			compatible = "arm,scmi-shmem";
-			reg = <0x0 0x17b4e000 0x0 0x400>;
+			reg = <0x0 0x17b4e000 0x0 0x200>;
+		};
+
+		cpucp_rx: scmi-shmem@1 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x17b4e200 0x0 0x200>;
 		};
 	};
 
@@ -2898,9 +2903,9 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "arm,scmi";
-		mboxes = <&cpucp 0>;
-		mbox-names = "tx";
-		shmem = <&cpu_scp_lpri>;
+		mboxes = <&cpucp 0>, <&cpucp 2>;
+		mbox-names = "tx", "rx";
+		shmem = <&cpu_scp_lpri>, <&cpucp_rx>;
 
 		scmi_perf: protocol@13 {
 			reg = <0x13>;