dt-bindings: platform: msm: Add I2C msm geni bindings for Sun

Add DT bindings for I2C which provides the resource management details
for the I2C geni msm driver.

Change-Id: I2bc39bf86e0760db595cd2a17e7c1fc6ee1f98cf
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>

bindings/i2c/qcom,i2c-msm-geni.yaml

@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/i2c/qcom,i2c-msm-geni.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Technologies Inc GENI based QUPv3 I2C Controller
+
+maintainers:
+  - Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    const: qcom,i2c-geni
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: se-clk
+
+  dmas:
+    maxItems: 2
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+  interconnects:
+    maxItems: 3
+
+  interconnect-names:
+    items:
+      - const: qup-core
+      - const: qup-config
+      - const: qup-memory
+
+  interrupts:
+    maxItems: 1
+
+  pinctrl-0: true
+  pinctrl-1: true
+
+  pinctrl-names:
+    minItems: 1
+    items:
+      - const: default
+      - const: sleep
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - pinctrl-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,gcc-sun.h>
+    #include <dt-bindings/interconnect/qcom,sun.h>
+
+    qupv3_se0_i2c: i2c@a80000 {
+        compatible = "qcom,i2c-geni";
+        reg = <0xa80000 0x4000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+        clock-names = "se-clk";
+        clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+        inteconnect-names = "qup-core", "qup-config", "qup-memory";
+        interconnects =	<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+                        <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+                        <&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
+        pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+        dmas = <&gpi_dma1 0 0 3 64 0>,
+                <&gpi_dma1 1 0 3 64 0>;
+        dma-names = "tx", "rx";
+    };
+...