From 49f746bf1ebdf94b75e926eee2b6f188703c7512 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 1 Feb 2024 18:22:00 +0530 Subject: [PATCH] ARM: dts: msm: Mark gpucc clock node as GenPD provider Mark gpucc clock node as GenPD provider and disable the graphics GDSC regulator nodes. While at it, update gxclkctl node to add support for gx_clkctl_gx_gdsc power domain. Change-Id: I0d4c84da2e3aadd7e1a901d6a9e26c7d4ad1a3c1 Signed-off-by: Jagadeesh Kona --- qcom/sun.dtsi | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index b5df11d0..089e9e41 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1797,14 +1797,17 @@ "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; - gxclkctl: clock-controller@3d64000 { - compatible = "qcom,dummycc"; - clock-output-names = "gxclkctl_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; + gxclkctl: clock-controller@3d68024 { + compatible = "qcom,sun-gx_clkctl"; + reg = <0x3d68024 0x8>; + reg-name = "cc_base"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + vdd_gx-supply = <&VDD_GFX_GFX_MXC_VOTER_LEVEL>; + #power-domain-cells = <1>; }; tcsrcc: clock-controller@f204008 { @@ -2083,6 +2086,7 @@ qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; + status = "disabled"; }; /* GX_CLKCTL GDSCs */ @@ -2095,6 +2099,7 @@ reg-supply = <&gpu_cc_cx_gdsc>; qcom,retain-regs; qcom,support-cfg-gdscr; + status = "disabled"; }; /* VIDEO_CC GDSCs */