From 49f20e9cf68adf2dfe1f8b5dcaebc1a030aac560 Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Mon, 20 Jan 2025 15:11:05 +0530 Subject: [PATCH] Revert "ARM: dts: msm: Fake UFS Ref clock to run on HS mode" This reverts commit d5c176fe3b0cd6b8de93d67fbe01a740c7b059ca. Change-Id: I50cc341052b54a6d9381d0c6501f78413dd31dc4 Signed-off-by: Vishvanath Singh --- qcom/kera_ufs2.dtsi | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi index 7ebce858..320ed23f 100644 --- a/qcom/kera_ufs2.dtsi +++ b/qcom/kera_ufs2.dtsi @@ -57,39 +57,5 @@ qcom,vccq2-parent-supply = <&S1B>; qcom,vccq2-parent-max-microamp = <210000>; - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "dev_ref_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&rpmhcc RPMH_LN_BB_CLK3>; - freq-table-hz = - <100000000 403000000>, - <0 0>, - <0 0>, - <100000000 403000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "ok"; };