ARM: dts: msm: Correct the dma nodes for i3c instances

Corrected/rectified dma nodes for qup2 i3c instances,
and also added ibi-controller id changes.

Change-Id: I2bbc7391fce38c231c57327547573e0de0d774c0
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
This commit is contained in:
Anil Veshala Veshala
2023-11-28 01:50:50 -08:00
parent 362840c89a
commit 48ee3a2d4c

View File

@@ -137,7 +137,7 @@
<&pdc 30 IRQ_TYPE_LEVEL_HIGH>; <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <0>; qcom,ibi-ctrl-id = <1>;
dmas = <&gpi_dma1 0 0 4 64 0>, dmas = <&gpi_dma1 0 0 4 64 0>,
<&gpi_dma1 1 0 4 64 0>; <&gpi_dma1 1 0 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
@@ -212,7 +212,7 @@
<&pdc 32 IRQ_TYPE_LEVEL_HIGH>; <&pdc 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <1>; qcom,ibi-ctrl-id = <2>;
dmas = <&gpi_dma1 0 1 4 64 0>, dmas = <&gpi_dma1 0 1 4 64 0>,
<&gpi_dma1 1 1 4 64 0>; <&gpi_dma1 1 1 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
@@ -382,7 +382,7 @@
<&pdc 34 IRQ_TYPE_LEVEL_HIGH>; <&pdc 34 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <2>; qcom,ibi-ctrl-id = <3>;
dmas = <&gpi_dma1 0 4 4 64 0>, dmas = <&gpi_dma1 0 4 4 64 0>,
<&gpi_dma1 1 4 4 64 0>; <&gpi_dma1 1 4 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
@@ -614,13 +614,14 @@
pinctrl-1 = <&qupv3_se8_i3c_sda_sleep>, <&qupv3_se8_i3c_scl_sleep>; pinctrl-1 = <&qupv3_se8_i3c_sda_sleep>, <&qupv3_se8_i3c_scl_sleep>;
pinctrl-2 = <&qupv3_se8_i3c_disable>; pinctrl-2 = <&qupv3_se8_i3c_disable>;
interrupts-extended = <&intc GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 48 IRQ_TYPE_LEVEL_HIGH>, <&pdc 64 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 47 IRQ_TYPE_LEVEL_HIGH>; <&pdc 37 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <3>; qcom,ibi-ctrl-id = <5>;
dmas = <&gpi_dma1 0 0 4 1024 0>, dmas = <&gpi_dma2 0 0 4 1024 0>,
<&gpi_dma1 1 0 4 1024 0>; <&gpi_dma2 1 0 4 1024 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@@ -693,9 +694,9 @@
<&pdc 47 IRQ_TYPE_LEVEL_HIGH>; <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <4>; qcom,ibi-ctrl-id = <6>;
dmas = <&gpi_dma1 0 1 4 64 0>, dmas = <&gpi_dma2 0 1 4 64 0>,
<&gpi_dma1 1 1 4 64 0>; <&gpi_dma2 1 1 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@@ -773,9 +774,9 @@
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <6>; qcom,ibi-ctrl-id = <7>;
dmas = <&gpi_dma1 0 2 4 64 0>, dmas = <&gpi_dma2 0 2 4 64 0>,
<&gpi_dma1 1 2 4 64 0>; <&gpi_dma2 1 2 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@@ -853,9 +854,9 @@
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <7>; qcom,ibi-ctrl-id = <8>;
dmas = <&gpi_dma1 0 3 4 64 0>, dmas = <&gpi_dma2 0 3 4 64 0>,
<&gpi_dma1 1 3 4 64 0>; <&gpi_dma2 1 3 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@@ -1077,9 +1078,9 @@
<&pdc 49 IRQ_TYPE_LEVEL_HIGH>; <&pdc 49 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <0>; #size-cells = <0>;
qcom,ibi-ctrl-id = <4>; qcom,ibi-ctrl-id = <9>;
dmas = <&gpi_dma1 0 7 4 64 0>, dmas = <&gpi_dma2 0 7 4 64 0>,
<&gpi_dma1 1 7 4 64 0>; <&gpi_dma2 1 7 4 64 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };