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ARM: dts: msm: Update Sun V2 GPU frequencies

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Add new GPU frequency support for Sun V2.

Change-Id: I66a6584a671e51a8420e2ceaace3c067ee56d009
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
This commit is contained in:
Carter Cooper
2024-05-08 13:51:01 -06:00
parent 9cbd03668a
commit 48b0e9aa44
1 changed files with 43 additions and 29 deletions
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72
gpu/sun-v2-gpu-pwrlevels.dtsi
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@@ -4,6 +4,7 @@
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L4 0x88295ffd
#define ACD_LEVEL_TURBO_L3 0x882a5ffd
#define ACD_LEVEL_TURBO_L1 0x882a5ffd
#define ACD_LEVEL_NOM_L1 0x882b5ffd
@@ -354,13 +355,26 @@
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <13>;
qcom,initial-pwrlevel = <14>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L3 */
/* TURBO_L4 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,gpu-freq = <1200000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
};
/* TURBO_L3 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1100000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
qcom,bus-freq = <11>;
@@ -371,8 +385,8 @@
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
@@ -384,8 +398,8 @@
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -397,8 +411,8 @@
};
/* NOM */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -410,8 +424,8 @@
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -423,8 +437,8 @@
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -436,8 +450,8 @@
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
@@ -449,8 +463,8 @@
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -462,8 +476,8 @@
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
@@ -475,8 +489,8 @@
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -488,8 +502,8 @@
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
@@ -501,8 +515,8 @@
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -514,8 +528,8 @@
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
@@ -527,8 +541,8 @@
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-pwrlevel@14 {
reg = <14>;
qcom,gpu-freq = <160000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;