From 47c204a8782db0d347e3bd75912f7c045c6919c8 Mon Sep 17 00:00:00 2001 From: Krishna Chaithanya Reddy G Date: Thu, 12 Sep 2024 12:31:12 +0530 Subject: [PATCH] ARM: dts: msm: Add QUPv3 and GPI DT nodes for sdxkova Added QUPv3(I2C, SPI and UART), GPI DT nodes and QUPv3 pinctrl support for sdxkova. Change-Id: I55394b443be7dd2a37b04e62fa2f308ebdf67753 Signed-off-by: Krishna Chaithanya Reddy G --- qcom/sdxkova.dtsi | 1180 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1168 insertions(+), 12 deletions(-) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index bb5a6bde..c9056a6c 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -130,6 +130,18 @@ aliases: aliases { serial0 = &uart1; mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + hsuart0 = &qupv3_se3_4uart; + hsuart1 = &qupv3_se4_2uart; + hsuart2 = &qupv3_se8_2uart; + i2c0 = &qupv3_se0_i2c; + i2c2 = &qupv3_se2_i2c; + i2c5 = &qupv3_se5_i2c; + i2c6 = &qupv3_se6_i2c; + i2c7 = &qupv3_se7_i2c; + spi0 = &qupv3_se0_spi; + spi2 = &qupv3_se2_spi; + spi6 = &qupv3_se6_spi; + spi7 = &qupv3_se7_spi; }; }; @@ -267,20 +279,785 @@ drive-strength = <2>; }; }; -}; -&qupv3_id_0 { - interconnects = - <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>; - interconnect-names = "qup-core"; - status = "ok"; -}; + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_cts: qupv3_se3_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; -&uart1 { - interconnects = - <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>; - status = "ok"; + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_default_rts: qupv3_se3_default_rts { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: qupv3_se3_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_default_rx: qupv3_se3_default_rx { + mux { + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_cts: qupv3_se3_cts { + mux { + pins = "gpio52"; + function = "qup_se3"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio53"; + function = "qup_se3"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio54"; + function = "qup_se3"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_rx: qupv3_se3_rx { + mux { + pins = "gpio55"; + function = "qup_se3"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup_se0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup_se0"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup_se0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup_se0"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup_se0"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup_se0"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio14"; + function = "qup_se2"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio15"; + function = "qup_se2"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio14"; + function = "qup_se2"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio15"; + function = "qup_se2"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio16"; + function = "qup_se2"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio17"; + function = "qup_se2"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup_se3"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup_se3"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup_se3"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup_se3"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup_se3"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup_se3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active { + mux { + pins = "gpio64"; + function = "qup_se4"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_rx_active: qupv3_se4_2uart_rx_active { + mux { + pins = "gpio65"; + function = "qup_se4"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio110"; + function = "qup_se5"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio111"; + function = "qup_se5"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio110", "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio110", "gpio111"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio112"; + function = "qup_se6"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio113"; + function = "qup_se6"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio112", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio112"; + function = "qup_se6"; + }; + + config { + pins = "gpio112"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio113"; + function = "qup_se6"; + }; + + config { + pins = "gpio113"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio114"; + function = "qup_se6"; + }; + + config { + pins = "gpio114"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio115"; + function = "qup_se6"; + }; + + config { + pins = "gpio115"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio116"; + function = "qup_se7"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio117"; + function = "qup_se7"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio116", "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio116"; + function = "qup_se7"; + }; + + config { + pins = "gpio116"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio117"; + function = "qup_se7"; + }; + + config { + pins = "gpio117"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio118"; + function = "qup_se7"; + }; + + config { + pins = "gpio118"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio119"; + function = "qup_se7"; + }; + + config { + pins = "gpio119"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { + qupv3_se8_2uart_tx_active: qupv3_se8_2uart_tx_active { + mux { + pins = "gpio124"; + function = "qup_se8"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_rx_active: qupv3_se8_2uart_rx_active { + mux { + pins = "gpio125"; + function = "qup_se8"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep { + mux { + pins = "gpio124", "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio124", "gpio125"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; &scm { @@ -675,6 +1452,43 @@ opp-avg-kBps = <104000 0>; }; }; + + qup1_gpi_iommu_region: qup1_gpi_iommu_region { + iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>; + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x0 0x900000 0x0 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x7f>; + qcom,ev-factor = <2>; + memory-region = <&qup1_gpi_iommu_region>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + qup1_se_iommu_region: qup1_se_iommu_region { + iommu-addresses = <&qupv3_id_0 0x0 0x40000000>, + <&qupv3_id_0 0x50000000 0xb0000000>; + }; }; &gcc { @@ -718,5 +1532,347 @@ #reset-cells = <1>; }; +/* QUPv3_0 wrapper instance */ +&qupv3_id_0 { + /delete-property/ interconnects; + /delete-property/ interconnect-names; + memory-region = <&qup1_se_iommu_region>; + qcom,iommu-geometry = <0x0 0x40000000 0x0 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@98c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x0 0x98c000 0x0 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 55 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_rx>; + pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_default_rx>; + pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART1 Instance */ + qupv3_se4_2uart: qcom,qup_uart@990000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x0 0x990000 0x0 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_tx_active>, <&qupv3_se4_2uart_rx_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x99c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@99c000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x99c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART2 Instance */ + qupv3_se8_2uart: qcom,qup_uart@9a0000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x0 0x9a0000 0x0 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_2uart_tx_active>, <&qupv3_se8_2uart_rx_active>; + pinctrl-1 = <&qupv3_se8_2uart_sleep>; + status = "disabled"; + }; +}; + +&uart1 { + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>; + status = "ok"; +}; + #include "sdxkova-usb.dtsi" #include "ipcc-test-sdxkova.dtsi"