diff --git a/Kbuild b/Kbuild
index eef19472..311841fd 100644
--- a/Kbuild
+++ b/Kbuild
@@ -12,6 +12,10 @@ ifeq ($(CONFIG_ARCH_TUNA), y)
 dtbo-y += gpu/tuna-gpu.dtbo
 endif
 
+ifeq ($(CONFIG_ARCH_KERA), y)
+dtbo-y += gpu/kera-gpu.dtbo
+endif
+
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
 clean-files    := *.dtb *.dtbo
diff --git a/bindings/adreno.txt b/bindings/adreno.txt
index 0f5c0311..d2855ed0 100644
--- a/bindings/adreno.txt
+++ b/bindings/adreno.txt
@@ -16,6 +16,7 @@ Required properties:
 			Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target.
 			Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target.
 			Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target.
+			Must include "qcom,adreno-gpu-gen7-17-0" for Kera target.
 			Must include "qcom,adreno-gpu-gen8-6-0" for Tuna target.
 - reg:			Specifies the list of register regions for the device.
 - reg-names:		Resource names used for the register regions specified
diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi
new file mode 100644
index 00000000..bba8f52f
--- /dev/null
+++ b/gpu/kera-gpu-pwrlevels.dtsi
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&msm_gpu {
+	qcom,initial-pwrlevel = <7>;
+
+	/* Power levels */
+	qcom,gpu-pwrlevels {
+		compatible="qcom,gpu-pwrlevels";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Turbo_L1 */
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <1075000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+			qcom,bus-freq-ddr7 = <10>;
+			qcom,bus-min-ddr7 = <10>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <9>;
+			qcom,bus-min-ddr8 = <8>;
+			qcom,bus-max-ddr8 = <10>;
+		};
+
+		/* Turbo */
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <975000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+			qcom,bus-freq-ddr7 = <10>;
+			qcom,bus-min-ddr7 = <10>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <8>;
+			qcom,bus-min-ddr8 = <8>;
+			qcom,bus-max-ddr8 = <9>;
+		};
+
+		/* Nom_L1 */
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <900000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+			qcom,bus-freq-ddr7 = <10>;
+			qcom,bus-min-ddr7 = <9>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <8>;
+			qcom,bus-min-ddr8 = <8>;
+			qcom,bus-max-ddr8 = <8>;
+		};
+
+		/* Nom */
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
+			qcom,gpu-freq = <796000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+			qcom,bus-freq-ddr7 = <10>;
+			qcom,bus-min-ddr7 = <9>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <7>;
+			qcom,bus-min-ddr8 = <6>;
+			qcom,bus-max-ddr8 = <8>;
+		};
+
+		/* SVS_L2 */
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
+			qcom,gpu-freq = <724000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+			qcom,bus-freq-ddr7 = <9>;
+			qcom,bus-min-ddr7 = <8>;
+			qcom,bus-max-ddr7 = <9>;
+
+			qcom,bus-freq-ddr8 = <6>;
+			qcom,bus-min-ddr8 = <5>;
+			qcom,bus-max-ddr8 = <7>;
+		};
+
+		/* SVS_L1 */
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
+			qcom,gpu-freq = <645000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+			qcom,bus-freq-ddr7 = <8>;
+			qcom,bus-min-ddr7 = <7>;
+			qcom,bus-max-ddr7 = <9>;
+
+			qcom,bus-freq-ddr8 = <6>;
+			qcom,bus-min-ddr8 = <5>;
+			qcom,bus-max-ddr8 = <7>;
+		};
+
+		/* SVS */
+		qcom,gpu-pwrlevel@6 {
+			reg = <6>;
+			qcom,gpu-freq = <515000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+			qcom,bus-freq-ddr7 = <6>;
+			qcom,bus-min-ddr7 = <3>;
+			qcom,bus-max-ddr7 = <6>;
+
+			qcom,bus-freq-ddr8 = <4>;
+			qcom,bus-min-ddr8 = <2>;
+			qcom,bus-max-ddr8 = <5>;
+		};
+
+		/* Low_SVS */
+		qcom,gpu-pwrlevel@7 {
+			reg = <7>;
+			qcom,gpu-freq = <345000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+			qcom,bus-freq-ddr7 = <2>;
+			qcom,bus-min-ddr7 = <2>;
+			qcom,bus-max-ddr7 = <6>;
+
+			qcom,bus-freq-ddr8 = <2>;
+			qcom,bus-min-ddr8 = <2>;
+			qcom,bus-max-ddr8 = <4>;
+		};
+
+		/* Low_SVS_D1 */
+		qcom,gpu-pwrlevel@8 {
+			reg = <8>;
+			qcom,gpu-freq = <259000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+			qcom,bus-freq-ddr7 = <2>;
+			qcom,bus-min-ddr7 = <1>;
+			qcom,bus-max-ddr7 = <6>;
+
+			qcom,bus-freq-ddr8 = <2>;
+			qcom,bus-min-ddr8 = <2>;
+			qcom,bus-max-ddr8 = <4>;
+		};
+	};
+};
diff --git a/gpu/kera-gpu.dts b/gpu/kera-gpu.dts
new file mode 100644
index 00000000..5c8ca057
--- /dev/null
+++ b/gpu/kera-gpu.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-kera.h>
+#include <dt-bindings/clock/qcom,gpucc-kera.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,kera.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+#include "kera-gpu.dtsi"
+#include "kera-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kera SoC";
+	compatible = "qcom,kera";
+	qcom,msm-id = <0x293 0x10000>;
+	qcom,board-id = <0 0>;
+};
diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi
new file mode 100644
index 00000000..c1c2eb31
--- /dev/null
+++ b/gpu/kera-gpu.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
+
+&msm_gpu {
+	compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0";
+	status = "ok";
+	reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>,
+		<0x3d61000 0x800>, <0x3d9e000 0x1000>,
+		<0x10048000 0x8000>, <0x10900000 0x80000>,
+		<0x10b05000 0x1000>;
+	reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc",
+		"cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc";
+
+	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "kgsl_3d0_irq";
+
+	clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>,	<&gpucc GPU_CC_AHB_CLK>,
+		<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>;
+	clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb",
+		"gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk";
+
+	qcom,gpu-model = "Adreno716";
+
+	qcom,min-access-length = <32>;
+
+	qcom,ubwc-mode = <4>;
+
+	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+	interconnect-names = "gpu_icc_path";
+
+	qcom,bus-table-cnoc =
+		<0>,   /* Off */
+		<100>; /* On */
+
+	qcom,bus-table-ddr7 =
+		<MHZ_TO_KBPS(0, 4)>,    /*          index=0  */
+		<MHZ_TO_KBPS(200, 4)>,  /*   LowSVS index=1  */
+		<MHZ_TO_KBPS(451, 4)>,  /*   LowSVS index=2  */
+		<MHZ_TO_KBPS(547, 4)>,  /*   LowSVS index=3  */
+		<MHZ_TO_KBPS(681, 4)>,  /*      SVS index=4  */
+		<MHZ_TO_KBPS(768, 4)>,  /*   	SVS index=5  */
+		<MHZ_TO_KBPS(1017, 4)>, /*      SVS index=6  */
+		<MHZ_TO_KBPS(1353, 4)>, /*      NOM index=7  */
+		<MHZ_TO_KBPS(1555, 4)>, /*      NOM index=8  */
+		<MHZ_TO_KBPS(1708, 4)>, /*    TURBO index=9  */
+		<MHZ_TO_KBPS(2092, 4)>; /* TURBO_L1 index=10 */
+
+	qcom,bus-table-ddr8 =
+		<MHZ_TO_KBPS(0, 4)>,    /*          index=0  */
+		<MHZ_TO_KBPS(200, 4)>,  /*   LowSVS index=1  */
+		<MHZ_TO_KBPS(547, 4)>,  /*   LowSVS index=2  */
+		<MHZ_TO_KBPS(1353, 4)>, /*   LowSVS index=3  */
+		<MHZ_TO_KBPS(1555, 4)>, /*      SVS index=4  */
+		<MHZ_TO_KBPS(1708, 4)>, /*      SVS index=5  */
+		<MHZ_TO_KBPS(2092, 4)>, /*      SVS index=6  */
+		<MHZ_TO_KBPS(2736, 4)>, /*      NOM index=7  */
+		<MHZ_TO_KBPS(3187, 4)>, /*    TURBO index=8  */
+		<MHZ_TO_KBPS(3686, 4)>, /*    TURBO index=9  */
+		<MHZ_TO_KBPS(4224, 4)>; /* TURBO_L1 index=10 */
+
+	zap-shader {
+		memory-region = <&gpu_microcode_mem>;
+	};
+
+	qcom,gpu-mempools {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,gpu-mempools";
+
+		/* 4K Page Pool configuration */
+		qcom,gpu-mempool@0 {
+			reg = <0>;
+			qcom,mempool-page-size = <4096>;
+			qcom,mempool-reserved = <2048>;
+		};
+		/* 8K Page Pool configuration */
+		qcom,gpu-mempool@1 {
+			reg = <1>;
+			qcom,mempool-page-size = <8192>;
+			qcom,mempool-reserved = <1024>;
+		};
+		/* 64K Page Pool configuration */
+		qcom,gpu-mempool@2 {
+			reg = <2>;
+			qcom,mempool-page-size = <65536>;
+			qcom,mempool-reserved = <256>;
+		};
+		/* 128K Page Pool configuration */
+		qcom,gpu-mempool@3 {
+			reg = <3>;
+			qcom,mempool-page-size = <131072>;
+			qcom,mempool-reserved = <128>;
+		};
+		/* 256K Page Pool configuration */
+		qcom,gpu-mempool@4 {
+			reg = <4>;
+			qcom,mempool-page-size = <262144>;
+			qcom,mempool-reserved = <80>;
+		};
+		/* 1M Page Pool configuration */
+		qcom,gpu-mempool@5 {
+			reg = <5>;
+			qcom,mempool-page-size = <1048576>;
+			qcom,mempool-reserved = <32>;
+		};
+	};
+};
+
+&soc {
+	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
+		compatible = "qcom,kgsl-smmu-v2";
+		reg = <0x3da0000 0x40000>;
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+
+		gfx3d_user: gfx3d_user {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x0 0x000>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		gfx3d_secure: gfx3d_secure {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x2 0x000>;
+			qcom,iommu-dma = "disabled";
+		};
+	};
+
+	gmu: qcom,gmu@3d68000 {
+		compatible = "qcom,gen7-gmu";
+
+		reg = <0x3d68000 0x37000>, <0xb290000 0x10000>, <0x3d40000 0x10000>;
+		reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
+
+		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+			<0 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		regulator-names = "vddcx", "vdd";
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+		vdd-supply = <&gpu_cc_gx_gdsc>;
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			<&gpucc GPU_CC_CXO_CLK>,
+			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
+			<&gpucc GPU_CC_AHB_CLK>,
+			<&gpucc GPU_CC_HUB_CX_INT_CLK>,
+			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+
+		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+			"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote";
+
+		qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
+					<550000000 RPMH_REGULATOR_LEVEL_SVS>;
+
+		iommus = <&kgsl_smmu 0x5 0x000>;
+		qcom,iommu-dma = "disabled";
+	};
+};