From 458709ab91dc6f638f4b16581a2293f84cdd663e Mon Sep 17 00:00:00 2001 From: Kunal Singh Ranawat Date: Fri, 7 Feb 2025 12:23:47 +0530 Subject: [PATCH] ARM: dts: msm: Add initial device tree for QCS610 LE target Added initial device tree for QCS610 LE target. Change-Id: Ia8b8790fa0916a8a87a5bc696f5b9e23d7e951dc Signed-off-by: Kunal Singh Ranawat --- bindings/arm/msm/msm.yaml | 15 ++ qcom/Makefile | 12 + qcom/platform_map.bzl | 12 + qcom/qcs610-iot-overlay.dts | 15 ++ qcom/qcs610-iot.dtsi | 10 + qcom/qcs610-ipc-overlay.dts | 16 ++ qcom/qcs610-ipc.dtsi | 12 + qcom/qcs610-opk-overlay.dts | 16 ++ qcom/qcs610-opk.dtsi | 14 + qcom/qcs610.dts | 14 + qcom/qcs610.dtsi | 12 + qcom/sm6150.dtsi | 512 ++++++++++++++++++++++++++++++++++++ 12 files changed, 660 insertions(+) create mode 100644 qcom/qcs610-iot-overlay.dts create mode 100644 qcom/qcs610-iot.dtsi create mode 100644 qcom/qcs610-ipc-overlay.dts create mode 100644 qcom/qcs610-ipc.dtsi create mode 100644 qcom/qcs610-opk-overlay.dts create mode 100644 qcom/qcs610-opk.dtsi create mode 100644 qcom/qcs610.dts create mode 100644 qcom/qcs610.dtsi create mode 100644 qcom/sm6150.dtsi diff --git a/bindings/arm/msm/msm.yaml b/bindings/arm/msm/msm.yaml index 996c4289..6eccd379 100644 --- a/bindings/arm/msm/msm.yaml +++ b/bindings/arm/msm/msm.yaml @@ -205,4 +205,19 @@ properties: - qcom,wdp - const: qcom,monacop + - description: Qualcomm Technologies, Inc. QCS610 + items: + - enum: + - qcom,qcs610-iot + - qcom,iot + - qcom,qcs610-ipc + - qcom,ipc + - qcom,qcs610-opk + - qcom,opk + - const: qcom,qcs610 + + - description: Qualcomm Technologies, Inc. SM6150 + items: + - const: qcom,sm6150 + additionalProperties: true diff --git a/qcom/Makefile b/qcom/Makefile index a20c41b7..0336b1b6 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -112,6 +112,18 @@ sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS) $(KE dtb-y += $(sun-dtb-y) +QCS610_BASE_DTB += qcs610.dtb + +QCS610_BOARDS += \ + qcs610-iot-overlay.dtbo \ + qcs610-ipc-overlay.dtbo \ + qcs610-opk-overlay.dtbo + +qcs610-dtb-$(CONFIG_ARCH_SM6150) += \ + $(call add-overlays, $(QCS610_BOARDS),$(QCS610_BASE_DTB)) +qcs610-overlays-dtb-$(CONFIG_ARCH_SM6150) += $(QCS610_BOARDS) $(QCS610_BASE_DTB) +dtb-y += $(qcs610-dtb-y) + PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb PINEAPPLE_APQ_BASE_DTB += pineapplep.dtb pineapplep-v2.dtb diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 91a4156e..b997d990 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -127,6 +127,18 @@ _platform_map = { ], "binary_compatible_with": ["tuna", "kera"], }, + "qcs610": { + "dtb_list": [ + # keep sorted + {"name": "qcs610.dtb"}, + ], + "dtbo_list": [ + # keep sorted + {"name": "qcs610-iot-overlay.dtbo"}, + {"name": "qcs610-ipc-overlay.dtbo"}, + {"name": "qcs610-opk-overlay.dtbo"}, + ], + }, "tuna": { "dtb_list": [ {"name": "tuna.dtb"}, diff --git a/qcom/qcs610-iot-overlay.dts b/qcom/qcs610-iot-overlay.dts new file mode 100644 index 00000000..7d53d124 --- /dev/null +++ b/qcom/qcs610-iot-overlay.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "qcs610-iot.dtsi" +/ { + model = "Qualcomm Technologies, Inc. QCS610 IOT Overlay"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,msm-id = <401 0x0>; + qcom,board-id = <32 0>; +}; diff --git a/qcom/qcs610-iot.dtsi b/qcom/qcs610-iot.dtsi new file mode 100644 index 00000000..26b86790 --- /dev/null +++ b/qcom/qcs610-iot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + model = "Qualcomm Technologies, Inc. QCS610 IOT"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,board-id = <32 0>; +}; diff --git a/qcom/qcs610-ipc-overlay.dts b/qcom/qcs610-ipc-overlay.dts new file mode 100644 index 00000000..554ab2ba --- /dev/null +++ b/qcom/qcs610-ipc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "qcs610-ipc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610 IOT IPC"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,msm-id = <401 0x0>; + qcom,board-id = <32 1>; +}; diff --git a/qcom/qcs610-ipc.dtsi b/qcom/qcs610-ipc.dtsi new file mode 100644 index 00000000..8ed7509e --- /dev/null +++ b/qcom/qcs610-ipc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qcs610-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610 IPC"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,board-id = <32 1>; +}; diff --git a/qcom/qcs610-opk-overlay.dts b/qcom/qcs610-opk-overlay.dts new file mode 100644 index 00000000..a2e0f0b4 --- /dev/null +++ b/qcom/qcs610-opk-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "qcs610-opk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Openkit Overlay"; + compatible = "qcom,qcs610-opk", "qcom,qcs610", "qcom,opk"; + qcom,msm-id = <401 0x0>; + qcom,board-id = <32 3>; +}; diff --git a/qcom/qcs610-opk.dtsi b/qcom/qcs610-opk.dtsi new file mode 100644 index 00000000..3fda344a --- /dev/null +++ b/qcom/qcs610-opk.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. QCS610 IOT"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,board-id = <32 0>; +}; diff --git a/qcom/qcs610.dts b/qcom/qcs610.dts new file mode 100644 index 00000000..ed512c59 --- /dev/null +++ b/qcom/qcs610.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "qcs610.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610 SoC"; + compatible = "qcom,qcs610"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/qcs610.dtsi b/qcom/qcs610.dtsi new file mode 100644 index 00000000..fb33064a --- /dev/null +++ b/qcom/qcs610.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610"; + qcom,msm-name = "QCS610"; + qcom,msm-id = <401 0>; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi new file mode 100644 index 00000000..3bad661d --- /dev/null +++ b/qcom/sm6150.dtsi @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + model = "Qualcomm Technologies, Inc. SM6150"; + compatible = "qcom,sm6150"; + qcom,msm-name = "SM6150"; + qcom,msm-id = <355 0x0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=2M earlycon=msm_geni_serial,0x880000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + + reserved_memory: reserved-memory { }; + + + aliases: aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + cache-size = <0x8000>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + cache-size = <0x8000>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + cache-size = <0x8000>; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + cache-size = <0x8000>; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + cache-size = <0x8000>; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; + cache-size = <0x10000>; + next-level-cache = <&L2_600>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <404>; + cache-size = <0x10000>; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; +}; + + &reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + no-map; + reg = <0x0 0x85e00000 0x0 0x120000>; + }; + + aop_cmd_db: memory@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + sec_apps_mem: sec_apps_region@85fff000 { + no-map; + reg = <0x0 0x85fff000 0x0 0x1000>; + }; + + smem_region: smem@86000000 { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_region: removed_region@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x2d00000>; + }; + + pil_camera_mem: camera_region@8ab00000 { + no-map; + reg = <0x0 0x8ab00000 0x0 0x500000>; + }; + + pil_modem_mem: modem_region@8b000000 { + no-map; + reg = <0x0 0x8b000000 0x0 0x8400000>; + }; + + pil_video_mem: pil_video_region@93400000 { + no-map; + reg = <0x0 0x93400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@93900000 { + no-map; + reg = <0x0 0x93900000 0x0 0x200000>; + }; + + pil_cdsp_mem: cdsp_regions@93b00000 { + no-map; + reg = <0x0 0x93b00000 0x0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@95900000 { + no-map; + reg = <0x0 0x95900000 0x0 0x1e00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@97700000 { + no-map; + reg = <0x0 0x97700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@97710000 { + no-map; + reg = <0x0 0x97710000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@97715000 { + no-map; + reg = <0x0 0x97715000 0x0 0x2000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@9f800000 { + no-map; + reg = <0x0 0x9f800000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + + cont_splash_memory: splash_region { + reg = <0x0 0x9c000000 0x0 0x0f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@9cf00000 { + reg = <0x0 0x9cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x01000000>; + label = "disp_rdump_region"; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + size = <0 0x2800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + }; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + qcom_tzlog: tz-log@146aa720 { + compatible = "qcom,tz-log"; + reg = <0x146aa720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + , + , + ; + + interrupt-names = "l1-l2-faultirq", + "l1-l2-errirq", + "l3-scu-errirq", + "l3-scu-faultirq"; + }; +};