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ARM: dts: msm: Add interconnect voting node for canoe kiwi/peach

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Add the interconnect voting node for canoe kiwi/peach, used
for bus bandwidth voting.

Change-Id: I4c1828ec5d6e8e8d2298f51f926338f977283a7e
CRs-Fixed: 4036509
This commit is contained in:
Srinivas Girigowda
2025-02-06 20:31:25 -08:00
parent 646a3acae6
commit 41f8240269
2 changed files with 93 additions and 1 deletions
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46
canoe-kiwi-cnss.dtsi
View File

@@ -108,6 +108,52 @@
vdd-wlan-supply = <&S7G>;
qcom,vdd-wlan-config = <952000 1100000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 308000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 308000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 308000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 308000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3210000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3210000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 6450000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1610000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"S2J1", "bb",
"S1J1", "bb",

48
canoe-peach-cnss.dtsi
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,canoe.h>
@@ -123,6 +123,52 @@
vdd-wlan-ant-share-supply = <&L3K>;
qcom,vdd-wlan-ant-share-config = <1200000 1200000 0 0 1>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 308000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 308000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 308000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 308000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3210000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3210000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 6450000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1610000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s1j", "bb",
"s2j", "rf",