From 2c1be65d15618f9bc3cb1a665f1c143ee0819b33 Mon Sep 17 00:00:00 2001 From: Megha Byahatti Date: Tue, 17 Dec 2024 14:13:02 +0530 Subject: [PATCH] mmrm: drvier: Add mmrm devicetree support for tuna variant Add mmrm devicetree support for tuna variant Change-Id: I18339a06951c6b562a6b4e3b3b9058599d08540b Signed-off-by: Megha Byahatti --- Kbuild | 6 +++ tuna/tuna-mmrm-test.dts | 20 ++++++++ tuna/tuna-mmrm-test.dtsi | 107 +++++++++++++++++++++++++++++++++++++++ tuna/tuna-mmrm.dts | 20 ++++++++ tuna/tuna-mmrm.dtsi | 54 ++++++++++++++++++++ 5 files changed, 207 insertions(+) create mode 100644 tuna/tuna-mmrm-test.dts create mode 100644 tuna/tuna-mmrm-test.dtsi create mode 100644 tuna/tuna-mmrm.dts create mode 100644 tuna/tuna-mmrm.dtsi diff --git a/Kbuild b/Kbuild index d4bed0d9..ae7a2d3f 100644 --- a/Kbuild +++ b/Kbuild @@ -1,3 +1,9 @@ +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += tuna/tuna-mmrm.dtbo +dtbo-y += tuna/tuna-mmrm-test.dtbo +endif + + ifeq ($(CONFIG_ARCH_SUN), y) dtbo-y += sun/sun-mmrm.dtbo dtbo-y += sun/sun-mmrm-test.dtbo diff --git a/tuna/tuna-mmrm-test.dts b/tuna/tuna-mmrm-test.dts new file mode 100644 index 00000000..de5b9074 --- /dev/null +++ b/tuna/tuna-mmrm-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-mmrm-test.dtsi b/tuna/tuna-mmrm-test.dtsi new file mode 100644 index 00000000..3c46dd09 --- /dev/null +++ b/tuna/tuna-mmrm-test.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,tuna-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_camnoc_rt_axi_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_icp_0_clk_src", + "cam_cc_icp_1_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_ofe_clk_src", + "cam_cc_tfe_0_clk_src", + "cam_cc_tfe_1_clk_src", + "cam_cc_tfe_2_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_cre_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "eva_cc_mvs0_clk_src", + "disp_cc_mdss_mdp_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&evacc EVA_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + /* + * clock_data : domain, clock-ID, + * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO, + * num_hw_blocks, hw_drv_instances, num_pwr_states + */ + clock_data = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_ICP_0_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_ICP_1_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 450000000 575000000 675000000 825000000 825000000 1 0 0>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_OFE_CLK_SRC 436000000 570000000 675000000 757000000 757000000 1 0 0>, + <0x1 CAM_CC_TFE_0_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_TFE_1_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_TFE_2_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 0 0>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 EVA_CC_MVS0_CLK_SRC 350000000 450000000 500000000 550000000 550000000 1 0 0>, + <0x1 DISP_CC_MDSS_MDP_CLK_SRC 207000000 342000000 417000000 535000000 600000000 1 0 0>, + <0x1 VIDEO_CC_MVS0_CLK_SRC 338000000 3360000000 444000000 444000000 533000000 1 0 0>; + }; +}; diff --git a/tuna/tuna-mmrm.dts b/tuna/tuna-mmrm.dts new file mode 100644 index 00000000..0a166cdd --- /dev/null +++ b/tuna/tuna-mmrm.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-mmrm.dtsi b/tuna/tuna-mmrm.dtsi new file mode 100644 index 00000000..098fba51 --- /dev/null +++ b/tuna/tuna-mmrm.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,tuna-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <35652 41157 44827 47711 50332 52429>; + + /* Scaling factors */ + scaling-fact-dyn = <36045 49152 58983 67503 75367 82576>; + scaling-fact-leak = <844760 1055785 1215038 1353974 1492911 1616118>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 4459070 263455 1>, + <0x1 CAM_CC_CSID_CLK_SRC 1795032 131072 3>, + <0x1 CAM_CC_ICP_0_CLK_SRC 353895 17040 1>, + <0x1 CAM_CC_ICP_1_CLK_SRC 253232 17040 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 383386 418120 2>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 35389440 409600 1>, + <0x1 CAM_CC_JPEG_CLK_SRC 770048 26870 4>, + <0x1 CAM_CC_OFE_CLK_SRC 41680896 418120 1>, + <0x1 CAM_CC_TFE_0_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_TFE_1_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_TFE_2_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6554 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11797 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CRE_CLK_SRC 65536 1967 1>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33424 10>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 492831 24249 2>, + + <0x2 EVA_CC_MVS0_CLK_SRC 3723822 105513 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 16117269 346686 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 727974 8127 1>; + }; +};