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ARM: dts: msm: Update DDR bandwidth for sun GMU scaling

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SVS is the highest voltage corner for GMU. The lowest DDR BW
that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX
at a corner high enough such that GMU can run at 650 MHz. This
is to get better GMU performance at no extra power cost.

Change-Id: I919476577e9b2e69161142c93d47e91505ffc222
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
This commit is contained in:
Kamal Agrawal
2024-02-03 16:22:37 +05:30
parent 8687f5ac09
commit 40c568a6d1
1 changed files with 2 additions and 2 deletions
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4
gpu/sun-gpu.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
@@ -171,7 +171,7 @@
qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
<650000000 RPMH_REGULATOR_LEVEL_SVS>;
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(1353, 4)>;
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(1555, 4)>;
iommus = <&kgsl_smmu 0x5 0x000>;
qcom,iommu-dma = "disabled";