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Merge "ARM: dts: msm: Add UFS nodes for kera pre-sil"

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QCTECMDR Service
2024-10-30 23:55:12 -07:00
committed by Gerrit - the friendly Code Review server
parent 8cd5a7442c 3845e9a00a
commit 3fbbd10df2
2 changed files with 167 additions and 0 deletions
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80
qcom/kera-rumi.dtsi
View File

@@ -3,6 +3,9 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/clock/qcom,rpmh.h>
&arch_timer { &arch_timer {
clock-frequency = <500000>; clock-frequency = <500000>;
}; };
@@ -35,6 +38,83 @@
}; };
}; };
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L6B>;
vdda-phy-max-microamp = <211860>;
/*
* Platforms supporting Gear 5 && Rate B require a different
* voltage supply. Check the Power Grid document.
*/
vdda-phy-min-microvolt = <912000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18330>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <1890>;
/* Detect whether RH132 card based sequences to be used */
qcom,soc_emulation_type_addr = <0x1fc8004>;
qcom,soc_emulation_type_bits = <32>;
status = "ok";
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <2>; /* HS Rate-B */
rpm-level = <0>;
spm-level = <0>;
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <800000>;
vccq-supply = <&L1D>;
vccq-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L3G>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&S2B>;
qcom,vccq-parent-max-microamp = <210000>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_PAD_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
qcom,disable-lpm;
status = "ok";
};
&usb0 { &usb0 {
dwc3@a600000 { dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>; usb-phy = <&usb_emuphy>, <&usb_nop_phy>;

87
qcom/kera.dtsi
View File

@@ -18,6 +18,7 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/spmi/spmi.h> #include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/gpio/gpio.h>
/ { / {
model = "Qualcomm Technologies, Inc. Kera"; model = "Qualcomm Technologies, Inc. Kera";
@@ -55,6 +56,7 @@
aliases { aliases {
serial0 = &qupv3_se13_2uart; serial0 = &qupv3_se13_2uart;
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
}; };
cpus { cpus {
@@ -1962,6 +1964,91 @@
status = "disabled"; status = "disabled";
}; };
}; };
ufsphy_mem: ufsphy_mem@1d80000 {
reg = <0x1d80000 0x2000>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_aux_clk", "qref_clk",
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>;
reg-names = "ufs_mem";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_LN_BB_CLK3>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<100000000 403000000>,
<0 0>,
<0 0>,
<100000000 403000000>,
<100000000 403000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
/* set the dependency that smmu being probed before ufs */
depends-on-supply = <&apps_smmu>;
iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "bypass";
dma-coherent;
qcom,bypass-pbl-rst-wa;
qcom,max-cpus = <8>;
reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
status = "disabled";
};
}; };
#include "tuna-gdsc.dtsi" #include "tuna-gdsc.dtsi"