From 3f805a805c9212ccfb1e7a06f88e78e6e69d7df2 Mon Sep 17 00:00:00 2001
From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Date: Tue, 21 Nov 2023 15:31:56 -0800
Subject: [PATCH] ARM: dts: msm: Update the pcie BAR address in ranges property

Update the pcie BAR address in ranges property for sun.

ADSP subsystem is not having access to the previously given
(0x60300000) memory region. So, moving to the lower memory
region to avoid NOC errors for adsp.

Change-Id: Id8223a78cf13d8f2c83095de30b193e85da6829d
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
---
 qcom/sun-pcie.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qcom/sun-pcie.dtsi b/qcom/sun-pcie.dtsi
index 6b2cf7cf..67331637 100644
--- a/qcom/sun-pcie.dtsi
+++ b/qcom/sun-pcie.dtsi
@@ -24,8 +24,8 @@
 
 		#address-cells = <3>;
 		#size-cells = <2>;
-		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
-			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3d00000>;
 
 		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
 				GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH