From 4f5358e026370d5fc2a7e93c6809b3a6df3e1df8 Mon Sep 17 00:00:00 2001 From: Gerrit SelfHelp Service Account Date: Tue, 18 Jul 2023 12:57:46 -0700 Subject: [PATCH 001/274] Initial empty repository From b8a4592a1ba1d24458d1bff1e9826ac5c5fdfb84 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Thu, 24 Aug 2023 13:22:53 -0700 Subject: [PATCH 002/274] ARM: dts: msm: Add devicetree changes for opensource project This chane will migragate all dts and dtsi file to opensourse project CRs-Fixed: 3583121 Change-Id: I837ee52ce68ad23fd5bff8ed69684824c9bfe3f4 Signed-off-by: Soumen Ghosh --- Kbuild | 18 + Makefile | 20 + bengal-camera-sensor-idp.dtsi | 406 ++++ bengal-camera-sensor-qrd.dtsi | 408 ++++ bengal-camera.dtsi | 893 ++++++++ bindings/msm-cam-cci.txt | 1065 ++++++++++ bindings/msm-cam-cdm.txt | 184 ++ bindings/msm-cam-cpas.txt | 595 ++++++ bindings/msm-cam-cre.txt | 163 ++ bindings/msm-cam-csiphy.txt | 175 ++ bindings/msm-cam-custom-hw.txt | 28 + bindings/msm-cam-custom.txt | 31 + bindings/msm-cam-eeprom.txt | 503 +++++ bindings/msm-cam-fd.txt | 154 ++ bindings/msm-cam-icp.txt | 367 ++++ bindings/msm-cam-ife-csid.txt | 147 ++ bindings/msm-cam-isp.txt | 36 + bindings/msm-cam-jpeg.txt | 202 ++ bindings/msm-cam-lrme.txt | 148 ++ bindings/msm-cam-ope.txt | 168 ++ bindings/msm-cam-ppi.txt | 95 + bindings/msm-cam-sfe.txt | 137 ++ bindings/msm-cam-smmu.txt | 147 ++ bindings/msm-cam-tfe-csid.txt | 123 ++ bindings/msm-cam-tfe.txt | 147 ++ bindings/msm-cam-tpg.txt | 137 ++ bindings/msm-cam-vfe.txt | 176 ++ bindings/msm-camera-flash.txt | 132 ++ bindings/msm-camera.txt | 18 + cape-camera-sensor-cdp.dts | 21 + cape-camera-sensor-cdp.dtsi | 798 +++++++ cape-camera-sensor-mtp.dts | 21 + cape-camera-sensor-mtp.dtsi | 879 ++++++++ cape-camera-sensor-qrd.dts | 21 + cape-camera-sensor-qrd.dtsi | 879 ++++++++ cape-camera.dts | 21 + cape-camera.dtsi | 2696 ++++++++++++++++++++++++ config/kalama.mk | 7 + config/parrot.mk | 1 + config/pineapple.mk | 5 + config/waipio.mk | 14 + diwali-camera-sensor-idp.dts | 21 + diwali-camera-sensor-idp.dtsi | 391 ++++ diwali-camera-sensor-qrd.dts | 21 + diwali-camera-sensor-qrd.dtsi | 391 ++++ diwali-camera.dts | 21 + diwali-camera.dtsi | 2308 ++++++++++++++++++++ holi-camera-sensor-cdp.dtsi | 389 ++++ holi-camera-sensor-mtp.dtsi | 459 ++++ holi-camera-sensor-qrd.dtsi | 389 ++++ holi-camera.dtsi | 1063 ++++++++++ kalama-camera-sensor-cdp.dts | 21 + kalama-camera-sensor-cdp.dtsi | 869 ++++++++ kalama-camera-sensor-hdk.dts | 21 + kalama-camera-sensor-hdk.dtsi | 659 ++++++ kalama-camera-sensor-mtp.dts | 21 + kalama-camera-sensor-mtp.dtsi | 867 ++++++++ kalama-camera-sensor-qrd.dts | 21 + kalama-camera-sensor-qrd.dtsi | 661 ++++++ kalama-camera.dts | 21 + kalama-camera.dtsi | 3123 +++++++++++++++++++++++++++ kalama-sg-hhg-camera-sensor.dts | 21 + kalama-sg-hhg-camera-sensor.dtsi | 93 + kalama-sg-hhg-camera.dts | 21 + kona-camera-sensor-cdp.dtsi | 679 ++++++ kona-camera-sensor-mtp.dtsi | 680 ++++++ kona-camera-sensor-qrd.dtsi | 678 ++++++ kona-camera-sensor-xr.dtsi | 691 ++++++ kona-camera.dtsi | 1748 +++++++++++++++ lagoon-camera-sensor-cdp.dtsi | 426 ++++ lagoon-camera-sensor-mtp.dtsi | 426 ++++ lagoon-camera.dtsi | 1484 +++++++++++++ lahaina-camera-sensor-cdp.dtsi | 751 +++++++ lahaina-camera-sensor-hdk.dtsi | 181 ++ lahaina-camera-sensor-mtp.dtsi | 751 +++++++ lahaina-camera-sensor-qrd.dtsi | 529 +++++ lahaina-camera.dtsi | 1935 +++++++++++++++++ lito-camera-sensor-cdp.dtsi | 298 +++ lito-camera-sensor-mtp.dtsi | 298 +++ lito-camera-sensor-qrd.dtsi | 677 ++++++ lito-camera.dtsi | 1623 ++++++++++++++ lito-v2-camera.dtsi | 21 + parrot-camera.dts | 21 + parrot-camera.dtsi | 1195 +++++++++++ pineapple-camera-sensor-cdp.dts | 21 + pineapple-camera-sensor-cdp.dtsi | 765 +++++++ pineapple-camera-sensor-mtp.dts | 21 + pineapple-camera-sensor-mtp.dtsi | 765 +++++++ pineapple-camera-sensor-qrd.dts | 21 + pineapple-camera-sensor-qrd.dtsi | 765 +++++++ pineapple-camera-v2.dts | 22 + pineapple-camera-v2.dtsi | 15 + pineapple-camera.dts | 21 + pineapple-camera.dtsi | 3384 ++++++++++++++++++++++++++++++ scuba-camera-sensor-idp.dtsi | 318 +++ scuba-camera.dtsi | 773 +++++++ shima-camera-sensor-idp.dtsi | 550 +++++ shima-camera-sensor-qrd.dtsi | 387 ++++ shima-camera.dtsi | 1910 +++++++++++++++++ waipio-camera-overlay-v2.dts | 116 + waipio-camera-sensor-cdp.dts | 21 + waipio-camera-sensor-cdp.dtsi | 798 +++++++ waipio-camera-sensor-mtp.dts | 21 + waipio-camera-sensor-mtp.dtsi | 879 ++++++++ waipio-camera-sensor-qrd.dts | 21 + waipio-camera-sensor-qrd.dtsi | 610 ++++++ waipio-camera.dts | 21 + waipio-camera.dtsi | 2698 ++++++++++++++++++++++++ yupik-camera.dtsi | 1651 +++++++++++++++ 109 files changed, 55724 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 bengal-camera-sensor-idp.dtsi create mode 100644 bengal-camera-sensor-qrd.dtsi create mode 100644 bengal-camera.dtsi create mode 100644 bindings/msm-cam-cci.txt create mode 100644 bindings/msm-cam-cdm.txt create mode 100644 bindings/msm-cam-cpas.txt create mode 100644 bindings/msm-cam-cre.txt create mode 100644 bindings/msm-cam-csiphy.txt create mode 100644 bindings/msm-cam-custom-hw.txt create mode 100644 bindings/msm-cam-custom.txt create mode 100644 bindings/msm-cam-eeprom.txt create mode 100644 bindings/msm-cam-fd.txt create mode 100644 bindings/msm-cam-icp.txt create mode 100644 bindings/msm-cam-ife-csid.txt create mode 100644 bindings/msm-cam-isp.txt create mode 100644 bindings/msm-cam-jpeg.txt create mode 100644 bindings/msm-cam-lrme.txt create mode 100644 bindings/msm-cam-ope.txt create mode 100644 bindings/msm-cam-ppi.txt create mode 100644 bindings/msm-cam-sfe.txt create mode 100644 bindings/msm-cam-smmu.txt create mode 100644 bindings/msm-cam-tfe-csid.txt create mode 100644 bindings/msm-cam-tfe.txt create mode 100644 bindings/msm-cam-tpg.txt create mode 100644 bindings/msm-cam-vfe.txt create mode 100644 bindings/msm-camera-flash.txt create mode 100644 bindings/msm-camera.txt create mode 100644 cape-camera-sensor-cdp.dts create mode 100644 cape-camera-sensor-cdp.dtsi create mode 100644 cape-camera-sensor-mtp.dts create mode 100644 cape-camera-sensor-mtp.dtsi create mode 100644 cape-camera-sensor-qrd.dts create mode 100644 cape-camera-sensor-qrd.dtsi create mode 100644 cape-camera.dts create mode 100644 cape-camera.dtsi create mode 100644 config/kalama.mk create mode 100644 config/parrot.mk create mode 100644 config/pineapple.mk create mode 100644 config/waipio.mk create mode 100644 diwali-camera-sensor-idp.dts create mode 100644 diwali-camera-sensor-idp.dtsi create mode 100644 diwali-camera-sensor-qrd.dts create mode 100644 diwali-camera-sensor-qrd.dtsi create mode 100644 diwali-camera.dts create mode 100644 diwali-camera.dtsi create mode 100644 holi-camera-sensor-cdp.dtsi create mode 100644 holi-camera-sensor-mtp.dtsi create mode 100644 holi-camera-sensor-qrd.dtsi create mode 100644 holi-camera.dtsi create mode 100644 kalama-camera-sensor-cdp.dts create mode 100644 kalama-camera-sensor-cdp.dtsi create mode 100644 kalama-camera-sensor-hdk.dts create mode 100644 kalama-camera-sensor-hdk.dtsi create mode 100644 kalama-camera-sensor-mtp.dts create mode 100644 kalama-camera-sensor-mtp.dtsi create mode 100644 kalama-camera-sensor-qrd.dts create mode 100644 kalama-camera-sensor-qrd.dtsi create mode 100644 kalama-camera.dts create mode 100644 kalama-camera.dtsi create mode 100644 kalama-sg-hhg-camera-sensor.dts create mode 100644 kalama-sg-hhg-camera-sensor.dtsi create mode 100644 kalama-sg-hhg-camera.dts create mode 100644 kona-camera-sensor-cdp.dtsi create mode 100644 kona-camera-sensor-mtp.dtsi create mode 100644 kona-camera-sensor-qrd.dtsi create mode 100644 kona-camera-sensor-xr.dtsi create mode 100644 kona-camera.dtsi create mode 100644 lagoon-camera-sensor-cdp.dtsi create mode 100644 lagoon-camera-sensor-mtp.dtsi create mode 100644 lagoon-camera.dtsi create mode 100644 lahaina-camera-sensor-cdp.dtsi create mode 100644 lahaina-camera-sensor-hdk.dtsi create mode 100644 lahaina-camera-sensor-mtp.dtsi create mode 100644 lahaina-camera-sensor-qrd.dtsi create mode 100644 lahaina-camera.dtsi create mode 100644 lito-camera-sensor-cdp.dtsi create mode 100644 lito-camera-sensor-mtp.dtsi create mode 100644 lito-camera-sensor-qrd.dtsi create mode 100644 lito-camera.dtsi create mode 100644 lito-v2-camera.dtsi create mode 100644 parrot-camera.dts create mode 100644 parrot-camera.dtsi create mode 100644 pineapple-camera-sensor-cdp.dts create mode 100644 pineapple-camera-sensor-cdp.dtsi create mode 100644 pineapple-camera-sensor-mtp.dts create mode 100644 pineapple-camera-sensor-mtp.dtsi create mode 100644 pineapple-camera-sensor-qrd.dts create mode 100644 pineapple-camera-sensor-qrd.dtsi create mode 100644 pineapple-camera-v2.dts create mode 100644 pineapple-camera-v2.dtsi create mode 100644 pineapple-camera.dts create mode 100644 pineapple-camera.dtsi create mode 100644 scuba-camera-sensor-idp.dtsi create mode 100644 scuba-camera.dtsi create mode 100644 shima-camera-sensor-idp.dtsi create mode 100644 shima-camera-sensor-qrd.dtsi create mode 100644 shima-camera.dtsi create mode 100644 waipio-camera-overlay-v2.dts create mode 100644 waipio-camera-sensor-cdp.dts create mode 100644 waipio-camera-sensor-cdp.dtsi create mode 100644 waipio-camera-sensor-mtp.dts create mode 100644 waipio-camera-sensor-mtp.dtsi create mode 100644 waipio-camera-sensor-qrd.dts create mode 100644 waipio-camera-sensor-qrd.dtsi create mode 100644 waipio-camera.dts create mode 100644 waipio-camera.dtsi create mode 100644 yupik-camera.dtsi diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..8b848089 --- /dev/null +++ b/Kbuild @@ -0,0 +1,18 @@ +# Use current $(MSM_ARCH) to set config/ makefile path +CAMERA_TARGET_MKFILE_PATH := $(CAMERA_DEVICETREE_ROOT)/config/$(MSM_ARCH).mk +# Check to see if current target makefile exists +CAMERA_TARGET_EXISTS := $(or $(and $(wildcard $(CAMERA_TARGET_MKFILE_PATH)),y),n) + +# Since Kernel SI can support multiple ARCH's this allows only the current selected target ARCH +# to compile. +ifeq ($(CAMERA_TARGET_EXISTS), y) +include $(CAMERA_TARGET_MKFILE_PATH) +else +# Print a warning but do not throw an error to allow bring-up of new targets! +$(warning [$(MODNAME)] $(MSM_ARCH) is not a valid target, make sure config\ folder contains a makefile named $(MSM_ARCH).mk) +$(warning [$(MODNAME)] driver is NOT being enabled!) +endif + +always-y := $(dtbo-y) $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..ba9b560b --- /dev/null +++ b/Makefile @@ -0,0 +1,20 @@ + +CAMERA_DEVICETREE_ROOT=$(KERNEL_SRC)/$(M) +CAMERA_KERNEL_ROOT=$(CAMERA_DEVICETREE_ROOT)/../../opensource/camera-kernel + +KBUILD_OPTIONS += CAMERA_DEVICETREE_ROOT=$(KERNEL_SRC)/$(M) +KBUILD_OPTIONS += KBUILD_DTC_INCLUDE=$(CAMERA_KERNEL_ROOT) +KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=. +KBUILD_OPTIONS += KERNEL_ROOT=$(ROOT_DIR)/$(KERNEL_DIR) +KBUILD_OPTIONS += MODNAME=camera-devicetree + +all: dtbs + +dtbs: + $(MAKE) -C $(KERNEL_SRC) M=$(M) dtbs $(KBUILD_OPTIONS) + +modules_install: + $(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi new file mode 100644 index 00000000..666f24cd --- /dev/null +++ b/bengal-camera-sensor-idp.dtsi @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/bengal-camera-sensor-qrd.dtsi b/bengal-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..d4851b67 --- /dev/null +++ b/bengal-camera-sensor-qrd.dtsi @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi new file mode 100644 index 00000000..7f00f40d --- /dev/null +++ b/bengal-camera.dtsi @@ -0,0 +1,893 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; + reg = <0x05C52000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L18A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; + reg = <0x05C53000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x53000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L18A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; + reg = <0x05C54000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x54000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L18A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_2_CLK>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci-v1.2", "qcom,cci", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 22 0>, + <&tlmm 23 0>, + <&tlmm 29 0>, + <&tlmm 30 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x400 0x000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x000>, + <&apps_smmu 0x840 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "ope", "ope-cdm"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas", "simple-bus"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x11000 0x13000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "minsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "cci0", + "csid0", "csid1", "csid2", "tfe0", + "tfe1", "tfe2", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe2_all_wr: tfe2-all-wr { + cell-index = <8>; + node-name = "tfe2-all-wr"; + client-name = "tfe2"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_0"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-client-names = "tfe0", "tfe1", "tfe2"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_0"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <240000000 0 0 0 256000000 0>, + <384000000 0 0 0 460800000 0>, + <426400000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + cam_hw_pid = <4>; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <240000000 0 0 0 256000000 0>, + <384000000 0 0 0 460800000 0>, + <426400000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + cam_hw_pid = <5>; + status = "ok"; + }; + + cam_tfe_csid2: qcom,tfe_csid2@5c7c000 { + cell-index = <2>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c7c000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x7c000 0x11000 0x13000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>; + clock-rates = + <240000000 0 0 0 256000000 0>, + <384000000 0 0 0 460800000 0>, + <426400000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_tfe2: qcom,tfe2@5c7c000 { + cell-index = <2>; + compatible = "qcom,tfe530"; + reg-names = "tfe2"; + reg = <0x5c7c000 0x5000>; + reg-cam-base = <0x7c000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + cam_hw_pid = <6>; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpg101"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg1@5c68000 { + cell-index = <1>; + compatible = "qcom,tpg101"; + reg-names = "tpg0", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0x1270>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 200000000 0>, + <171428571 266600000 0>, + <240000000 465000000 0>, + <240000000 580000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; +}; diff --git a/bindings/msm-cam-cci.txt b/bindings/msm-cam-cci.txt new file mode 100644 index 00000000..f84f2c34 --- /dev/null +++ b/bindings/msm-cam-cci.txt @@ -0,0 +1,1065 @@ +* Qualcomm Technologies, Inc. MSM CCI + +CCI (Camera Control Interface) is module that is use for camera sensor module +I2C communication. + +======================= +Required Node Structure +======================= +The camera CCI node must be described in two levels of device nodes. The +first level describe the overall CCI node structure. Second level nodes +describe camera sensor submodule nodes which is using CCI for +i2c communication. + +====================================== +First Level Node - CCI device +====================================== + +- cell-index: cci hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cci". + In case of cci version 1.2, + use "qcom,cci-v1.2". + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the cci operating in + compatible mode. + +- reg-names + Usage: required + Value type: + Definition: Should specify relevant names to each + reg property defined. + +- reg-cam-base + Usage: required + Value type: + Definition: List of bases. + +- interrupt-names + Usage: required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: required + Value type: + Definition: Interrupt associated with CCI HW. + +- gpios + Usage: required + Value type: + Definition: should specify the gpios to be used for the CCI. + +- gpio-req-tbl-num + Usage: required + Value type: + Definition: should specify the gpio table index. + +- gpio-req-tbl-flags + Usage: required + Value type: + Definition: should specify the gpio functions. + +- gpio-req-tbl-label + Usage: required + Value type: + Definition: should specify the gpio labels in + gpio-req-tbl-num property (in the same order) + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CCI HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clock rates in Hz for CCI HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- clocks + Usage: required + Value type: + Definition: all clock phandle and source clocks. + +- src-clock-name + Usage: required + Value type: + Definition: name for the source clock. + +- regulator-names + Usage: required + Value type: + Definition: name of the voltage regulators required for the device. + +- gdscr-supply + Usage: required + Value type: + Definition: should contain gdsr regulator used for cci clocks. + +- pctrl-idx-mapping + Usage: required + Value type: + Definition: should contain master index associated with cci hw. + +- pctrl-map-names + Usage: required + Value type: + Definition: should contain pctrl-idx-mapping associated mapping name. + +- mmagic-supply + Usage: optional + Value type: + Definition: should contain mmagic regulator used for mmagic clocks. + +========================= +CCI clock settings +========================= +- I2c speed settings (*) + Usage: required + Definition: List of i2c rates for CCI HW. + - i2c_freq_100Khz + Definition: qcom,i2c_standard_mode - node should contain clock settings for + 100Khz + - i2c_freq_400Khz + Definition: qcom,i2c_fast_mode - node should contain clock settings for + 400Khz + - i2c_freq_custom + Definition: qcom,i2c_custom_mode - node can contain clock settings for + frequencies other than 100Khz and 400Khz which is specific to usecase. + Currently it has settings for 375Khz. + - i2c_freq_1Mhz + Definition: qcom,i2c_fast_plus_mode - node should contain clock + settings for 1Mhz +* if speed settings is not defined the low level driver can use "i2c_freq_custom" +like default + + - hw-thigh + Definition: should contain high period of the SCL clock in terms of CCI clock cycle + - hw-tlow + Definition: should contain high period of the SCL clock in terms of CCI clock cycle + - hw-tsu-sto + Definition: should contain setup time for STOP condition + - hw-tsu-sta + Definition: should contain setup time for Repeated START condition + - hw-thd-dat + Definition: should contain hold time for the data + - hw-thd-sta + Definition: should contain hold time for START condition + - hw-tbuf + Definition: should contain free time between a STOP and a START condition + - hw-scl-stretch-en + Definition: should contain enable or disable clock stretching + - hw-trdhld + Definition: should contain internal hold time for SDA + - hw-tsp + Definition: should contain filtering of glitches + +Example: + + qcom,cci@0xfda0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xfda0c000 0x300>; + reg-names = "cci"; + interrupts = <0 50 0>; + interrupt-names = "cci"; + clock-names = "camnoc_axi_clk", "soc_ahb_clk", + "slow_ahb_src_clk", "cpas_ahb_clk", + "cci_clk", "cci_clk_src"; + clock-rates = <0 0 80000000 0 0 37500000>; + clock-cntl-level = "turbo"; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + gpio-tbl-num = <0 1 2 3>; + gpio-tbl-flags = <1 1 1 1>; + gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + i2c_freq_100Khz: qcom,i2c_standard_mode { + hw-thigh = <78>; + hw-tlow = <114>; + hw-tsu-sto = <28>; + hw-tsu-sta = <28>; + hw-thd-dat = <10>; + hw-thd-sta = <77>; + hw-tbuf = <118>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <1>; + status = "ok"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + hw-thigh = <20>; + hw-tlow = <28>; + hw-tsu-sto = <21>; + hw-tsu-sta = <21>; + hw-thd-dat = <13>; + hw-thd-sta = <18>; + hw-tbuf = <25>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + status = "ok"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + hw-thigh = <15>; + hw-tlow = <28>; + hw-tsu-sto = <21>; + hw-tsu-sta = <21>; + hw-thd-dat = <13>; + hw-thd-sta = <18>; + hw-tbuf = <25>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + status = "ok"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <19>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + +======================================= +Second Level Node - CAM SENSOR MODULES +======================================= + +======================================= +CAM SENSOR RESOURCE MANAGER +======================================= +Camera Sensor Resource manager node contains properties of shared camera +sensor resource. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-res-mgr". + +- gpios-shared + Usage: optional + Value type: + Definition: should contain the gpios which are used by two or more + cameras, and these cameras may be opened together. + +- gpios-shared-pinctrl + Usage: optional + Value type: + Definition: should contain the pinctrl gpios which are used by two or more + cameras, and these cameras may be opened together. + +- shared-pctrl-gpio-names + Usage: optional + Value type: + Definition: List of names to assign the shared pinctrl gpio defined in + shared-pinctrl-gpios entry + e.g "mclk0", "xyz" + +- pinctrl-names + Usage: optional + Value type: + Definition: List of names to assign the shared pin state defined in pinctrl device node + string should follow the strict rule which needs to start with shared-pinctrl-gpio-names + and followed by "_active" and "_suspend" + e.g. "mclk0_active", "mclk0_suspend", "xyz_active", "xyz_suspend" + +- pinctrl-<0..n> + Usage: optional + Value type: + Definition: Lists phandles each pointing to the pin configuration node within a pin + controller. These pin configurations are installed in the pinctrl device node. + + +============================== +CAMERA IMAGE SENSOR/TPG MODULE +============================== +Image sensor node contains properties of camera image sensor + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-sensor". + +- cell-index: cci hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the cci operating in + compatible mode. + +- cci-device + Usage: required + Value type: + Definition: should contain i2c device id to be used for this camera + sensor + +- cci-master + Usage: required + Value type: + Definition: should contain i2c master id to be used for this camera + sensor + - 0 -> MASTER 0 + - 1 -> MASTER 1 + +- csiphy-sd-index + Usage: required + Value type: + Definition: should contain csiphy instance that will used to + receive sensor data (0, 1, 2, 3). + +- cam_vdig-supply + Usage: required + Value type: + Definition: should contain regulator from which digital voltage is + supplied + +- cam_vana-supply + Usage: required + Value type: + Definition: should contain regulator from which analog voltage is + supplied + +- cam_vio-supply + Usage: required + Value type: + Definition: should contain regulator from which IO voltage is supplied + +- cam_bob-supply + Usage: optional + Value type: + Definition: should contain regulator from which BoB voltage is supplied + +- i3c-target + Usage: required for I3C targets + Value type: + Definition: A boolean flag to indicate the target being used as an pure I3C + target on a I3C bus. + +- i3c-i2c-target + Usage: required for I3C and I2C mixed bus targets + Value type: + Definition: A boolean flag to indicate the target being used as a I3C as + well as I2C target on a I3C bus. + +- regulator-names + Usage: required + Value type: + Definition: should contain names of all regulators needed by this + sensor + +- rgltr-cntrl-support + Usage: required + Value type: + Definition: This property is required if the sw control regulator parameters + e.g. rgltr-min-voltage + +- aon-camera-id + Usage: required + Value type: + Definition: This property is required if the sensor is being shared for Main and AON camera. + It refers to index of AON Camera. + e.g. aon-camera-id = ; + +- rgltr-min-voltage + Usage: required + Value type: + Definition: should contain minimum voltage level for regulators mentioned + in regulator-names property (in the same order) + +- rgltr-max-voltage + Usage: required + Value type: + Definition: should contain maximum voltage level for regulators mentioned + in regulator-names property (in the same order) + +- rgltr-load-current + Usage: required + Value type: + Definition: should contain optimum voltage level for regulators mentioned + in regulator-names property (in the same order) + +- sensor-position-roll + Usage: required + Value type: + Definition: should contain sensor rotational angle with respect to axis of + reference. i.e. 0, 90, 180, 360 + +- sensor-position-pitch + Usage: required + Value type: + Definition: should contain sensor rotational angle with respect to axis of + reference. i.e. 0, 90, 180, 360 + +- sensor-position-yaw + Usage: required + Value type: + Definition: should contain sensor rotational angle with respect to axis of + reference. i.e. 0, 90, 180, 360 + +- qcom,secure + Usage: optional + Value type: + Definition: should be enabled to operate the camera in secure mode + +- gpio-no-mux + Usage: optional + Value type: + Definition: should contain field to indicate whether gpio mux table is + available. i.e. 1 if gpio mux is not available, 0 otherwise + +- cam_vaf-supply + Usage: optional + Value type: + Definition: should contain regulator from which AF voltage is supplied + +- pwm-switch + Usage: optional + Value type: + Definition: This property is required for regulator to switch into PWM mode. + +- gpios + Usage: required + Value type: + Definition: should contain phandle to gpio controller node and array of + #gpio-cells specifying specific gpio (controller specific) + +- gpio-reset + Usage: required + Value type: + Definition: should contain index to gpio used by sensors reset_n + +- gpio-standby + Usage: optional + Value type: + Definition: should contain index to gpio used by sensors standby_n + +- gpio-vio + Usage: optional + Value type: + Definition: should contain index to gpio used by sensors io vreg enable + +- gpio-vana + Usage: optional + Value type: + Definition: should contain index to gpio used by sensors analog vreg enable + +- gpio-vdig + Usage: optional + Value type: + Definition: should contain index to gpio used by sensors digital vreg enable + +- gpio-vaf + Usage: optional + Value type: + Definition: should contain index to gpio used by sensors af vreg enable + +- gpio-af-pwdm + Usage: optional + Value type: + Definition: should contain index to gpio used by sensors af pwdm_n + +- gpio-req-tbl-num + Usage: optional + Value type: + Definition: should contain index to gpios specific to this sensor + +- gpio-req-tbl-flags + Usage: optional + Value type: + Definition: should contain direction of gpios present in + gpio-req-tbl-num property (in the same order) + +- gpio-req-tbl-label + Usage: optional + Value type: + Definition: should contain name of gpios present in + gpio-req-tbl-num property (in the same order) + +- gpio-set-tbl-num + Usage: optional + Value type: + Definition: should contain index of gpios that need to be + configured by msm + +- gpio-set-tbl-flags + Usage: optional + Value type: + Definition: should contain value to be configured for the gpios + present in gpio-set-tbl-num property (in the same order) + +- gpio-set-tbl-delay + Usage: optional + Value type: + Definition: should contain amount of delay after configuring + gpios as specified in gpio_set_tbl_flags property (in the same order) + +- actuator-src + Usage: optional + Value type: + Definition: if auto focus is supported by this sensor, this + property should contain phandle of respective actuator node + +- led-flash-src + Usage: optional + Value type: + Definition: if LED flash is supported by this sensor, this + property should contain phandle of respective LED flash node + +- qcom,vdd-cx-supply + Usage: optional + Value type: + Definition: should contain regulator from which cx voltage is supplied + +- qcom,vdd-cx-name + Usage: optional + Value type: + Definition: should contain names of cx regulator + +- eeprom-src + Usage: optional + Value type: + Definition: if eeprom memory is supported by this sensor, this + property should contain phandle of respective eeprom nodes + +- ois-src + Usage: optional + Value type: + Definition: if optical image stabilization is supported by this sensor, + this property should contain phandle of respective ois node + +- ir-led-src + Usage: optional + Value type: + Definition: if ir led is supported by this sensor, this property + should contain phandle of respective ir-led node + +- qcom,ir-cut-src + Usage: optional + Value type: + Definition: if ir cut is supported by this sensor, this property + should contain phandle of respective ir-cut node + +- qcom,special-support-sensors + Usage: required + Value type: + Definition: if only some special sensors are supported + on this board, add sensor name in this property. + +- use-shared-clk + Usage: optional + Value type: + Definition: It is booloean property. This property is required + if the clk is shared clk between different sensor and ois, if this + device need to be opened together. + +- clock-rates + Usage: required + Value type: + Definition: clock rate in Hz. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- clock-cntl-support + Usage: optional + Value type: + Definition: Says whether clock control support is present or not + +- clocks + Usage: required + Value type: + Definition: all clock phandle and source clocks. + +- clock-control + Usage: optional + Value type: + Definition: The valid fields are "NO_SET_RATE", "INIT_RATE" and + "SET_RATE". "NO_SET_RATE" the corresponding clock is enabled without setting + the rate assuming some other driver has already set it to appropriate rate. + "INIT_RATE" clock rate is not queried assuming some other driver has set + the clock rate and ispif will set the the clock to this rate. + "SET_RATE" clock is enabled and the rate is set to the value specified + in the property clock-rates. + +============================= +ACTUATOR MODULE +============================= + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,actuator". + +- cell-index: cci hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the cci operating in + compatible mode. + +- cci-device + Usage: required + Value type: + Definition: should contain i2c device id to be used for this camera + sensor + +- cci-master + Usage: required + Value type: + Definition: should contain i2c master id to be used for this camera + sensor + - 0 -> MASTER 0 + - 1 -> MASTER 1 + +- cam_vaf-supply + Usage: required + Value type: + Definition: should contain regulator from which AF voltage is supplied + +- regulator-names + Usage: required + Value type: + Definition: should contain names of all regulators needed by this + actuator. i.e. "cam_vaf" + +- aon-user + Usage: optional + Value type: + Definition: AON support detection + +- i3c-target + Usage: required for I3C Targets + Value type: + Definition: A boolean flag to indicate the target being used as an pure I3C + target on a I3C bus. + +- rgltr-cntrl-support + Usage: optional + Value type: + Definition: It is booloean property. This property is required + if the code and regulator control parameters e.g. rgltr-min-voltage + +- rgltr-min-voltage + Usage: optional + Value type: + Definition: should contain minimum voltage level in mcrovolts + for regulators mentioned in regulator-names property (in the same order) + +- rgltr-max-voltage + Usage: optional + Value type: + Definition: should contain maximum voltage level in mcrovolts + for regulators mentioned in regulator-names property (in the same order) + +- rgltr-load-current + Usage: optional + Value type: + Definition: should contain the maximum current in microamps + required from the regulators mentioned in the regulator-names property + (in the same order). + +============================= +OIS MODULE +============================= + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,ois". + +- cell-index: cci hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the cci operating in + compatible mode. + +- cci-device + Usage: required + Value type: + Definition: should contain i2c device id to be used for this camera + sensor + +- cci-master + Usage: required + Value type: + Definition: should contain i2c master id to be used for this camera + sensor + - 0 -> MASTER 0 + - 1 -> MASTER 1 + +- cam_vaf-supply + Usage: required + Value type: + Definition: should contain regulator from which AF voltage is supplied + +- regulator-names + Usage: required + Value type: + Definition: should contain names of all regulators needed by this + actuator. i.e. "cam_vaf" + +- rgltr-cntrl-support + Usage: optional + Value type: + Definition: It is booloean property. This property is required + if the code and regulator control parameters e.g. rgltr-min-voltage + +- i3c-target + Usage: required for I3C Targets + Value type: + Definition: A boolean flag to indicate the target being used as an pure I3C + target on a I3C bus. + +- rgltr-min-voltage + Usage: optional + Value type: + Definition: should contain minimum voltage level in mcrovolts + for regulators mentioned in regulator-names property (in the same order) + +- rgltr-max-voltage + Usage: optional + Value type: + Definition: should contain maximum voltage level in mcrovolts + for regulators mentioned in regulator-names property (in the same order) + +- rgltr-load-current + Usage: optional + Value type: + Definition: should contain the maximum current in microamps + required from the regulators mentioned in the regulator-names property + (in the same order). + +- use-shared-clk + Usage: optional + Value type: + Definition: This property is required if the clk is shared clk between different + sensor and ois, if this device need to be opened together. + +============================= +I3C ID Table MODULE +============================= + +- i3c-sensor-id-table + Usage: optional + Value type: + Definition: Contains entries for supported I3C Sensors. One entry of this property is + of form . + +- i3c-eeprom-id-table + Usage: optional + Value type: + Definition: Contains entries for supported I3C EEPROMs. One entry of this property is + of form . + +- i3c-actuator-id-table + Usage: optional + Value type: + Definition: Contains entries for supported I3C actuators. One entry of this property is + of form . + +- i3c-ois-id-table + Usage: optional + Value type: + Definition: Contains entries for supported I3C OIS slaves. One entry of this property is + of form . + + +Example: +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi8994_flash0 &pmi8994_flash1>; + torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + switch-source = <&pmi8998_switch>; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0766>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; +}; + +&cam_cci0 { + actuator0: qcom,actuator0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pmi8998_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + ois0: qcom,ois0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pmi8998_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + gpios-shared = <18 19>; + gpios-shared-pinctrl = <408 409>; + shared-pctrl-gpio-names = "mclk0", "mclk1"; + pinctrl-names = "mclk0_active", "mclk0_suspend", + "mclk1_active", "mclk1_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend>; + pintcrl-2 = <&cam_sensor_mclk1_active>; + pinctrl-3 = <&cam_sensor_mclk1_suspend>; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + secure = <1>; + led-flash-src = <&led_flash0>; + actuator-src = <&actuator0>; + ois-src = <&ois0>; + eeprom-src = <&eeprom0>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009l_l1>; + cam_vana-supply = <&pm8009l_l5>; + cam_bob-supply = <&pm8150l_bob>; + cam_clk-supply = <&tital_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 80 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + use-shared-clk; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + clock-cntl-leveli = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-tpg0 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&i3c0 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <100000>; + compatible = "qcom,geni-i3c", "simple-bus"; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator1@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator", "qcom,actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7N>; + i3c-i2c-target; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom2@50 { + cell-index = <2>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom", "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-i2c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <2>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/bindings/msm-cam-cdm.txt b/bindings/msm-cam-cdm.txt new file mode 100644 index 00000000..0e188fec --- /dev/null +++ b/bindings/msm-cam-cdm.txt @@ -0,0 +1,184 @@ +* Qualcomm Technologies, Inc. MSM Camera CDM + +CDM (Camera Data Mover) is module intended to provide means for fast programming +camera registers and lookup tables. + +======================= +Required Node Structure +======================= +CDM Interface node takes care of the handling has HW nodes and provide interface +for camera clients. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-cdm-intf". + +- label + Usage: required + Value type: + Definition: Should be "cam-cdm-intf". + +- num-hw-cdm + Usage: required + Value type: + Definition: Number of supported HW blocks. + +- cdm-client-names + Usage: required + Value type: + Definition: List of Clients supported by CDM interface. + +Example: + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpeg-dma", + "jpeg", + "fd"; + }; + +======================= +Required Node Structure +======================= +CDM HW node provides interface for camera clients through +to CDM interface node. + +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam170-cpas-cdm0", "qcom,cam480-cpas-cdm0", + "qcom,cam480-cpas-cdm1", "qcom,cam480-cpas-cdm2", "qcom,cam-cpas-cdm1_0", + "qcom,cam-cpas-cdm1_1", "qcom,cam-cpas-cdm1_2", "qcom,cam-ife-cdm1_2", + "qcom,cam-cpas-cdm2_0", "qcom,cam-ope-cdm2_0", "qcom,cam-cpas-cdm2_1", + "qcom,cam-rt-cdm2_1" or "qcom,cam-ope-cdm2_1" + +- label + Usage: required + Value type: + Definition: Should be "cpas-cdm", "ife-cdm", or "rt-cdm". + +- reg-names + Usage: required + Value type: + Definition: Name of the register resources. + +- reg + Usage: required + Value type: + Definition: Register values. + +- reg-cam-base + Usage: required + Value type: + Definition: Offset of the register space compared to + to Camera base register space. + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt associated with CDM HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for CDM HW. + +- camss-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CDM HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for CDM HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. + +- cdm-client-names + Usage: required + Value type: + Definition: List of Clients supported by CDM HW node. + +- config-fifo + Usage: required + Value type: + Definition: Flag to let driver know whether to load fifo depths + from property fifo-depths or not. + +- fifo-depths + Usage: required + Value type: + Definition: List of fifo depths supported by device. + +- single-context-cdm + Usage: required + Value type: + Definition: Flag to indicate that the CDM is being used in single + context mode. + +- nrt-device + Usage: optional + Value type: + Definition: Flag to indicate whether this is non real time device. + +Example: + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm0"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + interrupts = <0 461 0>; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "soc_ahb_clk", + "titan_top_ahb_clk", + "cam_axi_clk", + "camcc_slow_ahb_clk_src", + "cpas_top_ahb_clk", + "camnoc_axi_clk"; + clocks = <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + qcom,clock-rates = <0 80000000 80000000 80000000 80000000 80000000>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + single-context-cdm; + status = "ok"; + }; diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt new file mode 100644 index 00000000..33c70f51 --- /dev/null +++ b/bindings/msm-cam-cpas.txt @@ -0,0 +1,595 @@ +* Qualcomm Technologies, Inc. MSM Camera CPAS + +The MSM camera CPAS device provides dependency definitions for +enabling Camera CPAS HW and provides the Client definitions +for all HW blocks that use CPAS driver for BW voting. These +definitions consist of various properties that define the list +of clients supported, AHB, AXI master-slave IDs used for BW +voting. + +======================= +Required Node Structure +======================= +The camera CPAS device must be described in five levels. The first level has +general description of cpas including compatibility, interrupts, power info +etc. +The second level deals with information related to CPAS clients and how +the BW should be calculated. For simplicity in BW vote consolidation, the +grouping of granular votes pertaining to CPAS clients is represented as nodes +at four CAMNOC levels. The nodes at a particular level have some common +properties such as traffic merge type which indicates whether the votes at a +node have to be summed up, sum divided by two or taken max of all. CAMNOC Level +zero node usually represents granular vote info for clients. CAMNOC Level one +represents nodes which are clubbed together by arbiter in CAMNOC diagram. CAMNOC +Level two represents consolidated read and write nodes for RT and NRT paths. +CAMNOC Level three provides axi port information and these have nodes where all +paths from clients eventually converge according to their properties. This +includes master-slave IDs, ab, ib values for mnoc, camnoc bus interface + +================================== +First Level Node - CAM CPAS device +================================== +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-cpas". + +- label + Usage: required + Value type: + Definition: Should be "cpas". + +- arch-compat + Usage: required + Value type: + Definition: Should be "cpas_top" or "camss_top". + +- reg-names + Usage: required + Value type: + Definition: Name of the register resources. + +- reg + Usage: required + Value type: + Definition: Register values. + +- reg-cam-base + Usage: required + Value type: + Definition: Offset of the register space compared to + to Camera base register space. + +- cam_hw_fuse + Usage: optional + Value type: + Definition: List of fuse based features and respective fuse info. + fuse_id: fuse id for each features + fuse_address: fuse register io address + fuse_mask: fuse mask for the fuse registers + fuse_type: fuse feature is enable, disable or value type + hw_map: Hw map of the feature, set bit positions which HWs are + supported for that feature. Use 0xFF if all HWs supported + + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt associated with CAMNOC HW. + +- qcom,cpas-hw-ver + Usage: required + Value type: + Definition: CAM HW Version information. + +- camnoc-axi-min-ib-bw + Usage: optional + Value type: + Definition: Min camnoc axi bw for the given target. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for CPAS HW. + +- camss-vdd-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CPAS HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for CPAS HW. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. + +- qcom,cam-cx-ipeak + Usage: required + Value type: + Definition: Camera Cx Ipeak ID. + +- control-camnoc-axi-clk + Usage: optional + Value type: + Definition: Bool property specifying whether to control camnoc axi + clock from cpas driver. + +- camnoc-bus-width + Usage: required if control-camnoc-axi-clk is enabled + Value type: + Definition: camnoc bus width. + +- camnoc-axi-clk-bw-margin-perc + Usage: optional + Value type: + Definition: Percentage value to be added to camnoc bw while calculating + camnoc axi clock frequency. + +- rpmh-bcm-info + Usage: optional + Value type: + Definition: Rpmh bcm register map + idx: Total number of BCMs + bcm_fe: First BCM FE (front-end) register offset. + bcm_be: First BCM BE (back-end) register offset. + ddr_idx: DDR BCM index + mmnoc_idx: MMNOC BCM index + +- qcom,msm-bus,name +- qcom,msm-bus,num-cases +- qcom,msm-bus,num-paths +- qcom,msm-bus,vectors-KBps + Please refer Documentation/devicetree/bindings/arm/msm/msm_bus.txt + for the properties above. + +- vdd-corners + Usage: required + Value type: + Definition: List of vdd corners to map for ahb level. + +- vdd-corner-ahb-mapping + Usage: required + Value type: + Definition: List of ahb level strings corresponds to vdd-corners. + Supported strings: suspend, svs, nominal, turbo + +- client-id-based + Usage: required + Value type: + Definition: Bool property specifying whether CPAS clients are ID based. + +- client-names + Usage: required + Value type: + Definition: List of Clients supported by CPAS. + +- client-bus-camnoc-based + Usage: optional + Value type: + Definition: Bool property specifying whether Clients are connected + through CAMNOC for AXI access. + +- sys-cache-names + Usage: optional + Value type: + Definition: last level cache info for camera. Specifies the type + of cache; small or large. Small cache is around 256K and its + read property is self-evict. Large cache is around 3.2M which + is pre-determined for a target based on the calulations done + for concerned use cases. Large cache is Non-self evict. + UIDs value and their usage can vary from target to target. + for example; same UID 38 is used as small and large in different + targets. + +- sys-cache-uids + Usage: optional + Value type: + Definition: Client ID for camera caches. ID is used to differentiate + the property of the cache like being Forget, Dealloc. + +- enable-smart-qos + Usage: optional + Value type: + Definition: Bool property specifying whether Smart Qos feature is enabled. + +- enable-cam-drv + Usage: optional + Value type: + Definition: Bit mask value specifying the DRV features enabled. + Supported: CAM_DDR_DRV + Please refer dt-bindings/msm-camera.h for all supported + definitions. + +- rt-wr-priority-min + Usage: optional + Value type: + Definition: Minimum priority value for rt write NIUs. + +- rt-wr-priority-max + Usage: optional + Value type: + Definition: Maximum priority value for rt write NIUs. + +- rt-wr-priority-clamp + Usage: optional + Value type: + Definition: Clamp priority value for rt write NIUs. + +- rt-wr-slope-factor + Usage: optional + Value type: + Definition: Slope factor value for rt write NIUs. Take in percentages + to avoid confusion, such as take value 100 for 1, take value 70 for 0.7. + +- rt-wr-leaststressed-clamp-threshold + Usage: optional + Value type: + Definition: Least stressed clamp threshold value for rt write NIUs. + +- rt-wr-moststressed-clamp-threshold + Usage: optional + Value type: + Definition: Most stressed clamp threshold value for rt write NIUs. + +- rt-wr-highstress-indicator-threshold + Usage: optional + Value type: + Definition: High stress indicator threshold value for rt write NIUs. + Take in percentages to avoid confusion, such as take value 100 for 1, + take value 50 for 0.5. If the buf bw ratio for a NIU is larger than + high stress indicator threshold, this NIU is more stressed. + +- rt-wr-lowstress-indicator-threshold + Usage: optional + Value type: + Definition: Low stress indicator threshold value for rt write NIUs. + Take in percentages to avoid confusion. + +- rt-wr-bw-ratio-scale-factor + Usage: optional + Value type: + Definition: BW ratio scale factor value for rt write NIUs. + +- domain-id + Usage: optional + Value type: + Definition: List of mapping between domain types and their IDs. + See dt-bindings/msm-camera.h for definitions of + supported domain types. + +- domain-id-support-clks + Usage: optional + Value type: + Definition: Clocks needed to be turned on for domain-id support. + Note that this property builds on top of clock-names-option, + clocks-option, clock-rates-option and shared-clks-option + (if any of these clocks are shared), so the associated + properties for those need to be included for this + property to work. + +=================================================================== +Third Level Node - CAMNOC Level nodes +=================================================================== +- level-index + Usage: required + Value type: + Definition: Number representing level index for ndoes at current CAMNOC level + +- camnoc-max-needed + Usage: optional + Value type: + Definition: Bool property for all votes at current level to be taken maximum + for CAMNOC BW calculation. + +=================================================================== +Fourth Level Node - Generic CAMNOC node properties +=================================================================== +- cell-index + Usage: required + Value type: + Definition: Unique index of node to be used by CPAS driver. + +- node-name + Usage: required + Value type: + Definition: Unique name representing this node. + +- path-data-type + Usage: required if a CAMNOC Level 0 Node + Value type: + Definition: Type of path data for a specific client. + Supported : CAM_CPAS_PATH_DATA_IFE_LINEAR, CAM_CPAS_PATH_DATA_ALL, etc. + Please refer dt-bindings/msm-camera.h for all supported + definitions. + +- path-transaction-type + Usage: required if a CAMNOC Level 0 Node + Value type: + Definition: Type of path transaction for a specific client. + Supported : CAM_CPAS_TRANSACTION_READ, CAM_CPAS_TRANSACTION_WRITE + +- client-name + Usage: required if a CAMNOC Level 0 Node + Value type: + Definition: Name of the client with above properties. + Supported : From "client-names" property in CPAS node + +- constituent-paths + Usage: optional, applicable only to CAMNOC Level 0 Nodes + Value type: + Definition: List of constituents of path data type of current node. + Supported : CAM_CPAS_PATH_DATA_IFE_VID, CAM_CPAS_PATH_DATA_IFE_DISP, etc. + Please refer dt-bindings/msm-camera.h for all supported + definitions. + +- drv-voting-index + Usage: optional, applicable only to CAMNOC Level 0 Nodes + Value type: + Definition: Voting index pointing to Bus Ids for Camera DRV (HLOS DRV by default). + Supported : CAM_CPAS_PORT_DRV_0, CAM_CPAS_PORT_DRV_1, etc. + Please refer dt-bindings/msm-camera.h for all supported + definitions. + +- traffic-merge-type + Usage: required if NOT a CAMNOC Level 0 Node + Value type: + Definition: Type of traffic merge for that node. + Supported : CAM_CPAS_TRAFFIC_MERGE_SUM, CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE. + +- parent-node + Usage: required for all except CAMNOC Level 3 Nodes + Value type: + Definition: Parent node of this node. Parent node must be at least + one level above the current level. + +- rt-wr-niu + Usage: optional + Value type: + Definition: Bool property representing whether this node represents a + Real Time Write NIU node. + +- niu-size + Usage: optional + Value type: + Definition: Size of NIU represented by this node. + +- priority-lut-low-offset + Usage: optional + Value type: + Definition: Priority lut low register offset of NIU represented by this node. + +- priority-lut-high-offset + Usage: optional + Value type: + Definition: Priority lut high register offset of NIU represented by this node. + +- bus-width-factor + Usage: optional + Value type: + Definition: For bus width factor consideration in CAMNOC BW calculation + +- qcom,axi-port-name + Usage: required at CAMNOC Level 3 + Value type: + Definition: Name of the AXI Port. + +- ib-bw-voting-needed + Usage: optional + Value type: + Definition: Bool property indicating axi port requires instantaneous bandwidth + +- rt-axi-port + Usage: optional + Value type: + Definition: Bool property indicating whether this axi port represents + a real time port. + +=================================================================== +Fifth Level Node - CAM AXI Bus Properties +=================================================================== +- qcom,msm-bus,name +- qcom,msm-bus,num-cases +- qcom,msm-bus,num-paths +- qcom,msm-bus,vectors-KBps + Please refer Documentation/devicetree/bindings/arm/msm/msm_bus.txt + for the properties above. + +- qcom,msm-bus-vector-dyn-vote + Usage: optional + Value type: + Definition: Bool property specifying whether this bus client + is dynamic vote based. + +Example: + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x5000>; + reg-cam-base = <0x40000 0x42000>; + cam_hw_fuse = , + ; + interrupt-names = "cpas_camnoc"; + interrupts = <0 459 0>; + qcom,cpas-hw-ver = <0x170100>; /* Titan v170 v1.0.0 */ + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "camnoc_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "slow_ahb_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + /* domain-id-support-clks property dependent on below clock option properties */ + clock-names-option = "cam_icp_clk", + "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + domain-id = , + ; + clock-rates = <0 0 0 0 80000000 0>; + clock-cntl-level = "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <10>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", + "csid4", "csid5", "csid6", + "ife0", "ife1", "ife2", "ife3", "custom0", + "ipe0", "cam-cdm-intf0", "cpas-cdm0", "cpas-cdm1", + "cpas-cdm2", + "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "fd0"; + sys-cache-names = "small-1", "large-1", "large-2", "large-3", "large-4"; + sys-cache-uids = <34 38 50 51 52>; + enable-smart-qos; + rt-wr-priority-min = <3>; + rt-wr-priority-max = <6>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <100>; + rt-wr-leaststressed-clamp-threshold = <7>; + rt-wr-moststressed-clamp-threshold = <7>; + rt-wr-highstress-indicator-threshold = <100>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + enable-cam-drv; + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <175>; + priority-lut-low-offset = <0x5830>; + priority-lut-high-offset = <0x5834>; + }; + }; + level0-nodes { + level-index = <0>; + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <16>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_wr0>; + }; + }; + }; + }; diff --git a/bindings/msm-cam-cre.txt b/bindings/msm-cam-cre.txt new file mode 100644 index 00000000..b85228b7 --- /dev/null +++ b/bindings/msm-cam-cre.txt @@ -0,0 +1,163 @@ +* Qualcomm Technologies, Inc. MSM Camera CRE + +The cre device node has properties defined to hint the driver +about the number of CRE nodes available during the +probe sequence. Each node has multiple properties defined +for interrupts, clocks and regulators. + +======================= +Required Node Structure +======================= +CRE root interface node takes care of the handling account for number +of CRE devices present on the hardware. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-cre". + +- compat-hw-name + Usage: required + Value type: + Definition: Should be "qcom,cre". + +- num-cre + Usage: required + Value type: + Definition: Number of supported CRE HW blocks. + +Example: + qcom,cam-cre { + compatible = "qcom,cam-cre"; + compat-hw-name = "qcom,cre"; + num-cre = <2>; + status = "ok"; + }; + +======================= +Required Node Structure +======================= +CRE Node provides interface for Image Control Processor driver +about the CRE register map, interrupt map, clocks, regulators. + +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cre". + +- reg-names + Usage: optional + Value type: + Definition: Name of the register resources. + +- reg + Usage: optional + Value type: + Definition: Register values. + +- reg-cam-base + Usage: optional + Value type: + Definition: Register values. + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt associated with CRE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for CRE HW. + +- camss-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CDM HW. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for CDM HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: lowsvs, svs, svs_l1, nominal, turbo. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +Examples: +qcom,cam-cre { + compatible = "qcom,cam-cre"; + compat-hw-name = "qcom,cre"; + num-cre = <1>; + status = "ok"; +}; + +cre: qcom,cre@ac00000 { + cell-index = <0>; + compatible = "qcom,cre"; + reg = + <0xFA000 0x400>, + <0xFA400 0xB0>, + <0xFAB00 0x300>; + reg-names = + "cre_top", + "cre_bus_rd", + "cre_bus_wr"; + reg-cam-base = <0xFA000 0xFA400 0xFAB00>; + interrupts = ; + interrupt-names = "cre"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cre_ahb_clk", + "cre_clk_src", + "cre_clk"; + clocks = + <&gcc GCC_CAMSS_CRE_AHB_CLK>, + <&gcc GCC_CAMSS_CRE_CLK_SRC>, + <&gcc GCC_CAMSS_CRE_CLK>; + + clock-rates = + <80000000 30000000 30000000>, + <80000000 41000000 41000000>, + <80000000 46000000 46000000>, + <80000000 60000000 60000000>, + <80000000 70000000 70000000>; + + clock-cntl-level = "lowsvs", "maxsvs", "svs", "nom", "turbo"; + src-clock-name = "cre_clk_src"; + status = "ok"; +}; diff --git a/bindings/msm-cam-csiphy.txt b/bindings/msm-cam-csiphy.txt new file mode 100644 index 00000000..b6fc719d --- /dev/null +++ b/bindings/msm-cam-csiphy.txt @@ -0,0 +1,175 @@ +* Qualcomm Technologies, Inc. MSM CSI Phy + +======================= +Required Node Structure +======================= +The camera CSIPHY node must be described in First level of device nodes. The +first level describe the overall CSIPHY node structure. + +====================================== +First Level Node - CSIPHY device +====================================== +- cell-index: csiphy hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,csiphy-v1.0", + "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1", + "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", + "qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy-v2.1.0", + "qcom,csiphy-v1.2.4", "qcom,csiphy-v1.2.5", "qcom,csiphy". + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the csiphy operating in + compatible mode. + +- reg-names + Usage: required + Value type: + Definition: Should specify relevant names to each + reg property defined. + +- reg-cam-base + Usage: required + Value type: + Definition: offset of CSIPHY in camera hw block + +- interrupts + Usage: required + Value type: + Definition: Interrupt associated with CCI HW. + +- interrupt-names + Usage: required + Value type: + Definition: Name of the interrupt. + +- regulator-names + Usage: required + Value type: + Definition: name of the voltage regulators required for the device. + +- gdscr-supply + Usage: required + Value type: + Definition: should contain gdsr regulator used for CSIPHY clocks. + +- mipi-csi-vdd-supply + Usage: required + Value type: + Definition: should contain phandle for mipi-csi-vdd regulator used for + CSIPHY device. + +- csi-vdd-xxx-supply + Usage: required + Value type: + Definition: should contain phandles for csi-vdd-1p2 and csi-vdd-0p9 + regulators used for CSIPHY. + +- csi-vdd-voltage + Usage: required + Value type: + Definition: should contain required voltage for csi-vdd supply + for CSIPHY. + +- rgltr-cntrl-support + Usage: required + Value type: + Definition: Flag to indicate whether regulator control support is + enabled or not. + +- rgltr-min-voltage + Usage: required + Value type: + Definition: should contain required min voltage for gdsr, csi-vdd-1p2 + and csi-vdd-0p9 supply for CSIPHY. + +- rgltr-max-voltage + Usage: required + Value type: + Definition: should contain required max voltage for gdsr, csi-vdd-1p2 + and csi-vdd-0p9 supply for CSIPHY. + +- rgltr-load-current + Usage: required + Value type: + Definition: should contain peak current for gdsr, csi-vdd-1p2 + and csi-vdd-0p9 supply for CSIPHY. + +- rgltr-enable-sync + Usage: required + Value type: + Definition: Decides whether regulator enable should be done in sync + for all the csiphys together or not. + +- clocks + Usage: required + Value type: + Definition: all clock phandle and source clocks. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CSIPHY HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-rates + Usage: required + Value type: + Definition: List of clock rates in Hz for CSIPHY HW. + +- shared-clks + Usage: optional + Value type: + Definition: List of 0 or 1 values indicating whether shared clk or not. + +Example: + +cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = < 0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "csiphy0"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + shared-clks = <1 0 0 0>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + status = "ok"; +}; diff --git a/bindings/msm-cam-custom-hw.txt b/bindings/msm-cam-custom-hw.txt new file mode 100644 index 00000000..61125d0c --- /dev/null +++ b/bindings/msm-cam-custom-hw.txt @@ -0,0 +1,28 @@ +* Qualcomm Technologies, Inc. MSM Camera Custom HW + +Camera Custom device provides the definitions for enabling +the custom hardware. It also provides the functions for the client +to control the Custom hardware. + +======================= +Required Node Structure +======================= +The Custom device is described in one level of the device node. + +====================================== +First Level Node - CAM Custom device +====================================== +Required properties: +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + driver. e.g. "qcom,cam_custom_hw_sub_mod". + +Example: + + qcom,cam-custom-hw { + compatible = "qcom,cam_custom_hw_sub_mod"; + arch-compat = "custom"; + status = "ok"; + }; diff --git a/bindings/msm-cam-custom.txt b/bindings/msm-cam-custom.txt new file mode 100644 index 00000000..8c5cc614 --- /dev/null +++ b/bindings/msm-cam-custom.txt @@ -0,0 +1,31 @@ +* Qualcomm Technologies, Inc. MSM Camera Custom + +The MSM camera Custom driver provides the definitions for enabling +the Camera custom hadware. It provides the functions for the Client to +control the custom hardware. + +======================= +Required Node Structure +======================= +The camera Custom device is described in one level of device node. + +================================== +First Level Node - CAM CUSTOM device +================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-custom". + +- arch-compat + Usage: required + Value type: + Definition: Should be "custom". + +Example: + + qcom,cam-custom { + compatible = "qcom,cam-custom"; + arch-compat = "custom"; + status = "ok"; + }; diff --git a/bindings/msm-cam-eeprom.txt b/bindings/msm-cam-eeprom.txt new file mode 100644 index 00000000..d692385b --- /dev/null +++ b/bindings/msm-cam-eeprom.txt @@ -0,0 +1,503 @@ +* Qualcomm Technologies, Inc. MSM EEPROM + +EEPROM is a one time programmed(OTP) device that stores the calibration data +use for camera sensor. It may either be integrated in the sensor module or in +the sensor itself. As a result, the power, clock and GPIOs may be the same as +the camera sensor. The following describes the page block map, power supply, +clock, GPIO and power on sequence properties of the EEPROM device. + +======================================================= +Required Node Structure if probe happens from userspace +======================================================= +The EEPROM device is described in one level of the device node. + +====================================== +First Level Node - CAM EEPROM device +====================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,eeprom". + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg + Usage: required + Value type: + Definition: Register values. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for EEPROM HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- rgltr-cntrl-support + Usage: required + Value type: + Definition: This property specifies if the regulator control is supported + e.g. rgltr-min-voltage. + +- rgltr-min-voltage + Usage: required + Value type: + Definition: should contain minimum voltage level for regulators + mentioned in regulator-names property. + +- rgltr-max-voltage + Usage: required + Value type: + Definition: should contain maximum voltage level for regulators + mentioned in regulator-names property. + +- rgltr-load-current + Usage: required + Value type: + Definition: should contain the maximum current in microamps required for + the regulators mentioned in regulator-names property. + +- gpio-no-mux + Usage: required + Value type: + Definition: should specify the gpio mux type. + +- gpios + Usage: required + Value type: + Definition: should specify the gpios to be used for the eeprom. + +- gpio-reset + Usage: required + Value type: + Definition: should specify the reset gpio index. + +- gpio-standby + Usage: required + Value type: + Definition: should specify the standby gpio index. + +- gpio-req-tbl-num + Usage: required + Value type: + Definition: should specify the gpio table index. + +- gpio-req-tbl-flags + Usage: required + Value type: + Definition: should specify the gpio functions. + +- gpio-req-tbl-label + Usage: required + Value type: + Definition: should specify the gpio labels. + +- sensor-position + Usage: required + Value type: + Definition: should contain the mount angle of the camera sensor. + +- cci-device + Usage: required + Value type: + Definition: should contain i2c device id to be used for this camera + sensor + +- cci-master + Usage: required + Value type: + Definition: should contain i2c master id to be used for this camera + sensor. + +- sensor-mode + Usage: required + Value type: + Definition: should contain sensor mode supported. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for EEPROM HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for EEPROM HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: says what all different clock levels eeprom node has. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +Example: + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8998_l5>; + cam_vio-supply = <&pm8998_lvs1>; + regulator-names = "cam_vdig", "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 0>; + rgltr-max-voltage = <1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + +======================================================= +Required Node Structure if probe happens from kernel +======================================================= +The EEPROM device is described in one level of the device node. + +====================================== +First Level Node - CAM EEPROM device +====================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,eeprom". + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg + Usage: required + Value type: + Definition: Register values. + +- qcom,eeprom-name + Usage: required + Value type: + Definition: Name of the EEPROM HW. + +- qcom,slave-addr + Usage: required + Value type: + Definition: Slave address of the EEPROM HW. + +- qcom,num-blocks + Usage: required + Value type: + Definition: Total block number that eeprom contains. + +- qcom,pageX + Usage: required + Value type: + Definition: List of values specifying page size, start address, + address type, data, data type, delay in ms. + size 0 stand for non-paged. + +- qcom,pollX + Usage: required + Value type: + Definition: List of values specifying poll size, poll reg address, + address type, data, data type, delay in ms. + size 0 stand for not used. + +- qcom,memX + Usage: required + Value type: + Definition: List of values specifying memory size, start address, + address type, data, data type, delay in ms. + size 0 stand for not used. + +- qcom,saddrX + Usage: required + Value type: + Definition: property should specify the slave address for block (%d). + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for EEPROM HW. + +- qcom,cmm-data-support + Usage: required + Value type: + Definition: Camera MultiModule data capability flag.. + +- qcom,cmm-data-compressed + Usage: required + Value type: + Definition: Camera MultiModule data compression flag. + +- qcom,cmm-data-offset + Usage: required + Value type: + Definition: Camera MultiModule data start offset. + +- qcom,cmm-data-size + Usage: required + Value type: + Definition: Camera MultiModule data size. + +- qcom,cam-power-seq-type + Usage: required + Value type: + Definition: should specify the power on sequence types. + +- qcom,cam-power-seq-val + Usage: required + Value type: + Definition: should specify the power on sequence values. + +- qcom,cam-power-seq-cfg-val + Usage: required + Value type: + Definition: should specify the power on sequence config values. + +- qcom,cam-power-seq-delay + Usage: required + Value type: + Definition: should specify the power on sequence delay time in ms. + +- spiop-read + Usage: required + Value type: + Definition: this array provides SPI read operation related data. + +- spiop-readseq + Usage: required + Value type: + Definition: this array provides SPI read sequence operation realted data. + +- spiop-queryid + Usage: required + Value type: + Definition: this array provides SPI query eeprom id operation related data. + +- spiop-pprog: + Usage: required + Value type: + Definition: this array provides SPI page program operation related data. + +- spiop-wenable + Usage: required + Value type: + Definition: this array provides SPI write enable operation related data. + +- spiop-readst + Usage: required + Value type: + Definition: this array provides SPI read destination operation related data. + +- spiop-erase + Usage: required + Value type: + Definition: this array provides SPI erase operation related data. + +- eeprom-idx + Usage: required + Value type: + Definition: this array provides eeprom id realted data. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- rgltr-cntrl-support + Usage: required + Value type: + Definition: This property specifies if the regulator control is supported + e.g. rgltr-min-voltage. + +- rgltr-min-voltage + Usage: required + Value type: + Definition: should contain minimum voltage level for regulators + mentioned in regulator-names property. + +- rgltr-max-voltage + Usage: required + Value type: + Definition: should contain maximum voltage level for regulators + mentioned in regulator-names property. + +- rgltr-load-current + Usage: required + Value type: + Definition: should contain the maximum current in microamps required for + the regulators mentioned in regulator-names property. + +- gpio-no-mux + Usage: required + Value type: + Definition: should specify the gpio mux type. + +- gpios + Usage: required + Value type: + Definition: should specify the gpios to be used for the eeprom. + +- gpio-reset + Usage: required + Value type: + Definition: should specify the reset gpio index. + +- gpio-standby + Usage: required + Value type: + Definition: should specify the standby gpio index. + +- gpio-req-tbl-num + Usage: required + Value type: + Definition: should specify the gpio table index. + +- gpio-req-tbl-flags + Usage: required + Value type: + Definition: should specify the gpio functions. + +- gpio-req-tbl-label + Usage: required + Value type: + Definition: should specify the gpio labels. + +- sensor-position + Usage: required + Value type: + Definition: should contain the mount angle of the camera sensor. + +- cci-device + Usage: required + Value type: + Definition: should contain i2c device id to be used for this camera + sensor + +- cci-master + Usage: required + Value type: + Definition: should contain i2c master id to be used for this camera + sensor. + +- sensor-mode + Usage: required + Value type: + Definition: should contain sensor mode supported. + +- clock-cntl-level + Usage: required + Value type: + Definition: says what all different clock levels eeprom node has. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for EEPROM HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for EEPROM HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +Example: + + eeprom0: qcom,eeprom0 { + cell-index = <0>; + reg = <0x0>; + qcom,eeprom-name = "msm_eeprom"; + eeprom-id0 = <0xF8 0x15>; + eeprom-id1 = <0xEF 0x15>; + eeprom-id2 = <0xC2 0x36>; + eeprom-id3 = <0xC8 0x15>; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0x60>; + qcom,num-blocks = <2>; + qcom,page0 = <1 0x100 2 0x01 1 1>; + qcom,poll0 = <0 0x0 2 0 1 1>; + qcom,mem0 = <0 0x0 2 0 1 0>; + qcom,page1 = <1 0x0200 2 0x8 1 1>; + qcom,pageen1 = <1 0x0202 2 0x01 1 10>; + qcom,poll1 = <0 0x0 2 0 1 1>; + qcom,mem1 = <32 0x3000 2 0 1 0>; + qcom,saddr1 = <0x62>; + qcom,cmm-data-support; + qcom,cmm-data-compressed; + qcom,cmm-data-offset = <0>; + qcom,cmm-data-size = <0>; + spiop-read = <0x03 3 0 0 0>; + spiop-readseq = <0x03 3 0 0 0>; + spiop-queryid = <0x90 3 0 0 0>; + spiop-pprog = <0x02 3 0 3 100>; + spiop-wenable = <0x06 0 0 0 0>; + spiop-readst = <0x05 0 0 0 0>; + spiop-erase = <0x20 3 0 10 100>; + qcom,cam-power-seq-type = "sensor_vreg", + "sensor_vreg", "sensor_clk", + "sensor_gpio", "sensor_gpio"; + qcom,cam-power-seq-val = "cam_vdig", + "cam_vio", "sensor_cam_mclk", + "sensor_gpio_reset", + "sensor_gpio_standby"; + qcom,cam-power-seq-cfg-val = <1 1 24000000 1 1>; + qcom,cam-power-seq-delay = <1 1 5 5 10>; + cam_vdig-supply = <&pm8998_l5>; + cam_vio-supply = <&pm8998_lvs1>; + regulator-names = "cam_vdig", "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 0>; + rgltr-max-voltage = <1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-cntl-level = "turbo"; + clock-names = "cam_clk"; + clock-rates = <24000000>; + }; diff --git a/bindings/msm-cam-fd.txt b/bindings/msm-cam-fd.txt new file mode 100644 index 00000000..51b0baba --- /dev/null +++ b/bindings/msm-cam-fd.txt @@ -0,0 +1,154 @@ +* Qualcomm Technologies, Inc. MSM Camera FD + +The MSM camera Face Detection device provides dependency definitions +for enabling Camera FD HW. MSM camera FD is implemented in multiple +device nodes. The root FD device node has properties defined to hint +the driver about the FD HW nodes available during the probe sequence. +Each node has multiple properties defined for interrupts, clocks and +regulators. + +======================= +Required Node Structure +======================= +FD root interface node takes care of the handling Face Detection high level +driver handling and controls underlying FD hardware present. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-fd". + +- compat-hw-name + Usage: required + Value type: + Definition: Should be "qcom,fd". + +- num-fd + Usage: required + Value type: + Definition: Number of supported FD HW blocks. + +Example: + qcom,cam-fd { + compatible = "qcom,cam-fd"; + compat-hw-name = "qcom,fd"; + num-fd = <1>; + }; + +======================= +Required Node Structure +======================= +FD Node provides interface for Face Detection hardware driver +about the device register map, interrupt map, clocks, regulators. + +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be one of "qcom,fd41", "qcom,fd501", + "qcom,fd600". + +- reg-names + Usage: optional + Value type: + Definition: Name of the register resources. + +- reg + Usage: optional + Value type: + Definition: Register values. + +- reg-cam-base + Usage: optional + Value type: + Definition: Offset of the register space compared to + to Camera base register space. + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt line associated with FD HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for FD HW. + +- camss-vdd-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for FD HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks required for FD HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. + +Examples: + cam_fd: qcom,fd@ac5a000 { + cell-index = <0>; + compatible = "qcom,fd600"; + reg-names = "fd_core", "fd_wrapper"; + reg = <0xac5a000 0x1000>, + <0xac5b000 0x400>; + reg-cam-base = <0x5a000 0x5b000>; + interrupt-names = "fd"; + interrupts = <0 462 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "fd_core_clk_src", + "fd_core_clk", + "fd_core_uar_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>, + <&clock_camcc CAM_CC_FD_CORE_CLK>, + <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>; + src-clock-name = "fd_core_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 0 0 0 0 400000000 0 0>; + }; diff --git a/bindings/msm-cam-icp.txt b/bindings/msm-cam-icp.txt new file mode 100644 index 00000000..aada7cc7 --- /dev/null +++ b/bindings/msm-cam-icp.txt @@ -0,0 +1,367 @@ +* Qualcomm Technologies, Inc. MSM Camera ICP + +The MSM camera ICP devices are implemented multiple device nodes. +The root icp device node has properties defined to hint the driver +about the number of ICP, IPE and BPS nodes available during the +probe sequence. Each node has multiple properties defined +for interrupts, clocks and regulators. icp_v1 and icp_v2 are names +corresponding to a5 and lx7 processors respectively. + +======================= +Required Node Structure +======================= +ICP root interface node takes care of the handling account for number +of A5, LX7, IPE and BPS devices present on the hardware. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-icp". + +- compat-hw-name + Usage: required + Value type: + Definition: Should be "qcom,icp", "qcom,ipe0", + "qcom,ipe1" or "qcom,bps". + +- num-icp + Usage: required + Value type: + Definition: Number of supported icp processors. ICP can either be a5 or lx7. + +- num-ipe + Usage: required + Value type: + Definition: Number of supported IPE HW blocks. + +- num-bps + Usage: required + Value type: + Definition: Number of supported BPS HW blocks. + +Example: +qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", "qcom,ipe0", + "qcom,ipe0", "qcom,bps"; + num-icp = <1>; + num-ipe = <2>; + num-bps = <1>; + status = "ok"; +}; + +======================= +Required Node Structure +======================= +A5/LX7/IPE/BPS Node's provides interface for Image Control Processor driver +about the A5/LX7 register map, interrupt map, clocks, regulators +and name of firmware image. + +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-a5", "qcom,cam-lx7", + "qcom,cam-ipe", "qcom,cam-ipe680", "qcom,cam-bps" or + "qcom,cam-bps680". + +- icp-version + Usage: required + Value type: + Definition: <0x0100> or <0x0200>. 0x0100 is a version tag for icp_v1 (a5). + 0x0200 is a version tag for icp_v2 (lx7). [15:8] indicates major version. + [7:0] indicates minor version. + +- reg-names + Usage: optional + Value type: + Definition: Name of the register resources. + +- reg + Usage: optional + Value type: + Definition: Register values. + +- reg-cam-base + Usage: optional + Value type: + Definition: Register values. + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt associated with ICP HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for ICP HW. + +- camss-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for ICP HW. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for ICP HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: lowsvs, svs, svs_l1, nominal, turbo. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- fw_name + Usage: optional + Value type: + Definition: Name of firmware image. + +- ubwc-ipe-fetch-cfg + Usage: required + Value type: + Definition: UBWC IPE fetch configuration based on DDR device type. + +- ubwc-ipe-write-cfg + Usage: required + Value type: + Definition: UBWC IPE write configuration based on DDR device type. + +- ubwc-bps-fetch-cfg + Usage: required + Value type: + Definition: UBWC BPS fetch configuration based on DDR device type. + +- ubwc-bps-write-cfg + Usage: required + Value type: + Definition: UBWC BPS write configuration based on DDR device type. + +- ubwc-cfg + Usage: optional + Value type: + Definition: UBWC configuration, this is mandatory if above + ipe/bps ubwc properties are not used. + +- nrt-device + Usage: optional + Value type: + Definition: Flag to indicate whether this is non real time device. + +Examples: +cam_a5: qcom,a5 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 600000000 0>, + <0 0 600000000 0>, + <0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + fw_name = "CAMERA_ICP.elf"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + status = "ok"; +}; + +cam_lx7: qcom,lx7 { + cell-index = <0>; + compatible = "qcom,cam-lx7"; + reg = <0xac01000 0x400>, + <0xac01800 0x400>; + reg-names = "lx7_csr", "lx7_cirq"; + reg-cam-base = <0x1000 0x1800>; + interrupts = ; + interrupt-names = "lx7"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_slow_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + + clock-rates = + <80000000 0 400000000 0>, + <80000000 0 480000000 0>, + <80000000 0 600000000 0>, + <80000000 0 600000000 0>, + <80000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + fw_name = "CAMERA_ICP.elf"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + status = "ok"; +}; + +cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe", "qcom,cam-ipe680"; + reg = <0xac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk_src", + "ipe_nps_ahb_clk", + "ipe_fast_ahb_clk_src", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk"; + "ipe_pps_clk"; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_CLK>; + + clock-rates = + <80000000 0 100000000 0 0 364000000 0 0>, + <80000000 0 200000000 0 0 500000000 0 0>, + <80000000 0 300000000 0 0 600000000 0 0>, + <80000000 0 400000000 0 0 700000000 0 0>, + <80000000 0 400000000 0 0 700000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + status = "ok"; +}; + +qcom,ipe1 { + cell-index = <1>; + compatible = "qcom,cam-ipe"; + regulator-names = "ipe1-vdd"; + ipe1-vdd-supply = <&ipe_1_gdsc>; + clock-names = "ipe_1_ahb_clk", + "ipe_1_areg_clk", + "ipe_1_axi_clk", + "ipe_1_clk", + "ipe_1_clk_src"; + src-clock-name = "ipe_1_clk_src"; + clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_1_CLK>, + <&clock_camcc CAM_CC_IPE_1_CLK_SRC>; + + clock-rates = <0 0 0 0 240000000>, + <0 0 0 0 404000000>, + <0 0 0 0 480000000>, + <0 0 0 0 538000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + nrt-device; +}; + +cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps", "qcom,cam-bps680"; + reg = <0xac2c000 0xB000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk_src", + "bps_ahb_clk", + "bps_fast_ahb_clk_src", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>; + + clock-rates = + <80000000 0 100000000 0 200000000 0>, + <80000000 0 200000000 0 400000000 0>, + <80000000 0 300000000 0 480000000 0>, + <80000000 0 400000000 0 600000000 0>, + <80000000 0 400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + status = "ok"; +}; diff --git a/bindings/msm-cam-ife-csid.txt b/bindings/msm-cam-ife-csid.txt new file mode 100644 index 00000000..2bb14da3 --- /dev/null +++ b/bindings/msm-cam-ife-csid.txt @@ -0,0 +1,147 @@ +* Qualcomm Technologies, Inc. MSM Camera IFE CSID + +Camera IFE CSID device provides the definitions for enabling +the IFE CSID hardware. It also provides the functions for the client +to control the IFE CSID hardware. + +======================= +Required Node Structure +======================= +The IFE CSID device is described in one level of the device node. + +====================================== +First Level Node - CAM IFE CSID device +====================================== +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,csid170", "qcom,csid170_200", "qcom,csid175", + "qcom,csid175_200", "qcom,csid480", "qcom,csid570", "qcom,csid580", + "qcom,csid680", "qcom,csid680_110", "qcom,csid165_204", "qcom,csid-lite170", + "qcom,csid-lite175", "qcom,csid-lite480", "qcom,csid-custom480", + "qcom,csid-lite580", "qcom,csid-lite580", "qcom,csid-custom580", + "qcom,csid-lite680", "qcom,csid-lite680_110" or "qcom,csid-custom680", + "qcom,csid-lite165". + +- reg-names + Usage: required + Value type: + Definition: Should be "csid". + +- reg + Usage: required + Value type: + Definition: Register values. + +- reg-cam-base + Usage: required + Value type: + Definition: List of bases. + +- rt-wrapper-base + Usage: required + Value type: u32 + Definition: Titan offset of start of the RT Wrapper. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with IFE CSID HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for IFE CSID HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for IFE CSID HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for IFE CSID HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- shared-clks + Usage: optional + Value type: + Definition: List of 0 or 1 values indicating whether shared clk or not. + +Example: + +cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top"; + reg = <0xacb7000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb7000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0 0 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "cphy_rx_clk_src", + "csiphy_rx_clk", + "cpas_fast_ahb_src", + "cpas_fast_ahb"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_FAST_AHB_CLK>; + clock-rates = + <400000000 0 400000000 0 100000000 0>, + <480000000 0 480000000 0 200000000 0>, + <480000000 0 480000000 0 300000000 0>, + <480000000 0 480000000 0 400000000 0>, + <480000000 0 480000000 0 400000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; +}; diff --git a/bindings/msm-cam-isp.txt b/bindings/msm-cam-isp.txt new file mode 100644 index 00000000..801c3fea --- /dev/null +++ b/bindings/msm-cam-isp.txt @@ -0,0 +1,36 @@ +* Qualcomm Technologies, Inc. MSM Camera ISP + +The MSM camera ISP driver provides the definitions for enabling +the Camera ISP hadware. It provides the functions for the Client to +control the ISP hardware. + +======================= +Required Node Structure +======================= +The camera ISP device is described in one level of device node. + +================================== +First Level Node - CAM ISP device +================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-isp". + +- arch-compat + Usage: required + Value type: + Definition: Should be "vfe", "ife" or "tfe". + +- ubwc-static-cfg + Usage: optional + Value type: + Definition: IFE UBWC static configuration based on DDR device type. + +Example: + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; diff --git a/bindings/msm-cam-jpeg.txt b/bindings/msm-cam-jpeg.txt new file mode 100644 index 00000000..9b842aec --- /dev/null +++ b/bindings/msm-cam-jpeg.txt @@ -0,0 +1,202 @@ +* Qualcomm Technologies, Inc. MSM Camera JPEG + +The MSM camera JPEG devices are implemented multiple device nodes. +The root JPEG device node has properties defined to hint the driver +about the number of Encoder and DMA nodes available during the +probe sequence. Each node has multiple properties defined +for interrupts, clocks and regulators. + +======================= +Required Node Structure +======================= +JPEG root interface node takes care of the handling account for number +of Encoder and DMA devices present on the hardware. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-jpeg". + +- compat-hw-name + Usage: required + Value type: + Definition: Should be "qcom,jpegenc" or "qcom,jpegdma". + +- num-jpeg-enc + Usage: required + Value type: + Definition: Number of supported Encoder HW blocks. + +- num-jpeg-dma + Usage: required + Value type: + Definition: Number of supported DMA HW blocks. + +Example: + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + +======================= +Required Node Structure +======================= +Encoder/DMA Nodes provide interface for JPEG driver about +the device register map, interrupt map, clocks and regulators. +Compatible string definition should be based on target. + +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam_jpeg_enc". + Definition: Should be "qcom,cam_jpeg_enc_165". + Definition: Should be "qcom,cam_jpeg_enc_580". + Definition: Should be "qcom,cam_jpeg_enc_680". + Definition: Should be "qcom,cam_jpeg_dma". + Definition: Should be "qcom,cam_jpeg_dma_165". + Definition: Should be "qcom,cam_jpeg_dma_580". + Definition: Should be "qcom,cam_jpeg_dma_680". + +- reg-names + Usage: optional + Value type: + Definition: Name of the register resources. + +- reg + Usage: optional + Value type: + Definition: Register values. + +- reg-cam-base + Usage: optional + Value type: + Definition: Offset of the register space compared to + to Camera base register space. + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt associated with JPEG HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for JPEG HW. + +- camss-vdd-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for JPEG HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for JPEG HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. + +- shared-clks + Usage: optional + Value type: + Definition: List of 0 or 1 values indicating whether shared clk or not. + +- nrt-device + Usage: optional + Value type: + Definition: Flag to indicate whether this is non real time device. + +- cam_hw_pid: + Usage: optional + Value type: + Definition: HW unique Pid values + +- cam_hw_rd_mid: + Usage: optional + Value type: + Definition: HW port read mid value + +- cam_hw_wr_mid: + Usage: optional + Value type: + Definition: HW port write mid value + +Examples: + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = <0 474 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = "jpegenc_clk_src", + "jpegenc_clk"; + clocks = <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@0xac52000{ + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = <0 475 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = "jpegdma_clk_src", + "jpegdma_clk"; + clocks = <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + status = "ok"; + }; diff --git a/bindings/msm-cam-lrme.txt b/bindings/msm-cam-lrme.txt new file mode 100644 index 00000000..409be3f0 --- /dev/null +++ b/bindings/msm-cam-lrme.txt @@ -0,0 +1,148 @@ +* Qualcomm Technologies, Inc. MSM Camera LRME + +The MSM camera Low Resolution Motion Estimation device provides dependency +definitions for enabling Camera LRME HW. MSM camera LRME is implemented in +multiple device nodes. The root LRME device node has properties defined to +hint the driver about the LRME HW nodes available during the probe sequence. +Each node has multiple properties defined for interrupts, clocks and +regulators. + +======================= +Required Node Structure +======================= +LRME root interface node takes care of the handling LRME high level +driver handling and controls underlying LRME hardware present. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-lrme" + +- compat-hw-name + Usage: required + Value type: + Definition: Should be "qcom,lrme" + +- num-lrme + Usage: required + Value type: + Definition: Number of supported LRME HW blocks + +Example: + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + compat-hw-name = "qcom,lrme"; + num-lrme = <1>; + }; + +======================= +Required Node Structure +======================= +LRME Node provides interface for Low Resolution Motion Estimation hardware +driver about the device register map, interrupt map, clocks, regulators. + +- cell-index + Usage: required + Value type: + Definition: Node instance number + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,lrme" + +- reg-names + Usage: optional + Value type: + Definition: Name of the register resources + +- reg + Usage: optional + Value type: + Definition: Register values + +- reg-cam-base + Usage: optional + Value type: + Definition: Offset of the register space compared to + to Camera base register space + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt + +- interrupts + Usage: optional + Value type: + Definition: Interrupt line associated with LRME HW + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for LRME HW + +- camss-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names" + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for LRME HW + +- clocks + Usage: required + Value type: + Definition: List of clocks required for LRME HW + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels + Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name + +Examples: + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = <0 476 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "lrme_clk_src", + "lrme_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_LRME_CLK_SRC>, + <&clock_camcc CAM_CC_LRME_CLK>; + clock-rates = <0 0 0 0 0 0 0>, + <0 0 0 0 0 19200000 19200000>, + <0 0 0 0 0 19200000 19200000>, + <0 0 0 0 0 19200000 19200000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "lrme_core_clk_src"; + }; diff --git a/bindings/msm-cam-ope.txt b/bindings/msm-cam-ope.txt new file mode 100644 index 00000000..fdd6c5e9 --- /dev/null +++ b/bindings/msm-cam-ope.txt @@ -0,0 +1,168 @@ +* Qualcomm Technologies, Inc. MSM Camera OPE + +The ope device node has properties defined to hint the driver +about the number of OPE nodes available during the +probe sequence. Each node has multiple properties defined +for interrupts, clocks and regulators. + +======================= +Required Node Structure +======================= +OPE root interface node takes care of the handling account for number +of OPE devices present on the hardware. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,cam-ope". + +- compat-hw-name + Usage: required + Value type: + Definition: Should be "qcom,ope". + +- num-ope + Usage: required + Value type: + Definition: Number of supported OPE HW blocks. + +Example: + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <2>; + status = "ok"; + }; + +======================= +Required Node Structure +======================= +OPE Node provides interface for Image Control Processor driver +about the OPE register map, interrupt map, clocks, regulators. + +- cell-index + Usage: required + Value type: + Definition: Node instance number. + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,ope". + +- reg-names + Usage: optional + Value type: + Definition: Name of the register resources. + +- reg + Usage: optional + Value type: + Definition: Register values. + +- reg-cam-base + Usage: optional + Value type: + Definition: Register values. + +- interrupt-names + Usage: optional + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: optional + Value type: + Definition: Interrupt associated with OPE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for OPE HW. + +- camss-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed + in "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CDM HW. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for CDM HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: List of strings corresponds clock-rates levels. + Supported strings: lowsvs, svs, svs_l1, nominal, turbo. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +Examples: +qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; +}; + +ope: qcom,ope@ac00000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x42000 0x400>, + <0x42400 0x200>, + <0x42600 0x200>, + <0x42800 0x4400>, + <0x46c00 0x190>, + <0x46d90 0x1270>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk_src", + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + + clock-rates = + <200000000 0 480000000 0>, + <400000000 0 600000000 0>; + + clock-cntl-level = "svs", "turbo"; + src-clock-name = "ope_clk_src"; + status = "ok"; +}; diff --git a/bindings/msm-cam-ppi.txt b/bindings/msm-cam-ppi.txt new file mode 100644 index 00000000..4733b8e8 --- /dev/null +++ b/bindings/msm-cam-ppi.txt @@ -0,0 +1,95 @@ +* Qualcomm Technologies, Inc. MSM camera PPI + +======================= +Required Node Structure +======================= +The camera PPI node must be described in First level of device nodes. The +first level describe the overall PPI node structure. + +====================================== +First Level Node - PPI device +====================================== + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,ppi100". + +- cell-index: ppi hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the ppi operating in + compatible mode. + +- reg-names + Usage: required + Value type: + Definition: Should specify relevant names to each + reg property defined. + +- reg-cam-base + Usage: required + Value type: + Definition: offset of PPI in camera hw block + +- interrupts + Usage: required + Value type: + Definition: Interrupt associated with PPI HW. + +- interrupt-names + Usage: required + Value type: + Definition: Name of the interrupt. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for PPI HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clock rates in Hz for PPI HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- clocks + Usage: required + Value type: + Definition: all clock phandle and source clocks. + +- regulator-names + Usage: required + Value type: + Definition: name of the voltage regulators required for the device. + +- gdscr-supply + Usage: required + Value type: + Definition: should contain gdsr regulator used for PPI clocks. + +Example: + qcom,ppi0@5cb3000 { + cell-index = <0>; + compatible = "qcom,ppi100"; + reg-names = "ppi0"; + reg = <0x5cb3000 0x200>; + reg-cam-base = <0xb3000>; + interrupt-names = "ppi0"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-names = "gcc_camss_cphy_0_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; +}; diff --git a/bindings/msm-cam-sfe.txt b/bindings/msm-cam-sfe.txt new file mode 100644 index 00000000..607bf02d --- /dev/null +++ b/bindings/msm-cam-sfe.txt @@ -0,0 +1,137 @@ +* Qualcomm Technologies, Inc. MSM Camera SFE + +Camera SFE device provides the definitions for enabling +the SFE hardware. It also provides the functions for the client +to control the SFE hardware. + +======================= +Required Node Structure +======================= +The SFE device is described in one level of the device node. + +====================================== +First Level Node - CAM SFE device +====================================== +Required properties: +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + + driver. e.g. "qcom,sfe680". + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + +- reg-cam-base + Usage: required + Value type: + Definition: List of bases. + +- rt-wrapper-base + Usage: required + Value type: u32 + Definition: Titan offset of start of the RT Wrapper. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with SFE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for SFE HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for SFE HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for SFE HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- scl-clk-names + Usage: required + Value type: + Definition: Source clock name for register write. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +Example: +cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe680"; + reg-names = "sfe0"; + reg = <0xac9e000 0x8000>; + reg-cam-base = <0x9e000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe"; + interrupts = ; + regulator-names = "camss", "sfe0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + sfe0-supply = <&cam_cc_sfe_0_gdsc>; + clock-names = + "sfe_0_ahb", + "sfe_clk_src", + "sfe_clk"; + clocks = + <&clock_camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_CLK>; + clock-rates = + <100000000 432000000 0>, + <200000000 594000000 0>, + <300000000 675000000 0>, + <400000000 785000000 0>, + <400000000 785000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_clk_src"; + scl-clk-names = "sfe_0_ahb"; + clock-control-debugfs = "true"; + status = "ok"; +}; diff --git a/bindings/msm-cam-smmu.txt b/bindings/msm-cam-smmu.txt new file mode 100644 index 00000000..94122f7b --- /dev/null +++ b/bindings/msm-cam-smmu.txt @@ -0,0 +1,147 @@ +* Qualcomm Technologies, Inc. MSM Camera SMMU + +The MSM camera SMMU device provides SMMU context bank definitions +for all HW blocks that need to map IOVA to physical memory. These +definitions consist of various properties that define how the +IOVA address space is laid out for each HW block in the camera +subsystem. + +======================= +Required Node Structure +======================= +The camera SMMU device must be described in three levels of device nodes. The +first level describes the overall SMMU device. Within it, second level nodes +describe individual context banks that map different stream ids. There can +also be second level nodes describing firmware device nodes. Each HW block +such as IFE, ICP maps into these second level device nodes. All context bank +specific properties that define how the IOVA is laid out is contained within +third level device nodes within the second level device nodes. + +During the kernel initialization all the devices are probed recursively and +a device pointer is created for each context bank keeping track of the IOVA +mapping information. + +Duplicate regions of the same type are not allowed within the same +context bank. All context banks must contain an IO region at the very least. + +================================== +First Level Node - CAM SMMU device +================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,msm-cam-smmu". + +=================================================================== +Second Level Node - CAM SMMU context bank device or firmware device +=================================================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,msm-cam-smmu-cb" or "qcom,msm-cam-smmu-fw-dev". + +- memory-region + Usage: optional + Value type: + Definition: Should specify the phandle of the memory region for firmware. + allocation + +- iommus + Usage: required + Value type: + Definition: first cell is phandle of the iommu, second cell is stream id + and third cell is SMR mask. + +- label + Usage: required + Value type: + Definition: Should specify a string label to identify the context bank. + +- qcom,secure-cb + Usage: optional + Value type: boolean + Definition: Specifies if the context bank is a secure context bank. + +- qti,smmu-proxy-cb-id + Usage: optional for secure camera 2.0, required for 2.5 + Value type: + Definition: Specifies that the SMMU proxy client is camera. + +============================================= +Third Level Node - CAM SMMU memory map device +============================================= +- iova-region-name + Usage: required + Value type: + Definition: Should specify a string label to identify the IOVA region. + +- iova-region-start + Usage: required + Value type: + Definition: Should specify start IOVA for region. + +- iova-region-len + Usage: required + Value type: + Definition: Should specify length for IOVA region. + +- iova-region-id + Usage: required + Value type: + Definition: Should specify the numerical identifier for IOVA region. + Allowed values are: 0x00 to 0x03 + - Firmware region: 0x00 + - Shared region: 0x01 + - Scratch region: 0x02 + - IO region: 0x03 + +- iova-granularity + Usage: optional + Value type: + Definition: Should specify IOVA granularity for shared memory region. + +Example: + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1078>, + <&apps_smmu 0x1020>, + <&apps_smmu 0x1028>, + <&apps_smmu 0x1040>, + <&apps_smmu 0x1048>, + <&apps_smmu 0x1030>, + <&apps_smmu 0x1050>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + iova-granularity = <0x15>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.5 GB */ + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; diff --git a/bindings/msm-cam-tfe-csid.txt b/bindings/msm-cam-tfe-csid.txt new file mode 100644 index 00000000..24ac5b3b --- /dev/null +++ b/bindings/msm-cam-tfe-csid.txt @@ -0,0 +1,123 @@ +* Qualcomm Technologies, Inc. MSM Camera TFE CSID + +Camera TFE CSID device provides the definitions for enabling +the TFE CSID hardware. It also provides the functions for the client +to control the TFE CSID hardware. + +======================= +Required Node Structure +======================= +The TFE CSID device is described in one level of the device node. + +====================================== +First Level Node - CAM TFE CSID device +====================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,csid640", "qcom,csid530". + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg-names + Usage: required + Value type: + Definition: Should be "csid". + +- reg + Usage: required + Value type: + Definition: Register values. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with TFE CSID HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for TFE CSID HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for TFE CSID HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for TFE CSID HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +Example: + + qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <240000000 0 0 0 256000000 0 0>, + <384000000 0 0 0 460800000 0 0>, + <426400000 0 0 0 576000000 0 0>, + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; diff --git a/bindings/msm-cam-tfe.txt b/bindings/msm-cam-tfe.txt new file mode 100644 index 00000000..1585ca77 --- /dev/null +++ b/bindings/msm-cam-tfe.txt @@ -0,0 +1,147 @@ +* Qualcomm Technologies, Inc. MSM Camera TFE + +Camera TFE device provides the definitions for enabling +the TFE hardware. It also provides the functions for the client +to control the TFE hardware. + +======================= +Required Node Structure +======================= +The TFE device is described in one level of the device node. + +====================================== +First Level Node - CAM TFE device +====================================== +Required properties: +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + driver. e.g. "qcom,tfe640", "qcom,tfe530". + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with TFE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for TFE HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for TFE HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for TFE HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +Optional properties: +- clock-names-option + Usage: optional + Value type: + Definition: Optional clock names. + +- clocks-option + Usage: required if clock-names-option defined + Value type: + Definition: List of optinal clocks used for TFE HW. + +- clock-rates-option + Usage: required if clock-names-option defined + Value type: + Definition: List of clocks rates for optional clocks. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- qcom,cam-cx-ipeak: + Usage: optional + Value type: + phandle - phandle of CX Ipeak device node + bit - Every bit corresponds to a client of CX Ipeak + Definition: CX Ipeak is a mitigation scheme which throttles camera frequency + if all the clients are running at their respective threshold + frequencies to limit CX peak current. + driver in the relevant register. + +- scl-clk-names: + Usage: optional + Value type: + Definition: Scalable clock names to identify which clocks needs to update + along with source clock. + +- cam_hw_pid: + Usage: optional + Value type: + Definition: HW unique Pid values + +Example: + cam_tfe0: qcom,tfe0@5c6e000{ + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <256000000 0 150000000>, + <460800000 0 200000000>, + <576000000 0 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; diff --git a/bindings/msm-cam-tpg.txt b/bindings/msm-cam-tpg.txt new file mode 100644 index 00000000..78fb5387 --- /dev/null +++ b/bindings/msm-cam-tpg.txt @@ -0,0 +1,137 @@ +* Qualcomm Technologies, Inc. MSM Camera TPG + +Camera TPG device provides the definitions for enabling +the TPG hardware. It also provides the functions for the client +to control the TPG hardware. + +======================= +Required Node Structure +======================= +The TPG device is described in one level of the device node. + +====================================== +First Level Node - CAM TPG device +====================================== +Required properties: +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + driver. e.g. "qcom,cam-tpg101", "qcom,cam-tpg102", "qcom,cam-tpgv1", "qcom,cam-tpg103" + +- phy-id + Usage: required + Value type: + Definition: Should specify the phy index number for csid input configuration + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + +- reg-cam-base + Usage: required + Value type: + Definition: List of bases. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for TFE HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with TFE HW. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for TFE HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for TFE HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- scl-clk-names: + Usage: optional + Value type: + Definition: Scalable clock names to identify which clocks needs to update + along with source clock. + +- shared-clks + Usage: optional + Value type: + Definition: List of 0 or 1 values indicating whether shared clk or not. + +Example: +cam_csiphy_tpg0: qcom,tpg0@acf6000 { + cell-index = <0>; + compatible = "qcom,tpg103"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0 0 0>; + clock-names = + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-rates = + <480000000 0 400000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; +}; diff --git a/bindings/msm-cam-vfe.txt b/bindings/msm-cam-vfe.txt new file mode 100644 index 00000000..cf3f7ffc --- /dev/null +++ b/bindings/msm-cam-vfe.txt @@ -0,0 +1,176 @@ +* Qualcomm Technologies, Inc. MSM Camera VFE + +Camera VFE device provides the definitions for enabling +the VFE hardware. It also provides the functions for the client +to control the VFE hardware. + +======================= +Required Node Structure +======================= +The VFE device is described in one level of the device node. + +====================================== +First Level Node - CAM VFE device +====================================== +Required properties: +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + + driver. e.g. "qcom,vfe680", "qcom,vfe680_110", "qcom,vfe580", "qcom,vfe580", + "qcom,vfe480", "qcom,vfe175", "qcom,vfe170", "qcom,vfe175_130", "qcom,vfe170_150", + "qcom,vfe165_160", "qcom,vfe-lite680", "qcom,vfe-lite680_110", "qcom,vfe-lite580",, + "qcom,vfe-lite580", "qcom,vfe-lite480", "qcom,vfe-lite175", + "qcom,vfe-lite175_130" or "qcom,vfe-lite170", "qcom,vfe-lite165". + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + + - reg-cam-base + Usage: required + Value type: + Definition: List of bases. + +- rt-wrapper-base + Usage: required + Value type: u32 + Definition: Titan offset of start of the RT Wrapper. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with VFE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for VFE HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for VFE HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for VFE HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +Optional properties: +- clock-names-option + Usage: optional + Value type: + Definition: Optional clock names. + +- clocks-option + Usage: required if clock-names-option defined + Value type: + Definition: List of optinal clocks used for VFE HW. + +- clock-rates-option + Usage: required if clock-names-option defined + Value type: + Definition: List of clocks rates for optional clocks. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- qcom,cam-cx-ipeak: + Usage: optional + Value type: + phandle - phandle of CX Ipeak device node + bit - Every bit corresponds to a client of CX Ipeak + Definition: CX Ipeak is a mitigation scheme which throttles camera frequency + if all the clients are running at their respective threshold + frequencies to limit CX peak current. + driver in the relevant register. + +- scl-clk-names: + Usage: optional + Value type: + Definition: Scalable clock names to identify which clocks needs to update + along with source clock. + +- cam_hw_pid: + Usage: optional + Value type: + Definition: HW unique Pid values + +Example: +cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac62000 0xF000>, + <0xac19000 0x9000>; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_ahb_src", + "ife_0_ahb", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>; + clock-rates = + <100000000 0 432000000 0>, + <200000000 0 594000000 0>, + <300000000 0 675000000 0>, + <400000000 0 785000000 0>, + <400000000 0 785000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_0_ahb"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 28 20 8>; + status = "ok"; +}; diff --git a/bindings/msm-camera-flash.txt b/bindings/msm-camera-flash.txt new file mode 100644 index 00000000..a44753c5 --- /dev/null +++ b/bindings/msm-camera-flash.txt @@ -0,0 +1,132 @@ +* Qualcomm Technologies, Inc. MSM FLASH + +The MSM camera Flash driver provides the definitions for +enabling and disabling LED Torch/Flash by requesting it to +PMIC/I2C/GPIO based hardware. It provides the functions for +the Client to control the Flash hardware. + +======================================================= +Required Node Structure +======================================================= +The Flash device is described in one level of the device node. + +====================================== +First Level Node - CAM FLASH device +====================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,camera-flash". + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg + Usage: required + Value type: + Definition: Register values. + +- flash-source + Usage: required + Value type: + Definition: Should contain array of phandles to Flash source nodes. + +- torch-source + Usage: required + Value type: + Definition: Should contain array of phandles to torch source nodes. + +- switch-source + Usage: Optional + Value type: + Definition: Should contain phandle to switch source nodes. + +- slave-id + Usage: optional + Value type: + Definition: should contain i2c slave address, device id address + and expected id read value. + +- cci-master + Usage: optional + Value type: + Definition: should contain i2c master id to be used for this camera + flash. + +- max-current + Usage: optional + Value type: + Definition: Max current in mA supported by flash + +- max-duration + Usage: optional + Value type: + Definition: Max duration in ms flash can glow. + +- wled-flash-support + Usage: optional + Value type: + Definition: To identity wled flash hardware support. + +- gpios + Usage: optional + Value type: + Definition: should specify the gpios to be used for the flash. + +- gpio-req-tbl-num + Usage: optional + Value type: + Definition: should specify the gpio table index. + +- gpio-req-tbl-flags + Usage: optional + Value type: + Definition: should specify the gpio functions. + +- gpio-req-tbl-label + Usage: optional + Value type: + Definition: should specify the gpio labels. + +- gpio-flash-reset + Usage: optional + Value type: + Definition: should contain index to gpio used by flash's "flash reset" pin. + +- gpio-flash-en + Usage: optional + Value type: + Definition: should contain index to gpio used by flash's "flash enable" pin. + +- gpio-flash-now + Usage: optional + Value type: + Definition: should contain index to gpio used by flash's "flash now" pin. + +Example: + +led_flash_rear: qcom,camera-flash0 { + reg = <0x00 0x00>; + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + switch-source = <&pmi8998_switch0>; + wled-flash-support; + qcom,slave-id = <0x00 0x00 0x0011>; + qcom,cci-master = <0>; + gpios = <&msmgpio 23 0>, + <&msmgpio 24 0>; + <&msmgpio 25 0>; + qcom,gpio-flash-reset = <0>; + qcom,gpio-flash-en = <0>; + qcom,gpio-flash-now = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <0 0>; + qcom,gpio-req-tbl-label = "FLASH_EN", + "FLASH_NOW"; + qcom,max-current = <1500>; + qcom,max-duration = <1200>; + }; diff --git a/bindings/msm-camera.txt b/bindings/msm-camera.txt new file mode 100644 index 00000000..cbbb136b --- /dev/null +++ b/bindings/msm-camera.txt @@ -0,0 +1,18 @@ +* Qualcomm Technologies, Inc. MSM Camera + +Required properties: +- compatible : + - "qcom,cam-req-mgr", "qcom,cam-sync" +- qcom,sensor-manual-probe : specify if sensor probes at kernel boot time or user driven + +Example: + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + qcom,sensor-manual-probe; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; diff --git a/cape-camera-sensor-cdp.dts b/cape-camera-sensor-cdp.dts new file mode 100644 index 00000000..b39536b2 --- /dev/null +++ b/cape-camera-sensor-cdp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "cape-camera-sensor-cdp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Cape CDP"; + compatible = "qcom,cape", "qcom,capep"; + qcom,msm-id = <530 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/cape-camera-sensor-cdp.dtsi b/cape-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..e481e58c --- /dev/null +++ b/cape-camera-sensor-cdp.dtsi @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_ois: qcom,actuator2 { + cell-index = <9>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + cam_v_custom2-supply = <&L6I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000 2800000 0>; + rgltr-max-voltage = <3000000 2896000 0>; + rgltr-load-current = <103000 90000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom7: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1800000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <20000 90000 550000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140400 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom9 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <155000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <20000 90000 550000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140400 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom7>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1800000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_triple_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_vana", "cam_v_custom1", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1050000 2900000 1800000 0>; + rgltr-max-voltage = <1800000 1200000 3000000 1800000 0>; + rgltr-load-current = <155000 872000 96000 88000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1800000 1200000 0 3000000>; + rgltr-load-current = <10000 139300 90100 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <20000 90000 550000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + regulator-names = "cam_vio", "cam_vana","cam_clk", "cam_vdig"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <10000 14720 0 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1800000 1200000 3000000 0 3960000>; + rgltr-load-current = <10000 139300 90100 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <20000 90000 550000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_clk", "cam_vdig", + "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <10000 14720 0 30000 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/cape-camera-sensor-mtp.dts b/cape-camera-sensor-mtp.dts new file mode 100644 index 00000000..9eedb91f --- /dev/null +++ b/cape-camera-sensor-mtp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "cape-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Cape MTP"; + compatible = "qcom,cape", "qcom,capep"; + qcom,msm-id = <530 0x10000>; + qcom,board-id = <8 0>; +}; diff --git a/cape-camera-sensor-mtp.dtsi b/cape-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..55a454a9 --- /dev/null +++ b/cape-camera-sensor-mtp.dtsi @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_ois: qcom,actuator2 { + cell-index = <9>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + cam_v_custom2-supply = <&L6I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000 2800000 0>; + rgltr-max-voltage = <3000000 2896000 0>; + rgltr-load-current = <103000 90000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom7: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1800000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <20000 90000 550000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140400 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom8: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + csiphy-sd-index = <0>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1100000 0 2904000 1800000 2800000>; + rgltr-max-voltage = <1800000 1200000 0 2904000 1800000 3000000>; + rgltr-load-current = <11000 415200 0 40600 20400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom9 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <155000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <20000 90000 550000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140400 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom7>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1800000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom8>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1100000 0 2904000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2904000 1800000>; + rgltr-load-current = <11000 415200 0 40600 20400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_triple_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_vana", "cam_v_custom1", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1050000 2900000 1800000 0>; + rgltr-max-voltage = <1800000 1200000 3000000 1800000 0>; + rgltr-load-current = <155000 872000 96000 88000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1800000 1200000 0 3000000>; + rgltr-load-current = <10000 139300 90100 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <20000 90000 550000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + regulator-names = "cam_vio", "cam_vana","cam_clk", "cam_vdig"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <10000 14720 0 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1800000 1200000 3000000 0 3960000>; + rgltr-load-current = <10000 139300 90100 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <20000 90000 550000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_clk", "cam_vdig", + "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <10000 14720 0 30000 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/cape-camera-sensor-qrd.dts b/cape-camera-sensor-qrd.dts new file mode 100644 index 00000000..a3dad7a0 --- /dev/null +++ b/cape-camera-sensor-qrd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "cape-camera-sensor-qrd.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Cape QRD"; + compatible = "qcom,cape", "qcom,capep"; + qcom,msm-id = <530 0x10000>, <540 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/cape-camera-sensor-qrd.dtsi b/cape-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..55a454a9 --- /dev/null +++ b/cape-camera-sensor-qrd.dtsi @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_ois: qcom,actuator2 { + cell-index = <9>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + cam_v_custom2-supply = <&L6I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000 2800000 0>; + rgltr-max-voltage = <3000000 2896000 0>; + rgltr-load-current = <103000 90000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom7: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1800000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <20000 90000 550000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140400 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom8: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + csiphy-sd-index = <0>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1100000 0 2904000 1800000 2800000>; + rgltr-max-voltage = <1800000 1200000 0 2904000 1800000 3000000>; + rgltr-load-current = <11000 415200 0 40600 20400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom9 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <155000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <20000 90000 550000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140400 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom7>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1800000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom8>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1100000 0 2904000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2904000 1800000>; + rgltr-load-current = <11000 415200 0 40600 20400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_triple_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_vana", "cam_v_custom1", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1050000 2900000 1800000 0>; + rgltr-max-voltage = <1800000 1200000 3000000 1800000 0>; + rgltr-load-current = <155000 872000 96000 88000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1800000 1200000 0 3000000>; + rgltr-load-current = <10000 139300 90100 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <20000 90000 550000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + regulator-names = "cam_vio", "cam_vana","cam_clk", "cam_vdig"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <10000 14720 0 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1800000 1200000 3000000 0 3960000>; + rgltr-load-current = <10000 139300 90100 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <20000 90000 550000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_clk", "cam_vdig", + "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <10000 14720 0 30000 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/cape-camera.dts b/cape-camera.dts new file mode 100644 index 00000000..3a611ea7 --- /dev/null +++ b/cape-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "cape-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Cape v1 SoC"; + compatible = "qcom,cape"; + qcom,msm-id = <530 0x10000>, <540 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/cape-camera.dtsi b/cape-camera.dtsi new file mode 100644 index 00000000..c277fd35 --- /dev/null +++ b/cape-camera.dtsi @@ -0,0 +1,2696 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio110","gpio111"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio110","gpio111"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio110","gpio111"; + function = "cci_i2c"; + }; + + config { + pins = "gpio110","gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio112","gpio113"; + function = "cci_i2c"; + }; + + config { + pins = "gpio112","gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112","gpio113"; + function = "cci_i2c"; + }; + + config { + pins = "gpio112","gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio114","gpio115"; + function = "cci_i2c"; + }; + + config { + pins = "gpio114","gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114","gpio115"; + function = "cci_i2c"; + }; + + config { + pins = "gpio114","gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "cci_i2c"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "cci_i2c"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + qcom,remote; + }; + + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_mclk"; + }; + + config { + pins = "gpio104"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_mclk"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + /* RESET REAR */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + /* RESET REAR */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + /* RESET 2 */ + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + /* RESET 2 */ + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 3 */ + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 3 */ + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 4 */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 4 */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + /* RESET 5 */ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + /* RESET 5 */ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + /* RESET 6 */ + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + /* RESET 6 */ + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; + +&soc { + + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.1.3", "qcom,csiphy"; + reg = < 0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.1.3", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.1.3", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.1.3", "qcom,csiphy"; + reg = <0xacea000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xea000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.1.3", "qcom,csiphy"; + reg = <0xacec000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY4_CLK>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@acee000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.1.3", "qcom,csiphy"; + reg = <0xacee000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xee000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY5_CLK>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac15000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupt-names = "cci0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac16000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupt-names = "cci1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + force_cache_allocs; + need_shared_buffer_padding; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x460>, + <&apps_smmu 0x820 0x460>, + <&apps_smmu 0xC00 0x460>, + <&apps_smmu 0xC20 0x460>, + <&apps_smmu 0x840 0x460>, + <&apps_smmu 0x860 0x460>, + <&apps_smmu 0xC40 0x460>, + <&apps_smmu 0xC60 0x460>; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20E0 0x400>, + <&apps_smmu 0x24E0 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2020 0x420>, + <&apps_smmu 0x2000 0x420>, + <&apps_smmu 0x2420 0x420>, + <&apps_smmu 0x2400 0x420>, + <&apps_smmu 0x2040 0x420>, + <&apps_smmu 0x2060 0x420>, + <&apps_smmu 0x2440 0x420>, + <&apps_smmu 0x2460 0x420>, + <&apps_smmu 0x2100 0x420>, + <&apps_smmu 0x2500 0x420>, + <&apps_smmu 0x2080 0x400>, + <&apps_smmu 0x2480 0x400>, + <&apps_smmu 0x2120 0x420>, + <&apps_smmu 0x2520 0x420>; + cam-smmu-label = "icp"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xFC00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x0400>, + <&apps_smmu 0x24C0 0x0400>, + <&apps_smmu 0x20A0 0x0400>, + <&apps_smmu 0x24A0 0x0400>; + cam-smmu-label = "cpas-cdm", "rt-cdm"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + multiple-client-devices; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac13000 0x1000>, + <0xac19000 0x9000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CORE_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 100000000 0 300000000 0>, + <0 0 0 80000000 0 0 200000000 0 400000000 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_axi_clk_src"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "csid0", "csid1", "csid2", "csid3", "csid4", + "csid5", "csid6", "csid7", "ife0", "ife1", "ife2", "ife3", "ife4", + "ife5", "ife6", "ife7", "sfe0", "sfe1", "custom0", "custom1", + "ipe0", "cpas-cdm0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "cam-cdm-intf0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "tpg13", + "tpg14", "tpg15"; + sys-cache-names = "small-1", "small-2"; + sys-cache-uids = <34 38>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-ife-ubwc-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-ife-rdi-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <10>; + node-name = "level1-ife-pdaf"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <11>; + node-name = "level1-ife01-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <12>; + node-name = "level1-ife2-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr5: level1-rt0-wr5 { + cell-index = <13>; + node-name = "level1-ifelite"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <14>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <15>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <16>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <17>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <18>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <19>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <20>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <21>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <22>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <23>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + sfe0_rdi_stats_nrdi_wr: sfe0-rdi-stats-nrdi-wr { + cell-index = <24>; + node-name = "sfe0-rdi-stats-nrdi-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + sfe1_rdi_stats_nrdi_wr: sfe1-rdi-stats-nrdi-wr { + cell-index = <25>; + node-name = "sfe1-rdi-stats-nrdi-wr"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + custom0_wr: custom0-wr { + cell-index = <26>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <27>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_pdaf_wr: ife1-pdaf-wr { + cell-index = <28>; + node-name = "ife1-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife2_pdaf_wr: ife2-pdaf-wr { + cell-index = <29>; + node-name = "ife2-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_linear_stats_wr: ife0-linear-stats-wr { + cell-index = <30>; + node-name = "ife0-linear-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife1_linear_stats_wr: ife1-linear-stats-wr { + cell-index = <31>; + node-name = "ife1-linear-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife2_linear_stats_wr: ife2-linear-stats-wr { + cell-index = <32>; + node-name = "ife2-linear-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + custom1_wr: custom1-wr { + cell-index = <33>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife7_rdi_stats_pixel_raw_wr: ife7-rdi-stats-pixel-raw-wr { + cell-index = <34>; + node-name = "ife7-rdi-stats-pixel-raw-wr"; + client-name = "ife7"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife6_rdi_stats_pixel_raw_wr: ife6-rdi-stats-pixel-raw-wr { + cell-index = <35>; + node-name = "ife6-rdi-stats-pixel-raw-wr"; + client-name = "ife6"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife5_rdi_stats_pixel_raw_wr: ife5-rdi-stats-pixel-raw-wr { + cell-index = <36>; + node-name = "ife5-rdi-stats-pixel-raw-wr"; + client-name = "ife5"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <37>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <38>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <39>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + sfe1_all_rd: sfe1-all-rd { + cell-index = <40>; + node-name = "sfe1-all-rd"; + client-name = "sfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom0_rd: custom0-rd { + cell-index = <41>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom1_rd: custom1-rd { + cell-index = <42>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <43>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <44>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <45>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <46>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <47>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <48>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <49>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <50>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <51>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <52>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <53>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <54>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <55>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <56>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac24000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_1"; + label = "cpas-cdm"; + reg = <0xac24000 0x400>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x24000>; + interrupt-names = "cpas-cdm"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + nrt-device; + cdm-client-names = "ife3", "ife4", "ife5", "ife6", "ife7"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac25000 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac26000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac26000 0x400>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac27000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac27000 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x27000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2", "dualife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe680"; + reg-names = "sfe0", "rt_wrapper"; + reg = <0xac9e000 0x8000>, + <0xac62000 0x64000>; + reg-cam-base = <0x9e000 0x62000>; + interrupt-names = "sfe0"; + interrupts = ; + regulator-names = "gdsc", "sfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe0-supply = <&cam_cc_sfe_0_gdsc>; + clock-names = + "sfe_0_fast_ahb", + "sfe_0_clk_src", + "sfe_0_clk", + "cam_cc_cpas_sfe_0_clk"; + clocks = + <&clock_camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_CLK>, + <&clock_camcc CAM_CC_CPAS_SFE_0_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_0_clk_src"; + cam_hw_pid = <11 24>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe1: qcom,sfe1@aca6000 { + cell-index = <1>; + compatible = "qcom,sfe680"; + reg-names = "sfe1", "rt_wrapper"; + reg = <0xaca6000 0x8000>, + <0xac62000 0x64000>; + reg-cam-base = <0xa6000 0x62000>; + interrupt-names = "sfe1"; + interrupts = ; + regulator-names = "gdsc", "sfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe1-supply = <&cam_cc_sfe_1_gdsc>; + clock-names = + "sfe_1_fast_ahb", + "sfe_1_clk_src", + "sfe_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clocks = + <&clock_camcc CAM_CC_SFE_1_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_1_CLK>, + <&clock_camcc CAM_CC_CPAS_SFE_1_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_1_clk_src"; + cam_hw_pid = <12 25>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid680_110"; + reg-names = "csid", "csid_top", "rt_wrapper"; + reg = <0xacb7000 0xd00>, + <0xacb6000 0x1000>, + <0xac62000 0x64000>; + reg-cam-base = <0xb7000 0xb6000 0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe680_110"; + reg-names = "ife", "cam_camnoc", "rt_wrapper"; + reg = <0xac62000 0xf000>, + <0xac19000 0x9000>, + <0xac62000 0x64000>; + reg-cam-base = <0x62000 0x19000 0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_0_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 28 20 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acb9000 { + cell-index = <1>; + compatible = "qcom,csid680_110"; + reg-names = "csid", "csid_top", "rt_wrapper"; + reg = <0xacb9000 0xd00>, + <0xacb6000 0x1000>, + <0xac62000 0x64000>; + reg-cam-base = <0xb9000 0xb6000 0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac71000 { + cell-index = <1>; + compatible = "qcom,vfe680_110"; + reg-names = "ife", "cam_camnoc", "rt_wrapper"; + reg = <0xac71000 0xf000>, + <0xac19000 0x9000>, + <0xac62000 0x64000>; + reg-cam-base = <0x71000 0x19000 0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_1_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 29 21 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acbb000 { + cell-index = <2>; + compatible = "qcom,csid680_110"; + reg-names = "csid", "csid_top", "rt_wrapper"; + reg = <0xacbb000 0xd00>, + <0xacb6000 0x1000>, + <0xac62000 0x64000>; + reg-cam-base = <0xbb000 0xb6000 0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@ac80000 { + cell-index = <2>; + compatible = "qcom,vfe680_110"; + reg-names = "ife", "cam_camnoc", "rt_wrapper"; + reg = <0xac80000 0xf000>, + <0xac19000 0x9000>, + <0xac62000 0x64000>; + reg-cam-base = <0x80000 0x19000 0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_fast_ahb", + "ife_2_clk_src", + "ife_2_clk", + "cam_cc_cpas_ife_2_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_2_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_2_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <18 30 22 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acc6000 { + cell-index = <3>; + compatible = "qcom,csid-lite680_110"; + reg-names = "csid-lite"; + reg = <0xacc6000 0xa00>; + reg-cam-base = <0xc6000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acc6000 { + cell-index = <3>; + compatible = "qcom,vfe-lite680_110"; + reg-names = "ife-lite"; + reg = <0xacc6000 0x2800>; + reg-cam-base = <0xc6000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <0>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@acca000 { + cell-index = <4>; + compatible = "qcom,csid-lite680_110"; + reg-names = "csid-lite"; + reg = <0xacca000 0xa00>; + reg-cam-base = <0xca000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@acca000 { + cell-index = <4>; + compatible = "qcom,vfe-lite680_110"; + reg-names = "ife-lite"; + reg = <0xacca000 0x2800>; + reg-cam-base = <0xca000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <1>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xacf7000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf7000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xacf8000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf8000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v2"; + icp-version = <0x0200>; + reg = <0xac01000 0x400>, + <0xac01800 0x400>, + <0x0ac04000 0x1000>; + reg-names = "icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>, + <&clock_camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + cam_hw_pid = <9>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x16000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clocks = + <&clock_camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_CLK>, + <&clock_camcc CAM_CC_CPAS_IPE_NPS_CLK>; + + clock-rates = + <0 0 0 364000000 0 0 0>, + <0 0 0 500000000 0 0 0>, + <0 0 0 600000000 0 0 0>, + <0 0 0 700000000 0 0 0>, + <0 0 0 700000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <22 23 30>; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps680"; + reg = <0xac2c000 0x7800>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clocks = + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>, + <&clock_camcc CAM_CC_CPAS_BPS_CLK>; + + clock-rates = + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 480000000 0 0>, + <0 0 600000000 0 0>, + <0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <10 16>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac2a000 0x1000>; + reg-cam-base = <0x2a000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <12 14>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac2b000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac2b000 0x1000>; + reg-cam-base = <0x2b000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <13 15>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; +}; diff --git a/config/kalama.mk b/config/kalama.mk new file mode 100644 index 00000000..f86b248a --- /dev/null +++ b/config/kalama.mk @@ -0,0 +1,7 @@ +dtbo-$(CONFIG_ARCH_KALAMA) := kalama-camera.dtbo +dtbo-$(CONFIG_ARCH_KALAMA) += kalama-camera-sensor-cdp.dtbo \ + kalama-camera-sensor-mtp.dtbo \ + kalama-camera-sensor-qrd.dtbo \ + kalama-camera-sensor-hdk.dtbo \ + kalama-sg-hhg-camera.dtbo \ + kalama-sg-hhg-camera-sensor.dtbo diff --git a/config/parrot.mk b/config/parrot.mk new file mode 100644 index 00000000..f91ec1bb --- /dev/null +++ b/config/parrot.mk @@ -0,0 +1 @@ +dtbo-$(CONFIG_ARCH_PARROT) := parrot-camera.dtbo diff --git a/config/pineapple.mk b/config/pineapple.mk new file mode 100644 index 00000000..1e4e05b2 --- /dev/null +++ b/config/pineapple.mk @@ -0,0 +1,5 @@ +dtbo-$(CONFIG_ARCH_PINEAPPLE) := pineapple-camera.dtbo +dtbo-$(CONFIG_ARCH_PINEAPPLE) += pineapple-camera-v2.dtbo \ + pineapple-camera-sensor-cdp.dtbo \ + pineapple-camera-sensor-mtp.dtbo \ + pineapple-camera-sensor-qrd.dtbo diff --git a/config/waipio.mk b/config/waipio.mk new file mode 100644 index 00000000..5fd53b1e --- /dev/null +++ b/config/waipio.mk @@ -0,0 +1,14 @@ +dtbo-$(CONFIG_ARCH_WAIPIO) := waipio-camera.dtbo +dtbo-$(CONFIG_ARCH_WAIPIO) += waipio-camera-overlay-v2.dtbo \ + waipio-camera-sensor-mtp.dtbo \ + waipio-camera-sensor-cdp.dtbo \ + waipio-camera-sensor-qrd.dtbo + +dtbo-$(CONFIG_ARCH_DIWALI) += diwali-camera.dtbo +dtbo-$(CONFIG_ARCH_DIWALI) += diwali-camera-sensor-idp.dtbo +dtbo-$(CONFIG_ARCH_DIWALI) += diwali-camera-sensor-qrd.dtbo + +dtbo-$(CONFIG_ARCH_CAPE) += cape-camera.dtbo +dtbo-$(CONFIG_ARCH_CAPE) += cape-camera-sensor-mtp.dtbo \ + cape-camera-sensor-cdp.dtbo \ + cape-camera-sensor-qrd.dtbo \ diff --git a/diwali-camera-sensor-idp.dts b/diwali-camera-sensor-idp.dts new file mode 100644 index 00000000..62c6a48f --- /dev/null +++ b/diwali-camera-sensor-idp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "diwali-camera-sensor-idp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Diwali IDP"; + compatible = "qcom,diwali"; + qcom,msm-id = <506 0x10000>; + qcom,board-id = <34 0>; +}; \ No newline at end of file diff --git a/diwali-camera-sensor-idp.dtsi b/diwali-camera-sensor-idp.dtsi new file mode 100644 index 00000000..c3684fb8 --- /dev/null +++ b/diwali-camera-sensor-idp.dtsi @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 67 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <3000 52000 257000 103000 0 7840000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140000 103000 0 7840000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 67 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1888000 1200000 0 3000000>; + rgltr-load-current = <4000 96000 88000 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 66 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <3000 52000 257000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 64 0>, + <&tlmm 20 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1888000 1200000 3000000 0 3960000>; + rgltr-load-current = <4000 96000 88000 872000 103000 0 7840000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 66 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 7840000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 64 0>, + <&tlmm 20 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; \ No newline at end of file diff --git a/diwali-camera-sensor-qrd.dts b/diwali-camera-sensor-qrd.dts new file mode 100644 index 00000000..6cb6397e --- /dev/null +++ b/diwali-camera-sensor-qrd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "diwali-camera-sensor-qrd.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Diwali QRD"; + compatible = "qcom,diwali"; + qcom,msm-id = <506 0x10000>; + qcom,board-id = <0x1000B 0>; +}; \ No newline at end of file diff --git a/diwali-camera-sensor-qrd.dtsi b/diwali-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..77b09b49 --- /dev/null +++ b/diwali-camera-sensor-qrd.dtsi @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 67 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <3000 52000 257000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 65 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 67 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1888000 1200000 0 3000000>; + rgltr-load-current = <4000 96000 88000 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 66 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <3000 52000 257000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 64 0>, + <&tlmm 20 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1888000 1200000 3000000 0 3960000>; + rgltr-load-current = <4000 96000 88000 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 66 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 68 0>, + <&tlmm 80 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; \ No newline at end of file diff --git a/diwali-camera.dts b/diwali-camera.dts new file mode 100644 index 00000000..c281e834 --- /dev/null +++ b/diwali-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "diwali-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Diwali v1 SoC"; + compatible = "qcom,diwali"; + qcom,msm-id = <506 0x10000>, <547 0x10000>; + qcom,board-id = <0 0>, <0 2>; +}; diff --git a/diwali-camera.dtsi b/diwali-camera.dtsi new file mode 100644 index 00000000..d2a85ae5 --- /dev/null +++ b/diwali-camera.dtsi @@ -0,0 +1,2308 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cci0_active: cci0_active { + mux { + /* DATA, CLK */ + pins = "gpio70","gpio71"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio70","gpio71"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* DATA, CLK */ + pins = "gpio70","gpio71"; + function = "cci_i2c"; + }; + + config { + pins = "gpio70","gpio71"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* DATA, CLK */ + pins = "gpio72","gpio73"; + function = "cci_i2c"; + }; + + config { + pins = "gpio72","gpio73"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* DATA, CLK */ + pins = "gpio72","gpio73"; + function = "cci_i2c"; + }; + + config { + pins = "gpio72","gpio73"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* DATA, CLK */ + pins = "gpio74","gpio75"; + function = "cci_i2c"; + }; + + config { + pins = "gpio74","gpio75"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* DATA, CLK */ + pins = "gpio74","gpio75"; + function = "cci_i2c"; + }; + + config { + pins = "gpio74","gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* DATA, CLK */ + pins = "gpio76","gpio77"; + function = "cci_i2c"; + }; + + config { + pins = "gpio76","gpio77"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* DATA, CLK */ + pins = "gpio76","gpio77"; + function = "cci_i2c"; + }; + + config { + pins = "gpio76","gpio77"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio69"; + function = "cam_mclk"; + }; + + config { + pins = "gpio69"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio69"; + function = "cam_mclk"; + }; + + config { + pins = "gpio69"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + /* RESET REAR */ + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + /* RESET REAR */ + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + /* RESET 2 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + /* RESET 2 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 3 */ + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 3 */ + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 4 */ + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 4 */ + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + /* RESET 5 */ + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + /* RESET 5 */ + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0@ac6a000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.1.1", "qcom,csiphy"; + reg = <0x0ac6a000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6a000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 45100 85200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ac6c000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.1.1", "qcom,csiphy"; + reg = <0x0ac6c000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6c000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 45100 85200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ac6e000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.1.1", "qcom,csiphy"; + reg = <0x0ac6e000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6e000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 45100 85200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@ac70000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.1.1", "qcom,csiphy"; + reg = <0x0ac70000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x70000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 45100 85200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@ac72000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.1.1", "qcom,csiphy"; + reg = <0x0ac72000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x72000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 45100 85200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac4f000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac4f000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4f000>; + interrupt-names = "cci0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac50000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac50000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x50000>; + interrupt-names = "cci1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_csiphy_tpg13: qcom,tpg13@ac97000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg102"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xac97000 0x100>, + <0xac40000 0x1000>; + reg-cam-base = <0x97000 0x40000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@ac98000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg102"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xac98000 0x100>, + <0xac40000 0x1000>; + reg-cam-base = <0x98000 0x40000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "csi1phytimer_clk_src"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + force_cache_allocs; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x440>, + <&apps_smmu 0x840 0x440>, + <&apps_smmu 0xC00 0x440>, + <&apps_smmu 0xC40 0x440>; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent; + cam-smmu-label = "ife", "ife-cdm"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2040 0x400>, + <&apps_smmu 0x2440 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2000 0x400>, + <&apps_smmu 0x2020 0x400>, + <&apps_smmu 0x2060 0x400>, + <&apps_smmu 0x20E2 0x400>, + <&apps_smmu 0x2400 0x400>, + <&apps_smmu 0x2420 0x400>, + <&apps_smmu 0x2460 0x400>, + <&apps_smmu 0x24E2 0x400>; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + dma-coherent; + iova-region-discard = <0xdff00000 0x300000>; + cam-smmu-label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x400>, + <&apps_smmu 0x24C0 0x400>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,cpas-cdm0 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm1_2"; + label = "cpas-cdm"; + reg = <0xac4d000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x4d000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife3", "ife4", "dualife"; + status = "ok"; + }; + + qcom,ife-cdm0 { + cell-index = <0>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacb4200 0x1000>; + reg-names = "ife-cdm0"; + reg-cam-base = <0xb4200>; + interrupts = ; + interrupt-names = "ife-cdm0"; + regulator-names = "camss","ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = "ife_0_ahb", + "ife_0_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + cdm-client-names = "ife0"; + status = "ok"; + }; + + qcom,ife-cdm1 { + cell-index = <1>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacc3200 0x1000>; + reg-names = "ife-cdm1"; + reg-cam-base = <0xc3200>; + interrupts = ; + interrupt-names = "ife-cdm1"; + regulator-names = "camss","ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = "ife_1_ahb", + "ife_1_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + cdm-client-names = "ife1"; + status = "ok"; + }; + + qcom,ife-cdm2 { + cell-index = <2>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacef200 0x1000>; + reg-names = "ife-cdm2"; + reg-cam-base = <0xef200>; + interrupts = ; + interrupt-names = "ife-cdm2"; + regulator-names = "camss","ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = "ife_2_ahb", + "ife_2_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&camcc CAM_CC_IFE_2_AHB_CLK>, + <&camcc CAM_CC_IFE_2_AREG_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + cdm-client-names = "ife2"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + cell-index = <0>; + compatible = "qcom,csid570"; + reg-names = "csid"; + reg = <0xacb5200 0x1000>; + reg-cam-base = <0xb5200>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_0_areg", + "ife_0_ahb", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0 0 338000000 0 100000000 0 0>, + <400000000 0 0 0 475000000 0 200000000 0 0>, + <400000000 0 0 0 600000000 0 300000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0 { + cell-index = <0>; + compatible = "qcom,vfe570"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb4000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xb4000 0x42000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_ahb", + "ife_0_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 100000000 338000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 600000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_0_areg"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1016 0x1026>; + cam_hw_pid = <28 4 16 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1 { + cell-index = <1>; + compatible = "qcom,csid570"; + reg-names = "csid"; + reg = <0xacc4200 0x1000>; + reg-cam-base = <0xc4200>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_1_areg", + "ife_1_ahb", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0 0 338000000 0 100000000 0 0>, + <400000000 0 0 0 475000000 0 200000000 0 0>, + <400000000 0 0 0 600000000 0 300000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1 { + cell-index = <1>; + compatible = "qcom,vfe570"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacc3000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xc3000 0x42000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_ahb", + "ife_1_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 100000000 338000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 600000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_1_areg"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1016 0x1026>; + cam_hw_pid = <29 5 17 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2 { + cell-index = <2>; + compatible = "qcom,csid570"; + reg-names = "csid"; + reg = <0xacf0200 0x1000>; + reg-cam-base = <0xf0200>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_2_areg", + "ife_2_ahb", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AREG_CLK>, + <&camcc CAM_CC_IFE_2_AHB_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <400000000 0 0 0 338000000 0 100000000 0 0>, + <400000000 0 0 0 475000000 0 200000000 0 0>, + <400000000 0 0 0 600000000 0 300000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2 { + cell-index = <2>; + compatible = "qcom,vfe570"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacef000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xef000 0x42000>; + interrupt-names = "ife2"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_ahb", + "ife_2_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_AHB_CLK>, + <&camcc CAM_CC_IFE_2_AREG_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <0 100000000 338000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 600000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_2_areg"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1016 0x1026>; + cam_hw_pid = <30 6 18 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0 { + cell-index = <3>; + compatible = "qcom,csid-lite570"; + reg-names = "csid-lite"; + reg = <0xacd9200 0x1000>; + reg-cam-base = <0xd9200>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0 { + cell-index = <3>; + compatible = "qcom,vfe-lite570"; + reg-names = "ife-lite"; + reg = <0xacd9000 0x2200>; + reg-cam-base = <0xd9000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <20>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1 { + cell-index = <4>; + compatible = "qcom,csid-lite570"; + reg-names = "csid-lite"; + reg = <0xacdb400 0x1000>; + reg-cam-base = <0xdb400>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1 { + cell-index = <4>; + compatible = "qcom,vfe-lite570"; + reg-names = "ife-lite"; + reg = <0xacdb200 0x2200>; + reg-cam-base = <0xdb200>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <19>; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + + clock-rates = + <100000000 0 400000000 0>, + <200000000 0 480000000 0>, + <300000000 0 600000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + fw_name = "CAMERA_ICP_480.elf"; + ubwc-ipe-fetch-cfg = <0x7073 0x707b>; + ubwc-ipe-write-cfg = <0x161cf 0x161ef>; + ubwc-bps-fetch-cfg = <0x7073 0x707b>; + ubwc-bps-write-cfg = <0x161cf 0x161ef>; + qos-val = <0x00000A0A>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac9a000 0x12000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x9a000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 450000000 0>, + <0 0 0 560000000 0>, + <0 0 0 700000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac7a000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x7a000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac53000 0x4000>; + reg-cam-base = <0x53000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <25 26>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac57000 0x4000>; + reg-cam-base = <0x57000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <24 27>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + qcom,cam-cpas { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac40000 0x1000>, + <0xac42000 0x8000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x40000 0x42000 0x0BBF0000>; + cam_hw_fuse = , + , + , + , + , + ; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 80000000 0 0 300000000 0>, + <0 0 80000000 0 0 400000000 0>, + <0 0 80000000 0 0 400000000 0>, + <0 0 80000000 0 0 480000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", + "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", + "ipe0", "cam-cdm-intf0","ife-cdm0", "ife-cdm1", + "ife-cdm2", "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", + "jpeg-enc0", "tpg13", "tpg14"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-rt0-wr1"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <10>; + node-name = "level1-rt0-rd0"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <11>; + node-name = "level1-rt0-wr2"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <12>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <13>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr1: level1-nrt0-wr1 { + cell-index = <14>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <15>; + node-name = "level1-nrt0-rd2"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife2_ubwc_stats_wr: ife2-ubwc-stats-wr { + cell-index = <16>; + node-name = "ife2-ubwc-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <17>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_stats_wr: ife1-ubwc-stats-wr { + cell-index = <18>; + node-name = "ife1-ubwc-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_linear_pdaf_wr: ife0-linear-pdaf-wr { + cell-index = <19>; + node-name = "ife0-linear-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_linear_pdaf_wr: ife1-linear-pdaf-wr { + cell-index = <20>; + node-name = "ife1-linear-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_linear_pdaf_wr: ife2-linear-pdaf-wr { + cell-index = <21>; + node-name = "ife2-linear-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_rdi_all_rd: ife0-rdi-all-rd { + cell-index = <22>; + node-name = "ife0-rdi-all-rd"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife1_rdi_all_rd: ife1-rdi-all-rd { + cell-index = <23>; + node-name = "ife1-rdi-all-rd"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife2_rdi_all_rd: ife2-rdi-all-rd { + cell-index = <24>; + node-name = "ife2-rdi-all-rd"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <27>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <28>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife4_rdi_all_wr: ife4-rdi-all-wr { + cell-index = <29>; + node-name = "ife4-rdi-all-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <30>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <31>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <32>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <33>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <34>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <35>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <36>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <37>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <38>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <39>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <40>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; +}; diff --git a/holi-camera-sensor-cdp.dtsi b/holi-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..f8f9b2c4 --- /dev/null +++ b/holi-camera-sensor-cdp.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vaf-supply = <&L5P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vaf", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 2800000 1056000 0>; + rgltr-load-current = <120000 80000 100000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&cam_cci1 { + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master= <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/holi-camera-sensor-mtp.dtsi b/holi-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..338305cf --- /dev/null +++ b/holi-camera-sensor-mtp.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vaf-supply = <&L5P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vaf", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 2800000 1056000 0>; + rgltr-load-current = <120000 80000 100000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*TPG0*/ + qcom,cam-tpg0 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*TPG1*/ + qcom,cam-tpg1 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*TPG2*/ + qcom,cam-tpg2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + +}; + +&cam_cci1 { + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master= <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/holi-camera-sensor-qrd.dtsi b/holi-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..f81b64cd --- /dev/null +++ b/holi-camera-sensor-qrd.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2880000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2880000 1056000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vaf-supply = <&L5P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vaf", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2880000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2880000 2800000 1056000 0>; + rgltr-load-current = <120000 80000 100000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&cam_cci1 { + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/holi-camera.dtsi b/holi-camera.dtsi new file mode 100644 index 00000000..c32e6298 --- /dev/null +++ b/holi-camera.dtsi @@ -0,0 +1,1063 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy"; + reg = <0x05C52000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1049000 1305000>; + rgltr-load-current = <0 0 15900 8900>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + clock-rates = + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <341330000 0 268800000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy"; + reg = <0x05C54000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x54000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1049000 1305000>; + rgltr-load-current = <0 15900 8900>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + clock-rates = + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <341330000 0 268800000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy"; + reg = <0x05C56000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x56000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1049000 1305000>; + rgltr-load-current = <0 15900 8900>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_2_CLK>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + clock-rates = + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <341330000 0 268800000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy"; + reg = <0x05C58000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x58000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1049000 1305000>; + rgltr-load-current = <0 15900 8900>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_3_CLK>, + <&gcc GCC_CAMSS_CSI3PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + clock-rates = + <240000000 0 200000000 0>, + <341330000 0 200000000 0>, + <341330000 0 268800000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_0_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 39 0>, + <&tlmm 40 0>, + <&tlmm 41 0>, + <&tlmm 42 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x05C1C000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1C000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_1_CLK>, + <&gcc GCC_CAMSS_CCI_1_CLK_SRC>; + clock-names = "cci_1_clk", + "cci_1_clk_src"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 43 0>, + <&tlmm 44 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xc20 0x000>, + <&apps_smmu 0xc40 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "ope", "ope-cdm"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xc00 0x000>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x5800>; + reg-cam-base = <0x11000 0x13000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 19200000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_CAMERA_CFG>; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = + <0 0>, <0 133333>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", + "lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1", + "svs_l1", "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "cci0", "cci1", "csid0", "csid1", "csid2", + "tfe0", "tfe1", "tfe2", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmrt_virt MASTER_CAMNOC_HF + &bimc SLAVE_EBI>; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmnrt_virt MASTER_CAMNOC_SF + &bimc SLAVE_EBI>; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe2_all_wr: tfe2-all-wr { + cell-index = <8>; + node-name = "tfe2-all-wr"; + client-name = "tfe2"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_1"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-priority-group = <0x3>; + cdm-client-names = "tfe0", "tfe1", "tfe2"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_1"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x5800>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <300000000 0 0 0 300000000 0>, + <426400000 0 0 0 460800000 0>, + <466500000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + ppi-enable; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <300000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <4>; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x5800>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <300000000 0 0 0 300000000 0>, + <426400000 0 0 0 460800000 0>, + <466500000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + ppi-enable; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <300000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <5>; + status = "ok"; + }; + + cam_tfe_csid2: qcom,tfe_csid2@5c7c000 { + cell-index = <2>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c7c000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x5800>; + reg-cam-base = <0x7c000 0x11000 0x13000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>; + clock-rates = + <300000000 0 0 0 300000000 0>, + <426400000 0 0 0 460800000 0>, + <466500000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + ppi-enable; + status = "ok"; + }; + + cam_tfe2: qcom,tfe2@5c7c000 { + cell-index = <2>; + compatible = "qcom,tfe530"; + reg-names = "tfe2"; + reg = <0x5c7c000 0x5000>; + reg-cam-base = <0x7c000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>; + clock-rates = + <300000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <6>; + status = "ok"; + }; + + cam_ppi0: qcom,ppi0@5cb3000 { + cell-index = <0>; + compatible = "qcom,ppi100"; + reg-names = "ppi0"; + reg = <0x5cb3000 0x200>; + reg-cam-base = <0xb3000>; + interrupt-names = "ppi0"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-names = "gcc_camss_cphy_0_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_ppi1: qcom,ppi1@5cb3200 { + cell-index = <1>; + compatible = "qcom,ppi100"; + reg-names = "ppi1"; + reg = <0x5cb3200 0x200>; + reg-cam-base = <0xb3200>; + interrupt-names = "ppi1"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-names = "gcc_camss_cphy_1_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_ppi2: qcom,ppi2@5cb3400 { + cell-index = <2>; + compatible = "qcom,ppi100"; + reg-names = "ppi2"; + reg = <0x5cb3400 0x200>; + reg-cam-base = <0xb3400>; + interrupt-names = "ppi2"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_2_CLK>; + clock-names = "gcc_camss_cphy_2_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_ppi3: qcom,ppi3@5cb3600 { + cell-index = <3>; + compatible = "qcom,ppi100"; + reg-names = "ppi3"; + reg = <0x5cb3600 0x200>; + reg-cam-base = <0xb3600>; + interrupt-names = "ppi3"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_3_CLK>; + clock-names = "gcc_camss_cphy_3_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpg101"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + cell-index = <1>; + compatible = "qcom,tpg101"; + reg-names = "tpg1", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0xA00>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk_src", + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 0 200000000 0>, + <171428571 0 266600000 0>, + <240000000 0 480000000 0>, + <240000000 0 580000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; +}; diff --git a/kalama-camera-sensor-cdp.dts b/kalama-camera-sensor-cdp.dts new file mode 100644 index 00000000..d163af7f --- /dev/null +++ b/kalama-camera-sensor-cdp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-camera-sensor-cdp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama CDP/RCM"; + compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp", "qcom,rcm", "qcom,kalama-rcm"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,board-id = <0x10001 0>, <0x1010001 0>, <0x10015 0>; +}; \ No newline at end of file diff --git a/kalama-camera-sensor-cdp.dtsi b/kalama-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..10a0005b --- /dev/null +++ b/kalama-camera-sensor-cdp.dtsi @@ -0,0 +1,869 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_ois: qcom,actuator3 { + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_hp1: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7N>; + cam_v_custom2-supply = <&L4N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000 2800000 0>; + rgltr-max-voltage = <2960000 2800000 0>; + rgltr-load-current = <103000 95000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_hp1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-max-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-load-current = <3500 913200 0 30000 91300>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + eeprom-src = <&eeprom_hp1>; + actuator-src= <&actuator_hp1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-max-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-load-current = <3500 913200 0 30000 91300>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator2{ + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>, + <&tlmm 206 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&i3c0 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <100000>; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator", "qcom,actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7N>; + i3c-i2c-target; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom", "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-i2c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/kalama-camera-sensor-hdk.dts b/kalama-camera-sensor-hdk.dts new file mode 100644 index 00000000..d1294115 --- /dev/null +++ b/kalama-camera-sensor-hdk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-camera-sensor-hdk.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama QRD"; + compatible = "qcom,kalama-qrd", "qcom,kalama", "qcom,qrd"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,board-id = <0x1001f 0>; +}; \ No newline at end of file diff --git a/kalama-camera-sensor-hdk.dtsi b/kalama-camera-sensor-hdk.dtsi new file mode 100644 index 00000000..d5766a13 --- /dev/null +++ b/kalama-camera-sensor-hdk.dtsi @@ -0,0 +1,659 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator2{ + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>, + <&tlmm 206 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c0 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <100000>; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator", "qcom,actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7N>; + i3c-i2c-target; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom", "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-i2c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/kalama-camera-sensor-mtp.dts b/kalama-camera-sensor-mtp.dts new file mode 100644 index 00000000..c60fe444 --- /dev/null +++ b/kalama-camera-sensor-mtp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama MTP"; + compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,board-id = <0x10008 0>; +}; \ No newline at end of file diff --git a/kalama-camera-sensor-mtp.dtsi b/kalama-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..d298a55b --- /dev/null +++ b/kalama-camera-sensor-mtp.dtsi @@ -0,0 +1,867 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_ois: qcom,actuator3 { + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_hp1: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7N>; + cam_v_custom2-supply = <&L4N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000 2800000 0>; + rgltr-max-voltage = <2960000 2800000 0>; + rgltr-load-current = <103000 95000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_hp1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-max-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-load-current = <3500 913200 0 30000 91300>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + eeprom-src = <&eeprom_hp1>; + actuator-src= <&actuator_hp1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-max-voltage = <1800000 1104000 0 3304000 2904000>; + rgltr-load-current = <3500 913200 0 30000 91300>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator2{ + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>, + <&tlmm 206 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c0 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <100000>; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator", "qcom,actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7N>; + i3c-i2c-target; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom", "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-i2c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2904000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/kalama-camera-sensor-qrd.dts b/kalama-camera-sensor-qrd.dts new file mode 100644 index 00000000..99b23fa7 --- /dev/null +++ b/kalama-camera-sensor-qrd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-camera-sensor-qrd.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama QRD"; + compatible = "qcom,kalama-qrd", "qcom,kalama", "qcom,qrd"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,board-id = <0x1000B 0>; +}; \ No newline at end of file diff --git a/kalama-camera-sensor-qrd.dtsi b/kalama-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..7e897b9e --- /dev/null +++ b/kalama-camera-sensor-qrd.dtsi @@ -0,0 +1,661 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4N>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 644000 0 95000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator2{ + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <10000 140400 0 52000 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>, + <&tlmm 206 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&S4G>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3N>; + cam_v_custom1-supply = <&L6N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 69 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&i3c0 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <100000>; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator", "qcom,actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7N>; + i3c-i2c-target; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom", "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-i2c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7M>; + cam_vaf-supply = <&L7N>; + cam_v_custom1-supply = <&L5M>; + i3c-target; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <3500 913200 0 91300 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/kalama-camera.dts b/kalama-camera.dts new file mode 100644 index 00000000..27b9f6ee --- /dev/null +++ b/kalama-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama v1 SoC"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,board-id = <0 0>; +}; \ No newline at end of file diff --git a/kalama-camera.dtsi b/kalama-camera.dtsi new file mode 100644 index 00000000..fb9aa842 --- /dev/null +++ b/kalama-camera.dtsi @@ -0,0 +1,3123 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio110"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio110"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio110"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio111"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio111"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio111"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio112"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio112"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio114"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_aon_i2c_active: cci_aon_i2c_active { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "aon_cci"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cci_aon_i2c_suspend: cci_aon_i2c_suspend { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "aon_cci"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + qcom,remote; + }; + }; + + cci_i2c_sda4_active: cci_i2c_sda4_active { + mux { + /* CLK, DATA */ + pins = "gpio74"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio74"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda4_suspend: cci_i2c_sda4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio74"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_active: cci_i2c_scl4_active { + mux { + /* CLK, DATA */ + pins = "gpio75"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio75"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_suspend: cci_i2c_scl4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio75"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_active: cci_i2c_sda5_active { + mux { + /* CLK, DATA */ + pins = "gpio0"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio0"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_suspend: cci_i2c_sda5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio0"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio0"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_active: cci_i2c_scl5_active { + mux { + /* CLK, DATA */ + pins = "gpio1"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio1"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_suspend: cci_i2c_scl5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio1"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio1"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_aon_mclk4"; + }; + + config { + pins = "gpio104"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_aon_mclk4"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_ponv_active: cam_sensor_ponv_active { + mux { + pins = "gpio206"; + function = "gpio"; + }; + + config { + pins = "gpio206"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_suspend: cam_sensor_ponv_suspend { + mux { + pins = "gpio206"; + function = "gpio"; + }; + + config { + pins = "gpio206"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0766>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18000 32000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xacea000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xea000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xacec000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18600 37900>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@acee000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xacee000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xee000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 950000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy6: qcom,csiphy6@acf0000 { + cell-index = <6>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xacf0000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xf0000>; + interrupt-names = "CSIPHY6"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18600 37900>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy6_clk", + "csi6phytimer_clk_src", + "csi6phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY6_CLK>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK>; + src-clock-name = "csi6phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy7: qcom,csiphy7@acf2000 { + cell-index = <7>; + compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy"; + reg = <0xacf2000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xf2000>; + interrupt-names = "CSIPHY7"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3E>; + csi-vdd-0p9-supply = <&L1E>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 875000>; + rgltr-max-voltage = <0 1200000 925000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy7_clk", + "csi7phytimer_clk_src", + "csi7phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY7_CLK>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK>; + src-clock-name = "csi7phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac15000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac16000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_aon_i2c_active>; + pinctrl-3 = <&cci_aon_i2c_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac17000 { + cell-index = <2>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac17000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x17000>; + interrupt-names = "CCI2"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_2_clk_src", + "cci_2_clk"; + clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_2_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>; + pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; + pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; + pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci2: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x20>; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0xf 0xffe00000>; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x00>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1800 0xC0>, + <&apps_smmu 0x1820 0x00>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0xf8c00000 0xf 0x07300000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 900MB long */ + iova-region-name = "shared"; + /* Start address: 0xc0800000 */ + iova-region-start = <0x0 0xc0800000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0xc0000000 */ + iova-region-start = <0x0 0xc0000000>; + /* Length: 0x700000 */ + iova-region-len = <0x0 0x700000>; + iova-region-id = <0x6>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf8c00000 */ + iova-region-start = <0x0 0xf8c00000>; + /* Length: 0xf07300000 */ + iova-region-len = <0xf 0x07300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0xc0700000 */ + iova-region-start = <0x0 0xc0700000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + multiple-client-devices; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac13000 0x1000>, + <0xac19000 0xa080>, + <0xbbf0000 0x1f00>; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "cam_cc_drv_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_axi_clk_src"; + clock-names-option = "cam_icp_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>; + clock-rates-option = <400000000>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "csiphy6","csiphy7", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "sfe0", "sfe1", "custom0", "custom1", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", + "cam-cdm-intf0", "bps0", "icp0", "cre0", + "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", + "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1", "large-2", "large-3", "large-4"; + sys-cache-uids = <34 52 38 51 50>; + enable-smart-qos; + enable-cam-drv = <(CAM_DDR_DRV)>; + rt-wr-priority-min = <3>; + rt-wr-priority-max = <6>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <100>; + rt-wr-leaststressed-clamp-threshold = <7>; + rt-wr-moststressed-clamp-threshold = <7>; + rt-wr-highstress-indicator-threshold = <100>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = "level1-ife-ubwc-linear-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x7630>; + priority-lut-high-offset = <0x7634>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <9>; + node-name = "level1-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x7C30>; + priority-lut-high-offset = <0x7C34>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x7A30>; + priority-lut-high-offset = <0x7A34>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <11>; + node-name = "level1-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x7830>; + priority-lut-high-offset = <0x7834>; + }; + + level1_rt0_rd: level1-rt0-rd { + cell-index = <12>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt1_wr: level1-nrt1-wr { + cell-index = <14>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt3_rd: level1-nrt3-rd { + cell-index = <15>; + node-name = "level1-nrt3-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt1_rd: level1-nrt1-rd { + cell-index = <16>; + node-name = "level1-nrt1-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <17>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_linear_wr: ife0-ubwc-linear-wr { + cell-index = <18>; + node-name = "ife0-ubwc-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_linear_wr: ife1-ubwc-linear-wr { + cell-index = <19>; + node-name = "ife1-ubwc-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_linear_wr: ife2-ubwc-linear-wr { + cell-index = <20>; + node-name = "ife2-ubwc-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <21>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <22>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <23>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe0_all_wr: sfe0-all-wr { + cell-index = <24>; + node-name = "sfe0-all-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe1_all_wr: sfe1-all-wr { + cell-index = <25>; + node-name = "sfe1-all-wr"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + custom0_wr: custom0-wr { + cell-index = <26>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_wr>; + }; + + custom1_wr: custom1-wr { + cell-index = <27>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <28>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_wr: ife1-pdaf-wr { + cell-index = <29>; + node-name = "ife1-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_wr: ife2-pdaf-wr { + cell-index = <30>; + node-name = "ife2-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <31>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <32>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <33>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <34>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <35>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <36>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + sfe1_all_rd: sfe1-all-rd { + cell-index = <37>; + node-name = "sfe1-all-rd"; + client-name = "sfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + custom0_all_rd: custom0-rd { + cell-index = <38>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd>; + }; + + custom1_rd: custom1-rd { + cell-index = <39>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <40>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <41>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <42>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <43>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <44>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + + jpeg_enc1_all_wr: jpeg-enc1-all-wr { + cell-index = <45>; + node-name = "jpeg-enc1-all-wr"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + jpeg_dma1_all_wr: jpeg-dma1-all-wr { + cell-index = <46>; + node-name = "jpeg-dma1-all-wr"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <47>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt3_rd>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <48>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt3_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <49>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <50>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + + jpeg_enc1_all_rd: jpeg1-enc1-all-rd { + cell-index = <51>; + node-name = "jpeg-enc1-rd"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + jpeg_dma1_all_rd: jpeg1-dma1-all-rd { + cell-index = <52>; + node-name = "jpeg-dma1-rd"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <53>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <54>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <55>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <56>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <57>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <58>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm4_all_rd: rt-cdm4-all-rd { + cell-index = <59>; + node-name = "rt-cdm4-all-rd"; + client-name = "rt-cdm4"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <60>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac25000 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac26000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac26000 0x400>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac27000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac27000 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x27000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2", "dualife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac28000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac28000 0x400>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x28000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm4@ac29000 { + cell-index = <4>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac29000 0x400>; + reg-names = "rt-cdm4"; + reg-cam-base = <0x29000>; + interrupt-names = "rt-cdm4"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife4"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <30>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe780"; + reg-names = "sfe0"; + reg = <0xac9e000 0x8000>; + reg-cam-base = <0x9e000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe0"; + interrupts = ; + regulator-names = "gdsc", "sfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe0-supply = <&cam_cc_sfe_0_gdsc>; + clock-names = + "sfe_0_fast_ahb", + "sfe_0_clk_src", + "sfe_0_clk", + "cam_cc_cpas_sfe_0_clk"; + clocks = + <&camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK>, + <&camcc CAM_CC_CPAS_SFE_0_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_0_clk_src"; + cam_hw_pid = <11 4>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe1: qcom,sfe1@aca6000 { + cell-index = <1>; + compatible = "qcom,sfe780"; + reg-names = "sfe1"; + reg = <0xaca6000 0x8000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe1"; + interrupts = ; + regulator-names = "gdsc", "sfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe1-supply = <&cam_cc_sfe_1_gdsc>; + clock-names = + "sfe_1_fast_ahb", + "sfe_1_clk_src", + "sfe_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clocks = + <&camcc CAM_CC_SFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_1_CLK_SRC>, + <&camcc CAM_CC_SFE_1_CLK>, + <&camcc CAM_CC_CPAS_SFE_1_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_1_clk_src"; + cam_hw_pid = <12 5>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid780"; + reg-names = "csid", "csid_top"; + reg = <0xacb7000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb7000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe780"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac62000 0xf000>, + <0xac19000 0xa080>; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "gdsc", "ife0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clocks = + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_0_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 20 24 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acb9000 { + cell-index = <1>; + compatible = "qcom,csid780"; + reg-names = "csid", "csid_top"; + reg = <0xacb9000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb9000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac71000 { + cell-index = <1>; + compatible = "qcom,vfe780"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac71000 0xf000>, + <0xac19000 0xa080>; + reg-cam-base = <0x71000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "gdsc", "ife1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clocks = + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_1_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 21 25 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acbb000 { + cell-index = <2>; + compatible = "qcom,csid780"; + reg-names = "csid", "csid_top"; + reg = <0xacbb000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xbb000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@ac80000 { + cell-index = <2>; + compatible = "qcom,vfe780"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac80000 0xf000>, + <0xac19000 0xa080>; + reg-cam-base = <0x80000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife2"; + interrupts = ; + regulator-names = "gdsc", "ife2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_fast_ahb", + "ife_2_clk_src", + "ife_2_clk", + "cam_cc_cpas_ife_2_clk"; + clocks = + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_2_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <18 22 26 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acca000 { + cell-index = <3>; + compatible = "qcom,csid-lite780"; + reg-names = "csid-lite"; + reg = <0xacca000 0xa00>; + reg-cam-base = <0xca000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acca000 { + cell-index = <3>; + compatible = "qcom,vfe-lite780"; + reg-names = "ife-lite"; + reg = <0xacca000 0x2800>; + reg-cam-base = <0xca000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@acce000 { + cell-index = <4>; + compatible = "qcom,csid-lite780"; + reg-names = "csid-lite"; + reg = <0xacce000 0xa00>; + reg-cam-base = <0xce000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@acce000 { + cell-index = <4>; + compatible = "qcom,vfe-lite780"; + reg-names = "ife-lite"; + reg = <0xacce000 0x2800>; + reg-cam-base = <0xce000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <28>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg1031"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg1031"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xacf7000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf7000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg1031"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xacf8000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf8000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v2"; + icp-version = <0x0200>; + reg = <0xac01000 0x400>, + <0xac01800 0x400>, + <0x0ac04000 0x1000>; + reg-names = "icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x808>; + cam_hw_pid = <12>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CPAS_IPE_NPS_CLK>; + clock-rates = + <0 0 0 455000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <14 31 15>; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps680"; + reg = <0xac2c000 0xb000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_CPAS_BPS_CLK>; + clock-rates = + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 480000000 0 0>, + <0 0 785000000 0 0>, + <0 0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <0 2>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc"; + reg = <0xac2a000 0x1000>, + <0xac19000 0xa080>; + reg-cam-base = <0x2a000 0x19000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@ac2b000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg = <0xac2b000 0x1000>, + <0xac19000 0xa080>; + reg-cam-base = <0x2b000 0x19000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +}; diff --git a/kalama-sg-hhg-camera-sensor.dts b/kalama-sg-hhg-camera-sensor.dts new file mode 100644 index 00000000..19baca5a --- /dev/null +++ b/kalama-sg-hhg-camera-sensor.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-sg-hhg-camera-sensor.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama SG HHG"; + compatible = "qcom,kalama-hhg", "qcom,kalama", "qcom,hhg"; + qcom,msm-id = <600 0x20000>, <601 0x20000>; + qcom,board-id = <0x1001f 0x1>; +}; \ No newline at end of file diff --git a/kalama-sg-hhg-camera-sensor.dtsi b/kalama-sg-hhg-camera-sensor.dtsi new file mode 100644 index 00000000..dbbb4ce2 --- /dev/null +++ b/kalama-sg-hhg-camera-sensor.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-sensor0 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L7N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000>; + rgltr-load-current = <120000 1200000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + qcom,cam-sensor1 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 1200000 0 2800000>; + rgltr-load-current = <120000 1200000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/kalama-sg-hhg-camera.dts b/kalama-sg-hhg-camera.dts new file mode 100644 index 00000000..c0e58d1f --- /dev/null +++ b/kalama-sg-hhg-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kalama-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kalama SG HHG"; + compatible = "qcom,kalama-hhg", "qcom,kalama", "qcom,hhg"; + qcom,msm-id = <600 0x20000>, <601 0x20000>; + qcom,board-id = <0 0>; +}; \ No newline at end of file diff --git a/kona-camera-sensor-cdp.dtsi b/kona-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..c039a708 --- /dev/null +++ b/kona-camera-sensor-cdp.dtsi @@ -0,0 +1,679 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_wide: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_uw: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom_triple_wide>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 1056000 0 2856000>; + rgltr-max-voltage = <0 3000000 1056000 0 3104000>; + rgltr-load-current = <0 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3600000 0>; + rgltr-max-voltage = <0 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3600000 0>; + rgltr-max-voltage = <1800000 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/kona-camera-sensor-mtp.dtsi b/kona-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..a35e40d1 --- /dev/null +++ b/kona-camera-sensor-mtp.dtsi @@ -0,0 +1,680 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_wide: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom_triple_wide>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3600000 0>; + rgltr-max-voltage = <0 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3600000 0>; + rgltr-max-voltage = <1800000 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/kona-camera-sensor-qrd.dtsi b/kona-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..8dea38e6 --- /dev/null +++ b/kona-camera-sensor-qrd.dtsi @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + led_flash_rear: qcom,camera-flash0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_wide: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_uw: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom_triple_wide>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3600000 0>; + rgltr-max-voltage = <0 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3600000 0>; + rgltr-max-voltage = <1800000 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/kona-camera-sensor-xr.dtsi b/kona-camera-sensor-xr.dtsi new file mode 100644 index 00000000..5708e84f --- /dev/null +++ b/kona-camera-sensor-xr.dtsi @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + shared-gpios = <84 83 82 114 145>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + pinctrl-0 = <&cam_sensor_6dof_vana_active + &cam_sensor_6dof_vdig_active + &cam_sensor_6dof_vio_active + &cam_sensor_active_6 + &cam_sensor_et_vio_active>; + pinctrl-1 = <&cam_sensor_6dof_vana_suspend + &cam_sensor_6dof_vdig_suspend + &cam_sensor_6dof_vio_suspend + &cam_sensor_suspend_6 + &cam_sensor_et_vio_suspend>; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_wide: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Left (Master) */ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rgbleft>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rgbleft>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2", + "CAM_VIO2", + "CAM_VDIG2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Right(Slave) */ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rgbright>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rgbright>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA3", + "CAM_VIO3", + "CAM_VDIG3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* 6DOF Left (Slave) */ + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <6000000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_6dofright>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_6dofright>; + gpios = <&tlmm 98 0>, + <&tlmm 131 0>, + <&tlmm 84 0>, + <&tlmm 83 0>, + <&tlmm 82 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4", + "CAM_VIO4", + "CAM_VDIG4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* 6DOF Right (Master) */ + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <6000000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_6dofleft>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_6dofleft>; + gpios = <&tlmm 99 0>, + <&tlmm 130 0>, + <&tlmm 84 0>, + <&tlmm 83 0>, + <&tlmm 82 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5", + "CAM_VANA5", + "CAM_VIO5", + "CAM_VDIG5"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3600000 0>; + rgltr-max-voltage = <0 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* ET LEFT (Master) */ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_etleft>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_etleft>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>, + <&tlmm 114 0>, + <&tlmm 145 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA0", + "CAM_VIO0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* ET RIGHT (Left) */ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_etright>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_etright>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>, + <&tlmm 114 0>, + <&tlmm 145 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1", + "CAM_VIO1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + +}; diff --git a/kona-camera.dtsi b/kona-camera.dtsi new file mode 100644 index 00000000..04b27fcc --- /dev/null +++ b/kona-camera.dtsi @@ -0,0 +1,1748 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy@ac6a000 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x0ac6a000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6a000>; + interrupts = ; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + regulator-names = "gdscr", "refgen"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150_l9>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy@ac6c000 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xac6c000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6c000>; + interrupts = ; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + regulator-names = "gdscr", "refgen"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150_l9>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy@ac6e000 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xac6e000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6e000>; + interrupts = ; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + regulator-names = "gdscr", "refgen"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150_l9>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy@ac70000 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xac70000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x70000>; + interrupts = ; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + regulator-names = "gdscr", "refgen"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150_l9>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy@ac72000 { + cell-index = <4>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xac72000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x72000>; + interrupts = ; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + regulator-names = "gdscr", "refgen"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150_l9>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY4_CLK>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy@ac74000 { + cell-index = <5>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xac74000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x74000>; + interrupts = ; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + regulator-names = "gdscr", "refgen"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150_l9>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY5_CLK>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci@ac4f000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac4f000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4f000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 101 0>, + <&tlmm 102 0>, + <&tlmm 103 0>, + <&tlmm 104 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci@ac50000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac50000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x50000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + gpios = <&tlmm 105 0>, + <&tlmm 106 0>, + <&tlmm 107 0>, + <&tlmm 108 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x400>, + <&apps_smmu 0x840 0x400>, + <&apps_smmu 0xC00 0x400>, + <&apps_smmu 0xC40 0x400>; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + cam-smmu-label = "ife", "ife-cdm"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2040 0x400>, + <&apps_smmu 0x2440 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20E2 0x400>, + <&apps_smmu 0x24E2 0x400>, + <&apps_smmu 0x2000 0x400>, + <&apps_smmu 0x2001 0x400>, + <&apps_smmu 0x2400 0x400>, + <&apps_smmu 0x2401 0x400>, + <&apps_smmu 0x2060 0x400>, + <&apps_smmu 0x2061 0x400>, + <&apps_smmu 0x2460 0x400>, + <&apps_smmu 0x2461 0x400>, + <&apps_smmu 0x2020 0x400>, + <&apps_smmu 0x2021 0x400>, + <&apps_smmu 0x2420 0x400>, + <&apps_smmu 0x2421 0x400>; + cam-smmu-label = "icp"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xdff00000 0x300000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x400>, + <&apps_smmu 0x24C0 0x400>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_fd { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2080 0x400>, + <&apps_smmu 0x2480 0x400>; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + cam-smmu-label = "fd"; + fd_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x8000>; + reg-cam-base = <0x40000 0x42000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CORE_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0 0>, + <0 0 0 19200000 0 0 19200000 0>, + <0 0 0 80000000 0 0 300000000 0>, + <0 0 0 80000000 0 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0>, + <0 0 0 80000000 0 0 480000000 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "minsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", + "csid4", "csid5", "csid6", "ife0", + "ife1", "ife2", "ife3", "custom0", + "ipe0", "cam-cdm-intf0", "cpas-cdm0", + "ife-cdm0", "ife-cdm1", "bps0", "icp0", + "jpeg-dma0", "jpeg-enc0", "fd0"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_icp"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_icp_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-rt0-wr1"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <10>; + node-name = "level1-rt0-rd0"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <11>; + node-name = "level1-rt0-wr2"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <12>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <13>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr1: level1-nrt0-wr1 { + cell-index = <14>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd2: level1-nrt0-rd2 { + cell-index = <15>; + node-name = "level1-nrt0-rd2"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <16>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_stats_wr: ife1-ubwc-stats-wr { + cell-index = <17>; + node-name = "ife1-ubwc-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_linear_pdaf_wr: ife0-linear-pdaf-wr { + cell-index = <18>; + node-name = "ife0-linear-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_linear_pdaf_wr: ife1-linear-pdaf-wr { + cell-index = <19>; + node-name = "ife1-linear-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_rdi_all_wr: ife2-rdi-all-wr { + cell-index = <20>; + node-name = "ife2-rdi-all-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <21>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_rdi_all_rd: ife0-rdi-all-rd { + cell-index = <22>; + node-name = "ife0-rdi-all-rd"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife1_rdi_all_rd: ife1-rdi-all-rd { + cell-index = <23>; + node-name = "ife1-rdi-all-rd"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom0_all_rd: custom0-all-rd { + cell-index = <24>; + node-name = "custom0-all-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + custom0_all_wr: custom0-all-wr { + cell-index = <27>; + node-name = "custom0-all-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <28>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <29>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <30>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <31>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <32>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <33>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <34>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <35>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd2>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <36>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd2>; + }; + + fd0_all_wr: fd0-all-wr { + cell-index = <37>; + node-name = "fd0-all-wr"; + client-name = "fd0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_wr>; + }; + + fd0_all_rd: fd0-all-rd { + cell-index = <38>; + node-name = "fd0-all-rd"; + client-name = "fd0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <39>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <40>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <3>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "fd"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm@ac4d000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm1_2"; + label = "cpas-cdm"; + reg = <0xac4d000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x4d000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife2", "ife3", "ife4", "ife5", "ife6", "dualife"; + status = "ok"; + }; + + qcom,ife-cdm0@acb4200 { + cell-index = <0>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacb4200 0x1000>; + reg-names = "ife-cdm0"; + reg-cam-base = <0xb4200>; + interrupts = ; + interrupt-names = "ife-cdm0"; + regulator-names = "camss","ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = "ife_0_ahb", + "ife_0_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife0"; + status = "ok"; + }; + + qcom,ife-cdm1@acc3200 { + cell-index = <1>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacc3200 0x1000>; + reg-names = "ife-cdm1"; + reg-cam-base = <0xc3200>; + interrupts = ; + interrupt-names = "ife-cdm1"; + regulator-names = "camss","ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = "ife_1_ahb", + "ife_1_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife1"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb5200 { + cell-index = <0>; + compatible = "qcom,csid480"; + reg-names = "csid"; + reg = <0xacb5200 0x1000>; + reg-cam-base = <0xb5200>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_0_areg", + "ife_0_ahb", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 400000000 0 350000000 0 100000000 0 0>, + <400000000 0 400000000 0 475000000 0 200000000 0 0>, + <400000000 0 400000000 0 576000000 0 300000000 0 0>, + <400000000 0 400000000 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@acb4000 { + cell-index = <0>; + compatible = "qcom,vfe480"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb4000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xb4000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_0_ahb", + "ife_0_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 100000000 350000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 576000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_0_areg"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1026 0x1036>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acc4200 { + cell-index = <1>; + compatible = "qcom,csid480"; + reg-names = "csid"; + reg = <0xacc4200 0x1000>; + reg-cam-base = <0xc4200>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_1_areg", + "ife_1_ahb", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 400000000 0 350000000 0 100000000 0 0>, + <400000000 0 400000000 0 475000000 0 200000000 0 0>, + <400000000 0 400000000 0 576000000 0 300000000 0 0>, + <400000000 0 400000000 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@acc3000 { + cell-index = <1>; + compatible = "qcom,vfe480"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacc3000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xc3000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_1_ahb", + "ife_1_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 100000000 350000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 576000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_1_areg"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1026 0x1036>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acd9200 { + cell-index = <2>; + compatible = "qcom,csid-lite480"; + reg-names = "csid-lite"; + reg = <0xacd9200 0x1000>; + reg-cam-base = <0xd9200>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acd9000 { + cell-index = <2>; + compatible = "qcom,vfe-lite480"; + reg-names = "ife-lite"; + reg = <0xacd9000 0x2200>; + reg-cam-base = <0xd9000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@acdb400 { + cell-index = <3>; + compatible = "qcom,csid-lite480"; + reg-names = "csid-lite"; + reg = <0xacdb400 0x1000>; + reg-cam-base = <0xdb400>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@acdb200 { + cell-index = <3>; + compatible = "qcom,vfe-lite480"; + reg-names = "ife-lite"; + reg = <0xacdb200 0x2200>; + reg-cam-base = <0xdb200>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + + clock-rates = + <100000000 0 400000000 0>, + <200000000 0 480000000 0>, + <300000000 0 600000000 0>, + <400000000 0 600000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac9a000 0xc000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x9a000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 475000000 0>, + <0 0 0 525000000 0>, + <0 0 0 700000000 0>, + <0 0 0 700000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac7a000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x7a000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_AREG_CLK>, + <&clock_camcc CAM_CC_BPS_AXI_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac53000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac53000 0x4000>; + reg-cam-base = <0x53000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac57000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac57000 0x4000>; + reg-cam-base = <0x57000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-fd { + compatible = "qcom,cam-fd"; + compat-hw-name = "qcom,fd"; + num-fd = <1>; + status = "ok"; + }; + + cam_fd: qcom,fd@ac5f000 { + cell-index = <0>; + compatible = "qcom,fd600"; + reg-names = "fd_core", "fd_wrapper"; + reg = <0xac5f000 0x1000>, + <0xac60000 0x400>; + reg-cam-base = <0x5f000 0x60000>; + interrupt-names = "fd"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "fd_core_clk_src", + "fd_core_clk", + "fd_core_uar_clk"; + clocks = + <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>, + <&clock_camcc CAM_CC_FD_CORE_CLK>, + <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>; + src-clock-name = "fd_core_clk_src"; + clock-control-debugfs = "true"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + status = "ok"; + }; +}; diff --git a/lagoon-camera-sensor-cdp.dtsi b/lagoon-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..e0a69fe1 --- /dev/null +++ b/lagoon-camera-sensor-cdp.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_v_custom1-supply = <&S2A>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lagoon-camera-sensor-mtp.dtsi b/lagoon-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..e0a69fe1 --- /dev/null +++ b/lagoon-camera-sensor-mtp.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_v_custom1-supply = <&S2A>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi new file mode 100644 index 00000000..ae42b7bf --- /dev/null +++ b/lagoon-camera.dtsi @@ -0,0 +1,1484 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0x0ac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac68000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x68000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 39 0>, + <&tlmm 40 0>, + <&tlmm 41 0>, + <&tlmm 42 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "cci_clk", + "cci_1_clk_src"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 43 0>, + <&tlmm 44 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + non-fatal-fault-disabled; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xD40 0x20>, + <&apps_smmu 0xD60 0x20>; + cam-smmu-label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0xc0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0xc0>, + <&apps_smmu 0x880 0x0>; + cam-smmu-label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xD00 0x20>, + <&apps_smmu 0xD20 0x20>; + cam-smmu-label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xCA2 0x0>, + <&apps_smmu 0xCC0 0x20>, + <&apps_smmu 0xCE0 0x20>; + cam-smmu-label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + iova-granularity = <0x15>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10A00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3 GB */ + iova-region-name = "io"; + iova-region-start = <0x10C00000>; + iova-region-len = <0xCF300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* qdss region is approximately 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10B00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xC80 0x0>; + cam-smmu-label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk"; + clocks = + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = <0 0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid170_200"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0 0>, + <384000000 0 0 0 404000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe170_150"; + reg-names = "ife"; + reg = <0xacaf000 0x4000>; + reg-cam-base = <0xaf000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <320000000 0 0>, + <404000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid170_200"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0 0>, + <384000000 0 0 0 404000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe170_150"; + reg-names = "ife"; + reg = <0xacb6000 0x4000>; + reg-cam-base = <0xb6000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <320000000 0 0>, + <404000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acc1000 { + cell-index = <2>; + compatible = "qcom,csid170_200"; + reg-names = "csid2"; + reg = <0xacc1000 0x1000>; + reg-cam-base = <0xc1000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0 0>, + <384000000 0 0 0 404000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe2: qcom,vfe2@acbd000 { + cell-index = <2>; + compatible = "qcom,vfe170_150"; + reg-names = "ife2"; + reg = <0xacbd000 0x4000>; + reg-cam-base = <0xbd000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <320000000 0 0>, + <404000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid_lite: qcom,csid-lite@acc8000 { + cell-index = <3>; + compatible = "qcom,csid-lite170"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0>, + <384000000 0 0 0 400000000 0>, + <400000000 0 0 0 480000000 0>, + <400000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe_lite: qcom,vfe-lite@acc4000 { + cell-index = <3>; + compatible = "qcom,vfe-lite170"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + }; + + cam_icp: qcom,icp@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "soc_ahb_clk", + "icp_clk", + "icp_clk_src"; + src-clock-name = "icp_clk_src"; + clocks = + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>; + + clock-rates = + <100000000 0 0 384000000>, + <200000000 0 0 404000000>, + <300000000 0 0 600000000>, + <404000000 0 0 600000000>, + <404000000 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0xa000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk", + "ipe_0_clk_src"; + src-clock-name = "ipe_0_clk_src"; + clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>; + + clock-rates = + <0 0 0 0 240000000>, + <0 0 0 0 320000000>, + <0 0 0 0 404000000>, + <0 0 0 0 538666666>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk", + "bps_clk_src"; + src-clock-name = "bps_clk_src"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>; + + clock-rates = + <0 0 0 0 200000000>, + <0 0 0 0 404000000>, + <0 0 0 0 480000000>, + <0 0 0 0 600000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = + <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@0xac52000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = + <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "lrme_clk_src", + "lrme_clk"; + clocks = + <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-rates = + <200000000 0>, + <269333333 0>, + <323200000 0>, + <404000000 0>, + <404000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr"; + reg = <0xac40000 0x1000>, + <0xac42000 0x4600>, + <0x01fc0000 0x40000>; + reg-cam-base = <0x40000 0x42000 0x0>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + qcom,cpas-hw-ver = <0x170200>; /* Titan v170 v2.0.0 */ + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "slow_ahb_clk_src"; + clock-rates = + <0 0 0 0 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0", + "cci1", "csid0", "csid1", "csid2", "csid3", + "ife0", "ife1", "ife2", "ife3", "ipe0", + "cam-cdm-intf0", "cpas-cdm0", "bps0", + "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_wr_sum: level3-rt0-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_hf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_sf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_icp"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_icp_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_sf_icp_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level2-nodes { + level-index = <2>; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd_wr: level2-nrt0-rd-wr { + cell-index = <4>; + node-name = "level2-nrt0-rd-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <5>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + level1_rt0_wr: level1-rt0-wr { + cell-index = <6>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt1_wr: level1-rt1-wr { + cell-index = <7>; + node-name = "level1-rt1-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr: level1-nrt0-wr { + cell-index = <8>; + node-name = "level1-nrt0-wr"; + parent-node = <&level2_nrt0_rd_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <9>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt0_rd_wr>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + + ife0_rdi_all_wr: ife0-rdi-all-wr { + cell-index = <10>; + node-name = "ife0-rdi-all-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife1_rdi_all_wr: ife1-rdi-all-wr { + cell-index = <11>; + node-name = "ife1-rdi-all-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife2_rdi_all_wr: ife2-rdi-all-wr { + cell-index = <12>; + node-name = "ife2-rdi-all-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <13>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pixelall_wr: ife0-pixelall-wr { + cell-index = <14>; + node-name = "ife0-pixelall-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife1_pixelall_wr: ife1-pixelall-wr { + cell-index = <15>; + node-name = "ife1-pixelall-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife2_pixelall_wr: ife2-pixelall-wr { + cell-index = <16>; + node-name = "ife2-pixelall-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <17>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <18>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <19>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <20>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <21>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <22>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <23>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + jpeg0_all_wr: jpeg0-all-wr { + cell-index = <24>; + node-name = "jpeg0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + jpeg0_all_rd: jpeg0-all-rd { + cell-index = <25>; + node-name = "jpeg0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <26>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; +}; diff --git a/lahaina-camera-sensor-cdp.dtsi b/lahaina-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..0a5f1deb --- /dev/null +++ b/lahaina-camera-sensor-cdp.dtsi @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + ois0: qcom,ois0 { + cell-index = <0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_tele: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l2>; + cam_v_custom2-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_v_custom2", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 950000 1000000 0 + 2700000>; + rgltr-max-voltage = <1800000 2900000 1900000 1150000 1200000 0 + 3000000>; + rgltr-load-current = <15000 52000 72000 140000 250000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 2700000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3000000>; + rgltr-load-current = <5000 68000 74000 805000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_tof2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1170000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 2040000 0 2800000 3600000>; + rgltr-load-current = <200000 680000 0 50000 29000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_ext_rgb0: qcom,eeprom7 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3 + &cam_sensor_active_ext_regs0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3 + &cam_sensor_suspend_ext_regs0>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_EXT_REGS0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3960000>; + rgltr-load-current = <5000 68000 74000 805000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1170000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 2040000 0 2800000 3600000>; + rgltr-load-current = <200000 680000 0 50000 29000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor6 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + ois-src = <&ois0>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l2>; + cam_v_custom2-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_v_custom2","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 950000 1000000 0 + 3200000>; + rgltr-max-voltage = <1800000 2900000 1900000 1150000 1200000 0 + 3960000>; + rgltr-load-current = <15000 52000 72000 140000 250000 0 + 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor7 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_ext_rgb0>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3 + &cam_sensor_active_ext_regs0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3 + &cam_sensor_suspend_ext_regs0>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_EXT_REGS0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_tof1: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0>; + rgltr-max-voltage = <1800000 2900000 1150000 0>; + rgltr-load-current = <5000 35000 301000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_ext_rgb1: qcom,eeprom8 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_active_ext_regs1>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_suspend_ext_regs1>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_EXT_REGS1"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <5000 35000 301000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor8 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_ext_rgb1>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_active_ext_regs1>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_suspend_ext_regs1>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_EXT_REGS1"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; diff --git a/lahaina-camera-sensor-hdk.dtsi b/lahaina-camera-sensor-hdk.dtsi new file mode 100644 index 00000000..69dd62b3 --- /dev/null +++ b/lahaina-camera-sensor-hdk.dtsi @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&cam_cci0 { +/delete-node/ qcom,cam-sensor0; +/delete-node/ qcom,cam-sensor1; + + qcom,cam-sensor0 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1050000 0 3200000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3960000>; + rgltr-load-current = <5000 68000 74000 805000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { +/delete-node/ qcom,cam-sensor2; +/delete-node/ qcom,cam-sensor5; + + qcom,cam-sensor2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <5000 35000 301000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; diff --git a/lahaina-camera-sensor-mtp.dtsi b/lahaina-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..0a5f1deb --- /dev/null +++ b/lahaina-camera-sensor-mtp.dtsi @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + ois0: qcom,ois0 { + cell-index = <0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_tele: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l2>; + cam_v_custom2-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_v_custom2", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 950000 1000000 0 + 2700000>; + rgltr-max-voltage = <1800000 2900000 1900000 1150000 1200000 0 + 3000000>; + rgltr-load-current = <15000 52000 72000 140000 250000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 2700000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3000000>; + rgltr-load-current = <5000 68000 74000 805000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_tof2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1170000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 2040000 0 2800000 3600000>; + rgltr-load-current = <200000 680000 0 50000 29000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_ext_rgb0: qcom,eeprom7 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3 + &cam_sensor_active_ext_regs0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3 + &cam_sensor_suspend_ext_regs0>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_EXT_REGS0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3960000>; + rgltr-load-current = <5000 68000 74000 805000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1170000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 2040000 0 2800000 3600000>; + rgltr-load-current = <200000 680000 0 50000 29000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor6 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + ois-src = <&ois0>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l2>; + cam_v_custom2-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_v_custom2","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 950000 1000000 0 + 3200000>; + rgltr-max-voltage = <1800000 2900000 1900000 1150000 1200000 0 + 3960000>; + rgltr-load-current = <15000 52000 72000 140000 250000 0 + 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor7 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_ext_rgb0>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3 + &cam_sensor_active_ext_regs0>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3 + &cam_sensor_suspend_ext_regs0>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_EXT_REGS0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_tof1: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0>; + rgltr-max-voltage = <1800000 2900000 1150000 0>; + rgltr-load-current = <5000 35000 301000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_ext_rgb1: qcom,eeprom8 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_active_ext_regs1>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_suspend_ext_regs1>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_EXT_REGS1"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <5000 35000 301000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor8 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_ext_rgb1>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <10000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_active_ext_regs1>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_suspend_ext_regs1>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_EXT_REGS1"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; diff --git a/lahaina-camera-sensor-qrd.dtsi b/lahaina-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..6677f33d --- /dev/null +++ b/lahaina-camera-sensor-qrd.dtsi @@ -0,0 +1,529 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_tele: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_wide: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_tele: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1050000 0 2700000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3000000>; + rgltr-load-current = <5000 68000 74000 805000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_tof2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1170000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 2040000 0 2800000 3600000>; + rgltr-load-current = <200000 680000 0 50000 29000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1050000 0 3200000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3960000>; + rgltr-load-current = <5000 68000 74000 805000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1170000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 2040000 0 2800000 3600000>; + rgltr-load-current = <200000 680000 0 50000 29000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_tof1: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0>; + rgltr-max-voltage = <1800000 2900000 1150000 0>; + rgltr-load-current = <5000 35000 301000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 116 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <5000 35000 301000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; diff --git a/lahaina-camera.dtsi b/lahaina-camera.dtsi new file mode 100644 index 00000000..522a9d3b --- /dev/null +++ b/lahaina-camera.dtsi @@ -0,0 +1,1935 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0x0ac6a000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6a000>; + interrupts = ; + interrupt-names = "csiphy0"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1208000 888000>; + rgltr-load-current = <0 54000 96400>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac6c000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6c000>; + interrupts = ; + interrupt-names = "csiphy1"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1208000 888000>; + rgltr-load-current = <0 54000 96400>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <400000000 0 300000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac6e000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6e000>; + interrupts = ; + interrupt-names = "csiphy2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1208000 888000>; + rgltr-load-current = <0 54000 96400>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac70000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x70000>; + interrupts = ; + interrupt-names = "csiphy3"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1208000 888000>; + rgltr-load-current = <0 54000 96400>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4 { + cell-index = <4>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac72000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x72000>; + interrupts = ; + interrupt-names = "csiphy4"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1208000 888000>; + rgltr-load-current = <0 54000 96400>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY4_CLK>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5 { + cell-index = <5>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac74000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x74000>; + interrupts = ; + interrupt-names = "csiphy5"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&pm8350_l6>; + csi-vdd-0p9-supply = <&pm8350_l5>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1208000 888000>; + rgltr-load-current = <0 54000 96400>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY5_CLK>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac4f000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4f000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 107 0>, + <&tlmm 108 0>, + <&tlmm 109 0>, + <&tlmm 110 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac50000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x50000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + gpios = <&tlmm 111 0>, + <&tlmm 112 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x440>, + <&apps_smmu 0x840 0x440>, + <&apps_smmu 0xC00 0x440>, + <&apps_smmu 0xC40 0x440>; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + cam-smmu-label = "ife", "ife-cdm"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2040 0x400>, + <&apps_smmu 0x2440 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20E2 0x400>, + <&apps_smmu 0x24E2 0x400>, + <&apps_smmu 0x2000 0x400>, + <&apps_smmu 0x2400 0x400>, + <&apps_smmu 0x2060 0x400>, + <&apps_smmu 0x2460 0x400>, + <&apps_smmu 0x2020 0x400>, + <&apps_smmu 0x2420 0x400>; + cam-smmu-label = "icp"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; + dma-coherent-hint-cached; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 261MB long */ + iova-region-name = "shared"; + iova-region-start = <0x500000>; + iova-region-len = <0x10500000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xdff00000 0x300000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x400>, + <&apps_smmu 0x24C0 0x400>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac40000 0x1000>, + <0xac42000 0x8000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x40000 0x42000 0x0BBF0000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "cpas_fast_ahb_clk_src"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CORE_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 100000000>, + <0 0 0 80000000 0 0 400000000 0 200000000>, + <0 0 0 80000000 0 0 400000000 0 300000000>, + <0 0 0 80000000 0 0 400000000 0 400000000>, + <0 0 0 80000000 0 0 400000000 0 400000000>, + <0 0 0 80000000 0 0 480000000 0 400000000>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", + "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", + "custom0", "custom1", "ipe0", "cam-cdm-intf0", + "ife-cdm0", "ife-cdm1", "ife-cdm2", "cpas-cdm0", + "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "tpg0", "tpg1"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-rt0-wr1"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <10>; + node-name = "level1-rt0-wr2"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <11>; + node-name = "level1-rt0-rd0"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <12>; + node-name = "level1-rt0-wr3"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <13>; + node-name = "level1-rt0-wr4"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <14>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <15>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr1: level1-nrt0-wr1 { + cell-index = <16>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <17>; + node-name = "level1-nrt0-rd2"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife2_ubwc_stats_wr: ife2-ubwc-stats-wr { + cell-index = <18>; + node-name = "ife2-ubwc-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <19>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_ubwc_stats_wr: ife1-ubwc-stats-wr { + cell-index = <20>; + node-name = "ife1-ubwc-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_linear_pdaf_wr: ife0-linear-pdaf-wr { + cell-index = <21>; + node-name = "ife0-linear-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_linear_pdaf_wr: ife1-linear-pdaf-wr { + cell-index = <22>; + node-name = "ife1-linear-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife2_linear_pdaf_wr: ife2-linear-pdaf-wr { + cell-index = <23>; + node-name = "ife2-linear-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <24>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_rdi_all_rd: ife0-rdi-all-rd { + cell-index = <25>; + node-name = "ife0-rdi-all-rd"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife1_rdi_all_rd: ife1-rdi-all-rd { + cell-index = <26>; + node-name = "ife1-rdi-all-rd"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife2_rdi_all_rd: ife2-rdi-all-rd { + cell-index = <27>; + node-name = "ife2-rdi-all-rd"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom0_rd: custom0-rd { + cell-index = <28>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom1_rd: custom1-rd { + cell-index = <29>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <30>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife4_rdi_all_wr: ife4-rdi-all-wr { + cell-index = <31>; + node-name = "ife4-rdi-all-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + custom1_wr: custom1-wr { + cell-index = <32>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <33>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <34>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + custom0_wr: custom0-wr { + cell-index = <35>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <36>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <37>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <38>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <39>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <40>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <41>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <42>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <43>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <44>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <45>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <46>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,cpas-cdm0 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm1_2"; + label = "cpas-cdm"; + reg = <0xac4d000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x4d000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife3", "ife4", "dualife"; + status = "ok"; + }; + + qcom,ife-cdm0 { + cell-index = <0>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacb4200 0x1000>; + reg-names = "ife-cdm0"; + reg-cam-base = <0xb4200>; + interrupts = ; + interrupt-names = "ife-cdm0"; + regulator-names = "camss","ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = "ife_0_ahb", + "ife_0_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife0"; + status = "ok"; + }; + + qcom,ife-cdm1 { + cell-index = <1>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacc3200 0x1000>; + reg-names = "ife-cdm1"; + reg-cam-base = <0xc3200>; + interrupts = ; + interrupt-names = "ife-cdm1"; + regulator-names = "camss","ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = "ife_1_ahb", + "ife_1_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife1"; + status = "ok"; + }; + + qcom,ife-cdm2 { + cell-index = <2>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacef200 0x1000>; + reg-names = "ife-cdm2"; + reg-cam-base = <0xef200>; + interrupts = ; + interrupt-names = "ife-cdm2"; + regulator-names = "camss","ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = "ife_2_ahb", + "ife_2_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_2_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_2_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife2"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + cell-index = <0>; + compatible = "qcom,csid580"; + reg-names = "csid"; + reg = <0xacb5200 0x1000>; + reg-cam-base = <0xb5200>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk", + "ife_0_areg", + "ife_0_ahb", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0 { + cell-index = <0>; + compatible = "qcom,vfe580"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb4000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xb4000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_ahb", + "ife_0_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 0 338000000 0 0>, + <0 0 475000000 0 0>, + <0 0 600000000 0 0>, + <0 0 720000000 0 0>, + <0 0 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = < 28 4 16 8 >; + status = "ok"; + }; + + cam_csid1: qcom,csid1 { + cell-index = <1>; + compatible = "qcom,csid580"; + reg-names = "csid"; + reg = <0xacc4200 0x1000>; + reg-cam-base = <0xc4200>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk", + "ife_1_areg", + "ife_1_ahb", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1 { + cell-index = <1>; + compatible = "qcom,vfe580"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacc3000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xc3000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_ahb", + "ife_1_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 0 338000000 0 0>, + <0 0 475000000 0 0>, + <0 0 600000000 0 0>, + <0 0 720000000 0 0>, + <0 0 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = < 29 5 17 9 >; + status = "ok"; + }; + + cam_csid2: qcom,csid2 { + cell-index = <2>; + compatible = "qcom,csid580"; + reg-names = "csid"; + reg = <0xacf0200 0x1000>; + reg-cam-base = <0xf0200>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk", + "ife_2_areg", + "ife_2_ahb", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_IFE_2_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_2_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>, + <400000000 0 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2 { + cell-index = <2>; + compatible = "qcom,vfe580"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacef000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xef000 0x42000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_ahb", + "ife_2_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_2_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_2_AREG_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <0 0 338000000 0 0>, + <0 0 475000000 0 0>, + <0 0 600000000 0 0>, + <0 0 720000000 0 0>, + <0 0 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = < 23 6 20 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0 { + cell-index = <3>; + compatible = "qcom,csid-lite580"; + reg-names = "csid-lite"; + reg = <0xacd9200 0x1000>; + reg-cam-base = <0xd9200>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 0>, + <400000000 0 0 0 0>, + <400000000 0 0 0 0>, + <400000000 0 0 0 0>, + <400000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0 { + cell-index = <3>; + compatible = "qcom,vfe-lite580"; + reg-names = "ife-lite"; + reg = <0xacd9000 0x2200>; + reg-cam-base = <0xd9000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 7 >; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1 { + cell-index = <4>; + compatible = "qcom,csid-lite580"; + reg-names = "csid-lite"; + reg = <0xacdb400 0x1000>; + reg-cam-base = <0xdb400>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 0>, + <400000000 0 0 0 0>, + <400000000 0 0 0 0>, + <400000000 0 0 0 0>, + <400000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1 { + cell-index = <4>; + compatible = "qcom,vfe-lite580"; + reg-names = "ife-lite"; + reg = <0xacdb200 0x2200>; + reg-cam-base = <0xdb200>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 21 >; + status = "ok"; + }; + + cam_csiphy_tpg0: qcom,tpg0@ac97000 { + cell-index = <0>; + compatible = "qcom,tpg102"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xac97000 0x100>, + <0xac40000 0x1000>; + reg-cam-base = <0x97000 0x40000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-rates = + <400000000 0 300000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg1: qcom,tpg1@ac98000 { + cell-index = <1>; + compatible = "qcom,tpg102"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xac98000 0x100>, + <0xac40000 0x1000>; + reg-cam-base = <0x98000 0x40000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-rates = + <400000000 0 300000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi1phytimer_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 600000000 0>, + <0 0 600000000 0>, + <0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac9a000 0x12000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x9a000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 450000000 0>, + <0 0 0 525000000 0>, + <0 0 0 700000000 0>, + <0 0 0 700000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac7a000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x7a000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_AREG_CLK>, + <&clock_camcc CAM_CC_BPS_AXI_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_580"; + reg-names = "jpege_hw","cam_camnoc"; + reg = <0xac53000 0x4000>, + <0x0ac42000 0x8000>; + reg-cam-base = <0x53000 0x42000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <25 26>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_580"; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg = <0xac57000 0x4000>, + <0x0ac42000 0x8000>; + reg-cam-base = <0x57000 0x42000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <24 27>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; +}; diff --git a/lito-camera-sensor-cdp.dtsi b/lito-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..3796cfa5 --- /dev/null +++ b/lito-camera-sensor-cdp.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&S8C>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1350000 0>; + rgltr-max-voltage = <1800000 2800000 1350000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 71 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VDIG1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + status="ok"; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&S8C>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1350000 0>; + rgltr-max-voltage = <1800000 2800000 1350000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 71 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VDIG1"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + status = "ok"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lito-camera-sensor-mtp.dtsi b/lito-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..3796cfa5 --- /dev/null +++ b/lito-camera-sensor-mtp.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&S8C>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1350000 0>; + rgltr-max-voltage = <1800000 2800000 1350000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 71 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VDIG1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + status="ok"; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&S8C>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1350000 0>; + rgltr-max-voltage = <1800000 2800000 1350000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 71 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VDIG1"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + status = "ok"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lito-camera-sensor-qrd.dtsi b/lito-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..0e16a57c --- /dev/null +++ b/lito-camera-sensor-qrd.dtsi @@ -0,0 +1,677 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + }; + + vreg_tof: regulator-dbb1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_tof"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + gpio = <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1000>; + enable-active-high; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&S8C>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1350000 0>; + rgltr-max-voltage = <1800000 2800000 1350000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 71 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VDIG1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + status="ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 25 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&S8C>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1350000 0>; + rgltr-max-voltage = <1800000 2800000 1350000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 71 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VDIG1"; + sensor-mode = <0>; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + status = "ok"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&L6P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 1800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 1800000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vdig-supply = <&L1P>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 25 0>, + <&tlmm 21 0>, + <&tlmm 51 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6", + "CAM_VANA6"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&BOB>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 4000000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 70 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5", + "CAM_VANA5"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L7P>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3600000 0>; + rgltr-max-voltage = <1800000 3600000 0>; + rgltr-load-current = <0 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&BOB>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 1056000 0>; + rgltr-max-voltage = <1800000 4000000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 29 0>, + <&tlmm 70 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5", + "CAM_VANA5"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lito-camera.dtsi b/lito-camera.dtsi new file mode 100644 index 00000000..49a54b50 --- /dev/null +++ b/lito-camera.dtsi @@ -0,0 +1,1623 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0x0ace0000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe0000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <880000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0xace2000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe2000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <880000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0xace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <880000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <880000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "cci_clk", + "cci_1_clk_src"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 28 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x900 0x5E0>, + <&apps_smmu 0x880 0x5E0>, + <&apps_smmu 0x820 0x5E0>, + <&apps_smmu 0x920 0x5E0>, + <&apps_smmu 0x8A0 0x5E0>, + <&apps_smmu 0x940 0x5E0>, + <&apps_smmu 0x8C0 0x5E0>, + <&apps_smmu 0xD00 0x5E0>, + <&apps_smmu 0xC80 0x5E0>, + <&apps_smmu 0xC20 0x5E0>, + <&apps_smmu 0xD20 0x5E0>, + <&apps_smmu 0xCA0 0x5E0>, + <&apps_smmu 0xD40 0x5E0>, + <&apps_smmu 0xCC0 0x5E0>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1280 0x20>, + <&apps_smmu 0x12A0 0x20>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1042 0x0>, + <&apps_smmu 0x11A0 0x0>, + <&apps_smmu 0x1220 0x0>, + <&apps_smmu 0x1300 0x20>, + <&apps_smmu 0x1320 0x20>, + <&apps_smmu 0x1180 0x0>, + <&apps_smmu 0x1200 0x0>, + <&apps_smmu 0x11E0 0x0>, + <&apps_smmu 0x1260 0x0>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xdff00000 0x300000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1000 0x0>; + cam-smmu-label = "cpas-cdm0"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_fd { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x12C0 0x20>, + <&apps_smmu 0x12E0 0x20>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "fd"; + fd_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x11C0 0x0>, + <&apps_smmu 0x1240 0x0>; + cam-smmu-label = "lrme"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "fd", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + cell-index = <0>; + compatible = "qcom,csid175_200"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <300000000 0 0 0 380000000 0 0>, + <384000000 0 0 0 510000000 0 0>, + <400000000 0 0 0 637000000 0 0>, + <400000000 0 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0 { + cell-index = <0>; + compatible = "qcom,vfe175_130"; + reg-names = "ife"; + reg = <0xacaf000 0x5200>; + reg-cam-base = <0xaf000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <760000000>; + status = "ok"; + }; + + cam_csid1: qcom,csid1 { + cell-index = <1>; + compatible = "qcom,csid175_200"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <300000000 0 0 0 380000000 0 0>, + <384000000 0 0 0 510000000 0 0>, + <400000000 0 0 0 637000000 0 0>, + <400000000 0 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1 { + cell-index = <1>; + compatible = "qcom,vfe175_130"; + reg-names = "ife"; + reg = <0xacb6000 0x5200>; + reg-cam-base = <0xb6000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <760000000>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0 { + cell-index = <2>; + compatible = "qcom,csid-lite175"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0>, + <384000000 0 0 0 400000000 0>, + <400000000 0 0 0 480000000 0>, + <400000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,vfe-lite0 { + cell-index = <2>; + compatible = "qcom,vfe-lite175"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,ipe1", + "qcom,bps"; + num-icp = <1>; + num-ipe = <2>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + + clock-rates = + <100000000 0 400000000 0>, + <200000000 0 480000000 0>, + <300000000 0 600000000 0>, + <400000000 0 600000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x1073 0x101CF>; + qos-val = <0x00000A0A>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 430000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + cam_ipe1: qcom,ipe1 { + cell-index = <1>; + compatible = "qcom,cam-ipe"; + reg = <0xac91000 0x3000>; + reg-names = "ipe1_top"; + reg-cam-base = <0x91000>; + regulator-names = "ipe1-vdd"; + ipe1-vdd-supply = <&ipe_1_gdsc>; + clock-names = + "ipe_1_ahb_clk", + "ipe_1_areg_clk", + "ipe_1_axi_clk", + "ipe_1_clk_src", + "ipe_1_clk"; + src-clock-name = "ipe_1_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_IPE_1_AHB_CLK>, + <&camcc CAM_CC_IPE_1_AREG_CLK>, + <&camcc CAM_CC_IPE_1_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&camcc CAM_CC_IPE_1_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 430000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-fd { + compatible = "qcom,cam-fd"; + compat-hw-name = "qcom,fd"; + num-fd = <1>; + status = "ok"; + }; + + cam_fd: qcom,fd { + cell-index = <0>; + compatible = "qcom,fd501"; + reg-names = "fd_core", "fd_wrapper"; + reg = <0xac5a000 0x1000>, + <0xac5b000 0x400>; + reg-cam-base = <0x5a000 0x5b000>; + interrupt-names = "fd"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "fd_core_clk_src", + "fd_core_clk", + "fd_core_uar_clk"; + clocks = + <&camcc CAM_CC_FD_CORE_CLK_SRC>, + <&camcc CAM_CC_FD_CORE_CLK>, + <&camcc CAM_CC_FD_CORE_UAR_CLK>; + src-clock-name = "fd_core_clk_src"; + clock-control-debugfs = "true"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + clock-rates = + <380000000 0 0>, + <384000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "lrme_clk_src", + "lrme_clk"; + clocks = <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-rates = <240000000 240000000>, + <300000000 300000000>, + <320000000 320000000>, + <400000000 400000000>, + <400000000 400000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; + + qcom,cam-cpas { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x6000>; + reg-cam-base = <0x40000 0x42000>; + cam_hw_fuse = , + ; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 0 80000000 0 150000000 0>, + <0 0 0 80000000 0 240000000 0>, + <0 0 0 80000000 0 320000000 0>, + <0 0 0 80000000 0 400000000 0>, + <0 0 0 80000000 0 400000000 0>, + <0 0 0 80000000 0 480000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "cci0", "cci1", + "csid0", "csid1", "csid2", + "ife0", "ife1", "ife2", + "ipe0", "ipe1", "cam-cdm-intf0", "cpas-cdm0", + "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "fd0", "lrmecpas0"; + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_wr_sum: level3-rt0-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_3"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_3_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_rt1_rd_wr_sum: level3-rt1-rd-wr-sum { + cell-index = <1>; + node-name = "level3-rt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_1"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt1_rd_sum: level3-nrt1-rd-sum { + cell-index = <3>; + node-name = "level3-nrt1-rd-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_icp"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_4_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_write0: level2-rt0-write0 { + cell-index = <4>; + node-name = "level2-rt0-write0"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt1_read0: level2-rt1-read0 { + cell-index = <5>; + node-name = "level2-rt1-read0"; + parent-node = <&level3_rt1_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt1_write0: level2-rt1-write0 { + cell-index = <6>; + node-name = "level2-rt1-write0"; + parent-node = <&level3_rt1_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_write0: level2-nrt0-write0 { + cell-index = <7>; + node-name = "level2-nrt0-write0"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_read0: level2-nrt0-read0 { + cell-index = <8>; + node-name = "level2-nrt0-read0"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_read0: level2-nrt1-read0 { + cell-index = <9>; + node-name = "level2-nrt1-read0"; + parent-node = <&level3_nrt1_rd_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_write0: level1-rt0-write0 { + cell-index = <10>; + node-name = "level1-rt0-write0"; + parent-node = <&level2_rt0_write0>; + traffic-merge-type = + ; + }; + + level1_rt1_write0: level1-rt1-write0 { + cell-index = <11>; + node-name = "level1-rt1-write0"; + parent-node = <&level2_rt1_write0>; + traffic-merge-type = + ; + }; + + level1_rt1_read0: level1-rt1-read0 { + cell-index = <12>; + node-name = "level1-rt1-read0"; + parent-node = <&level2_rt1_read0>; + traffic-merge-type = + ; + }; + + level1_rt1_write1: level1-rt1-write1 { + cell-index = <13>; + node-name = "level1-rt1-write1"; + parent-node = <&level2_rt1_write0>; + traffic-merge-type = + ; + }; + + level1_nrt0_write0: level1-nrt0-write0 { + cell-index = <14>; + node-name = "level1-nrt0-write0"; + parent-node = <&level2_nrt0_write0>; + traffic-merge-type = + ; + }; + + level1_nrt0_write1: level1-nrt0-write1 { + cell-index = <15>; + node-name = "level1-nrt0-write1"; + parent-node = <&level2_nrt0_write0>; + traffic-merge-type = + ; + }; + + level1_nrt0_read0: level1-nrt0-read0 { + cell-index = <16>; + node-name = "level1-nrt0-read0"; + parent-node = <&level2_nrt0_read0>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <17>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_read0>; + }; + + fd0_all_wr: fd0-all-wr { + cell-index = <18>; + node-name = "fd0-all-wr"; + client-name = "fd0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_write0>; + }; + + fd0_all_rd: fd0-all-rd { + cell-index = <19>; + node-name = "fd0-all-rd"; + client-name = "fd0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_read0>; + }; + + ife0_pixelall_wr: ife0-pixelall-wr { + cell-index = <20>; + node-name = "ife0-pixelall-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_write0>; + }; + + ife1_rdi_wr: ife1-rdi-wr { + cell-index = <21>; + node-name = "ife1-rdi-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife0_rdi_wr: ife0-rdi-wr { + cell-index = <22>; + node-name = "ife0-rdi-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife2_rdi_wr: ife2-rdi-wr { + cell-index = <23>; + node-name = "ife2-rdi-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife1_rdi_rd: ife1-rdi-rd { + cell-index = <24>; + node-name = "ife1-rdi-rd"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_read0>; + }; + + ife0_rdi_rd: ife0-rdi-rd { + cell-index = <25>; + node-name = "ife0-rdi-rd"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_read0>; + }; + + ife1_pixelall_wr: ife1-pixelall-wr { + cell-index = <26>; + node-name = "ife1-pixelall-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_write1>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <27>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_read0>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <28>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_read0>; + }; + + ipe1_all_rd: ipe1-all-rd { + cell-index = <29>; + node-name = "ipe1-all-rd"; + client-name = "ipe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_read0>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <30>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_read0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <31>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe0_ref_wr: ipe0-ref-wr { + cell-index = <32>; + node-name = "ipe0-ref-wr"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe1_ref_wr: ipe1-ref-wr { + cell-index = <33>; + node-name = "ipe1-ref-wr"; + client-name = "ipe1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <34>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe1_viddisp_wr: ipe1-viddisp-wr { + cell-index = <35>; + node-name = "ipe1-viddisp-wr"; + client-name = "ipe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_write1>; + }; + + ipe0_viddisp_wr: ipe0-viddisp-wr { + cell-index = <36>; + node-name = "ipe0-viddisp-wr"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_write1>; + }; + + jpeg0_all_wr: jpeg0-all-wr { + cell-index = <37>; + node-name = "jpeg0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_write0>; + }; + + jpeg0_all_rd: jpeg0-all-rd { + cell-index = <38>; + node-name = "jpeg0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_read0>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <39>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_read0>; + }; + }; + }; + }; +}; diff --git a/lito-v2-camera.dtsi b/lito-v2-camera.dtsi new file mode 100644 index 00000000..55d8789e --- /dev/null +++ b/lito-v2-camera.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* Override CSIPHY version */ +&cam_csiphy0 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; + +&cam_csiphy1 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; + +&cam_csiphy2 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; + +&cam_csiphy3 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; diff --git a/parrot-camera.dts b/parrot-camera.dts new file mode 100644 index 00000000..c1445452 --- /dev/null +++ b/parrot-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "parrot-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Parrot v1 SoC"; + compatible = "qcom,parrot"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/parrot-camera.dtsi b/parrot-camera.dtsi new file mode 100644 index 00000000..b323c750 --- /dev/null +++ b/parrot-camera.dtsi @@ -0,0 +1,1195 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio49","gpio50"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio49","gpio50"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio49","gpio50"; + function = "cci_i2c"; + }; + + config { + pins = "gpio49","gpio50"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio51","gpio52"; + function = "cci_i2c"; + }; + + config { + pins = "gpio51","gpio52"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio51","gpio52"; + function = "cci_i2c"; + }; + + config { + pins = "gpio51","gpio52"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio53","gpio54"; + function = "cci_i2c"; + }; + + config { + pins = "gpio53","gpio54"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio53","gpio54"; + function = "cci_i2c"; + }; + + config { + pins = "gpio53","gpio54"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio55","gpio56"; + function = "cci_i2c"; + }; + + config { + pins = "gpio55","gpio56"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio55","gpio56"; + function = "cci_i2c"; + }; + + config { + pins = "gpio55","gpio56"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + qcom,remote; + }; + }; +}; + +&soc { + + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + status = "ok"; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + force_cache_allocs; + need_shared_buffer_padding; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x8A0 0x420>, + <&apps_smmu 0x880 0x420>, + <&apps_smmu 0xCA0 0x420>, + <&apps_smmu 0xC80 0x420>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + cam-smmu-label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2020 0x0000>, + <&apps_smmu 0x2040 0x00A0>, + <&apps_smmu 0x2060 0x00A0>, + <&apps_smmu 0x20E0 0x00A0>, + <&apps_smmu 0x2100 0x0000>, + <&apps_smmu 0x20C0 0x00A0>; + cam-smmu-label = "icp"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xFC00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cre { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2120 0x000>, + <&apps_smmu 0x2140 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + cam-smmu-label = "cre"; + dma-coherent; + cre_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2000 0x0000>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + multiple-client-devices; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac13000 0x1000>, + <0xac19000 0x8000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + cam_hw_fuse = , + , + , + ; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "sys_tmr_clk", + "soc_ahb_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "core_ahb_clk", + "fast_ahb_clk_src", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "camnoc_axi_hf_clk", + "camnoc_axi_sf_clk"; + clocks = + <&camcc CAM_CC_SYS_TMR_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_HF_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_SF_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0>, + <0 0 80000000 0 0 100000000 150000000 0 0 0>, + <0 0 80000000 0 0 150000000 240000000 0 0 0>, + <0 0 80000000 0 0 200000000 300000000 0 0 0>, + <0 0 80000000 0 0 240000000 400000000 0 0 0>, + <0 0 80000000 0 0 240000000 400000000 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "camnoc_axi_clk_src"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &cnoc2 SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 133320>, <0 150000>, <0 150000>,<0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0", "cci1", + "csid0", "csid1", "csid2", "tfe0", "tfe1", "tfe2", "ipe0", + "cpas-cdm0", "cam-cdm-intf0", "bps0", "icp0", "tpg13", + "tpg14", "cre0"; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-tfe-bayer-status-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-tfe-rdi-raw-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <10>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <11>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr1: level1-nrt0-wr1 { + cell-index = <12>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <13>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + }; + + level0-nodes { + level-index = <0>; + tfe0_bayer_stats_wr: tfe0_bayer_stats_wr { + cell-index = <14>; + node-name = "tfe0-bayer-stats-wr"; + client-name = "tfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + tfe1_bayer_stats_wr: tfe1-ubwc-wr { + cell-index = <15>; + node-name = "tfe1-ubwc-wr"; + client-name = "tfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + tfe2_bayer_stats_wr: tfe2-ubwc-wr { + cell-index = <16>; + node-name = "tfe2-ubwc-wr"; + client-name = "tfe2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + tfe0_rdi_raw_wr: tfe0_rdi_raw_wr { + cell-index = <17>; + node-name = "tfe0-rdi-raw-wr"; + client-name = "tfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + tfe1_rdi_raw_wr: tfe1-rdi-pixel-raw-wr { + cell-index = <18>; + node-name = "tfe1-rdi-pixel-raw-wr"; + client-name = "tfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + tfe2_rdi_raw_wr: tfe2-rdi-pixel-raw-wr { + cell-index = <19>; + node-name = "tfe2-rdi-pixel-raw-wr"; + client-name = "tfe2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ope_all_wr: ipe0-all-wr { + cell-index = <20>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps_all_wr: bps0-all-wr { + cell-index = <21>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps_all_rd: bps0-all-rd { + cell-index = <22>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + ope_ref_rd: ipe0-ref-rd { + cell-index = <23>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + ope_in_rd: ipe0-in-rd { + cell-index = <24>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + cre_all_rd: cre-all-rd { + cell-index = <25>; + node-name = "cre-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt0_rd>; + }; + cre_all_wr: cre-all-wr { + cell-index = <26>; + node-name = "cre-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <27>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <28>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac24000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_1"; + label = "cpas-cdm"; + reg = <0xac24000 0x400>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x24000>; + interrupt-names = "cpas-cdm"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + nrt-device; + cdm-client-names = "tfe0", "tfe1", "tfe2", "tfe"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <18>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@ac62000 { + cell-index = <0>; + compatible = "qcom,csid640"; + reg-names = "csid0", "camnoc"; + reg = <0xac62000 0x1000>, + <0xac19000 0x8000>; + reg-cam-base = <0x62000 0x19000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "tfe0_ahb_clk", + "tfe0_csid_clk_src", + "tfe0_csid_clk", + "tfe0_cphy_rx_clk", + "tfe0_clk"; + clocks = + <&camcc CAM_CC_TFE_0_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_TFE_0_CSID_CLK>, + <&camcc CAM_CC_TFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_TFE_0_CLK>; + clock-rates = + <0 300000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe0_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@ac62000 { + cell-index = <0>; + compatible = "qcom,tfe640"; + reg-names = "tfe0"; + reg = <0xac62000 0xD000>; + reg-cam-base = <0x62000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "tfe0_ahb_clk", + "tfe0_clk_src", + "tfe0_clk"; + clocks = + <&camcc CAM_CC_TFE_0_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_0_CLK>; + clock-rates = + <0 350000000 0>, + <0 432000000 0>, + <0 548000000 0>, + <0 630000000 0>, + <0 630000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe0_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 4 8 >; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@ac71000 { + cell-index = <1>; + compatible = "qcom,csid640"; + reg-names = "csid1", "camnoc"; + reg = <0xac71000 0x1000>, + <0xac19000 0x8000>; + reg-cam-base = <0x71000 0x72800 0x19000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "tfe1_ahb_clk", + "tfe1_csid_clk_src", + "tfe1_csid_clk", + "tfe1_cphy_rx_clk", + "tfe1_clk"; + clocks = + <&camcc CAM_CC_TFE_1_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_TFE_1_CSID_CLK>, + <&camcc CAM_CC_TFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_TFE_1_CLK>; + clock-rates = + <0 300000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe1_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@ac71000 { + cell-index = <1>; + compatible = "qcom,tfe640"; + reg-names = "tfe1"; + reg = <0xac71000 0x5000>; + reg-cam-base = <0x71000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "tfe1_ahb_clk", + "tfe1_clk_src", + "tfe1_clk"; + clocks = + <&camcc CAM_CC_TFE_1_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_1_CLK>; + clock-rates = + <0 350000000 0>, + <0 432000000 0>, + <0 548000000 0>, + <0 630000000 0>, + <0 630000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe1_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 5 9 >; + status = "ok"; + }; + + cam_tfe_csid2: qcom,tfe_csid2@ac80000 { + cell-index = <2>; + compatible = "qcom,csid640"; + reg-names = "csid2", "camnoc"; + reg = <0xac80000 0x1000>, + <0xac19000 0x8000>; + reg-cam-base = <0x80000 0x81800 0x19000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "tfe2_ahb_clk", + "tfe2_csid_clk_src", + "tfe2_csid_clk", + "tfe2_cphy_rx_clk", + "tfe2_clk"; + clocks = + <&camcc CAM_CC_TFE_2_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_TFE_2_CSID_CLK>, + <&camcc CAM_CC_TFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_TFE_2_CLK>; + clock-rates = + <0 300000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>, + <0 400000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe2_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe2: qcom,tfe2@ac80000 { + cell-index = <2>; + compatible = "qcom,tfe640"; + reg-names = "tfe2"; + reg = <0xac80000 0x5000>; + reg-cam-base = <0x80000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "tfe2_ahb_clk", + "tfe2_clk_src", + "tfe2_clk"; + clocks = + <&camcc CAM_CC_TFE_2_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_TFE_2_CLK>; + clock-rates = + <0 350000000 0>, + <0 432000000 0>, + <0 548000000 0>, + <0 630000000 0>, + <0 630000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe2_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 6 10 >; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg0"; + reg = <0xacf6000 0x400>; + reg-cam-base = <0xf6000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg1"; + reg = <0xacf7000 0x400>; + reg-cam-base = <0xf7000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; + src-clock-name = "csi1phytimer_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v2"; + icp-version = <0x0200>; + reg = <0xac01000 0x400>, + <0xac01800 0x400>, + <0xac04000 0x1000>; + reg-names = "icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_clk_src", + "icp_clk"; + clocks = + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>, + <600000000 0>, + <600000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + cam_hw_pid = <11>; + status = "ok"; + }; + + qcom,cam-cre { + compatible = "qcom,cam-cre"; + compat-hw-name = "qcom,cre"; + num-cre = <1>; + status = "ok"; + }; + + cre: qcom,cre@acfa000 { + cell-index = <0>; + compatible = "qcom,cre"; + reg = <0xacfa000 0x200>, + <0xacfa400 0xB0>, + <0xacfa700 0x300>; + reg-names = + "cre_top", + "cre_bus_rd", + "cre_bus_wr"; + reg-cam-base = <0xFA000 0xFA400 0xFA700>; + interrupts = ; + interrupt-names = "cre"; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "cre_ahb_clk", + "cre_clk_src", + "cre_clk"; + clocks = + <&camcc CAM_CC_CRE_AHB_CLK>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK>; + clock-rates = + <0 30000000 0>, + <0 41000000 0>, + <0 46000000 0>, + <0 60000000 0>, + <0 70000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "cre_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <13 12>; + status = "ok"; + }; + + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x16000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "ope0_ahb_clk", + "ope0_areg_clk", + "ope0_clk", + "ope0_clk_src"; + clocks = + <&camcc CAM_CC_OPE_0_AHB_CLK>, + <&camcc CAM_CC_OPE_0_AREG_CLK>, + <&camcc CAM_CC_OPE_0_CLK>, + <&camcc CAM_CC_OPE_0_CLK_SRC>; + + clock-rates = + <0 100000000 0 300000000>, + <0 150000000 0 410000000>, + <0 200000000 0 460000000>, + <0 240000000 0 600000000>, + <0 240000000 0 700000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ope0_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <16 2>; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps680"; + reg = <0xac2c000 0x7800>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_camss_top_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_clk", + "bps_clk_src"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>; + + clock-rates = + <0 100000000 0 300000000>, + <0 150000000 0 410000000>, + <0 200000000 0 460000000>, + <0 240000000 0 600000000>, + <0 240000000 0 700000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <17 3>; + status = "ok"; + }; +}; diff --git a/pineapple-camera-sensor-cdp.dts b/pineapple-camera-sensor-cdp.dts new file mode 100644 index 00000000..b1e82178 --- /dev/null +++ b/pineapple-camera-sensor-cdp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "pineapple-camera-sensor-cdp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple CDP/RCM"; + compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,cdp", "qcom,rcm", "qcom,pineapple-rcm"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <1 0>, <21 0>; +}; diff --git a/pineapple-camera-sensor-cdp.dtsi b/pineapple-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..24fd3fc1 --- /dev/null +++ b/pineapple-camera-sensor-cdp.dtsi @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + actuator_triple_uw: qcom,actuator1 { + cell-index = <1>; + reg = <0x0E>; + compatible = "qcom,cam-i2c-actuator"; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + reg = <0x50>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + reg = <0x51>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + reg = <0x1A>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_front_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_front_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + reg = <0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c2 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + ois_i3c_wide: qcom,ois@72 { + cell-index = <8>; + reg = <0x72 0x00 0x10>; + compatible = "qcom,cam-i2c-ois"; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio" ,"cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + ois-src = <&ois_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_wide>; + actuator-src = <&actuator_i3c_triple_wide>; + led-flash-src = <&led_flash_aon_rear>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/pineapple-camera-sensor-mtp.dts b/pineapple-camera-sensor-mtp.dts new file mode 100644 index 00000000..aed550a0 --- /dev/null +++ b/pineapple-camera-sensor-mtp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "pineapple-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple MTP"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,mtp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <8 0>, <0x50008 0>; +}; diff --git a/pineapple-camera-sensor-mtp.dtsi b/pineapple-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..24fd3fc1 --- /dev/null +++ b/pineapple-camera-sensor-mtp.dtsi @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + actuator_triple_uw: qcom,actuator1 { + cell-index = <1>; + reg = <0x0E>; + compatible = "qcom,cam-i2c-actuator"; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + reg = <0x50>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + reg = <0x51>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + reg = <0x1A>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_front_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_front_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + reg = <0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c2 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + ois_i3c_wide: qcom,ois@72 { + cell-index = <8>; + reg = <0x72 0x00 0x10>; + compatible = "qcom,cam-i2c-ois"; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio" ,"cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + ois-src = <&ois_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_wide>; + actuator-src = <&actuator_i3c_triple_wide>; + led-flash-src = <&led_flash_aon_rear>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/pineapple-camera-sensor-qrd.dts b/pineapple-camera-sensor-qrd.dts new file mode 100644 index 00000000..20fb5daa --- /dev/null +++ b/pineapple-camera-sensor-qrd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "pineapple-camera-sensor-qrd.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple QRD"; + compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,qrd"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <11 0>, <0x1000B 0>, <0x5000B 0>; +}; diff --git a/pineapple-camera-sensor-qrd.dtsi b/pineapple-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..24fd3fc1 --- /dev/null +++ b/pineapple-camera-sensor-qrd.dtsi @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + actuator_triple_uw: qcom,actuator1 { + cell-index = <1>; + reg = <0x0E>; + compatible = "qcom,cam-i2c-actuator"; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + reg = <0x50>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + reg = <0x51>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + reg = <0x1A>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_front_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_front_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + reg = <0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c2 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + ois_i3c_wide: qcom,ois@72 { + cell-index = <8>; + reg = <0x72 0x00 0x10>; + compatible = "qcom,cam-i2c-ois"; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio" ,"cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + ois-src = <&ois_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_wide>; + actuator-src = <&actuator_i3c_triple_wide>; + led-flash-src = <&led_flash_aon_rear>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/pineapple-camera-v2.dts b/pineapple-camera-v2.dts new file mode 100644 index 00000000..83e99194 --- /dev/null +++ b/pineapple-camera-v2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "pineapple-camera-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x20000>, <577 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/pineapple-camera-v2.dtsi b/pineapple-camera-v2.dtsi new file mode 100644 index 00000000..9dcbb10c --- /dev/null +++ b/pineapple-camera-v2.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-camera.dtsi" + +&cam_ipe0 { + clock-rates = + <0 0 0 475000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; +}; \ No newline at end of file diff --git a/pineapple-camera.dts b/pineapple-camera.dts new file mode 100644 index 00000000..29878aca --- /dev/null +++ b/pineapple-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "pineapple-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <577 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/pineapple-camera.dtsi b/pineapple-camera.dtsi new file mode 100644 index 00000000..68d3e191 --- /dev/null +++ b/pineapple-camera.dtsi @@ -0,0 +1,3384 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci_i2c_sda3_active { + mux { + pins = "gpio12"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio12"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { + mux { + pins = "gpio12"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci_i2c_scl3_active { + mux { + pins = "gpio13"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio13"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { + mux { + pins = "gpio13"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda4_active: cci_i2c_sda4_active { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda4_suspend: cci_i2c_sda4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_active: cci_i2c_scl4_active { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl4_suspend: cci_i2c_scl4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_active: cci_i2c_sda5_active { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda5_suspend: cci_i2c_sda5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_active: cci_i2c_scl5_active { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl5_suspend: cci_i2c_scl5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_aon_mclk2"; + }; + + config { + pins = "gpio102"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_aon_mclk2"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_aon_mclk4"; + }; + + config { + pins = "gpio104"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_aon_mclk4"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio108"; + function = "cam_mclk"; + }; + + config { + pins = "gpio108"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio108"; + function = "cam_mclk"; + }; + + config { + pins = "gpio108"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_active: cam_sensor_mclk7_active { + /* MCLK7 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_suspend: cam_sensor_mclk7_suspend { + /* MCLK7 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst7: cam_sensor_active_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst7: cam_sensor_suspend_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_ponv_front_active: cam_sensor_ponv_front_active { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_front_suspend: cam_sensor_ponv_front_suspend { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_ponv_rear_active: cam_sensor_ponv_rear_active { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_rear_suspend: cam_sensor_ponv_rear_suspend { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0766>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xacea000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xea000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xacec000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18600 37900>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@acee000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xacee000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xee000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac15000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac16000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac17000 { + cell-index = <2>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac17000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x17000>; + interrupt-names = "CCI2"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_2_clk_src", + "cci_2_clk"; + clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_2_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>; + pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; + pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; + pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci2: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x20>; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0xf 0xffe00000>; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x0040>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x18C0 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1880 0x00>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0xf9500000 0xf 0x06a00000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xc0700000 */ + iova-region-start = <0x0 0xc0700000>; + /* Length: 0x38e00000 */ + iova-region-len = <0x0 0x38e00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0xc0200000 */ + iova-region-start = <0x0 0xc0200000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0xc0300000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0xc0200000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0xc0100000>; + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0xc0100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + + iova-mem-region-ipc-hwmutex { + iova-region-name = "ipc_hwmutex"; + iova-region-start = <0x0 0xc0101000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x2>; + phy-addr = <0x1f4b000>; + }; + + iova-mem-region-global_cntr { + iova-region-name = "global_cntr"; + iova-region-start = <0x0 0xc0102000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x4>; + phy-addr = <0xc220000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf9500000 */ + iova-region-start = <0x0 0xf9500000>; + /* Length: 0xf06a00000 */ + iova-region-len = <0xf 0x06a00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0xc0000000 */ + iova-region-start = <0x0 0xc0000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + multiple-client-devices; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + qti,smmu-proxy-cb-id = ; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; + reg = <0xac13000 0x1000>, + <0xac19000 0xac80>, + <0xbbf0000 0x1f00>, + <0xadd7000 0x5000>; + reg-cam-base = <0x13000 0x19000 0x0bbf0000 0xadd7000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_rt_clk_src", + "camnoc_axi_rt_clk", + "camnoc_axi_nrt_clk", + "cam_cc_drv_xo_clk", + "cam_cc_pll0", + "cam_cc_qdss_debug_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>, + <&camcc CAM_CC_PLL0>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_axi_rt_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", + "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = , + ; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <13 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "csiphy6","csiphy7", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "sfe0", "sfe1", "sfe2", "custom0", "custom1", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", + "cam-cdm-intf0", "bps0", "icp0", "cre0", + "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", + "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; + sys-cache-uids = <34 38>; + enable-smart-qos; + enable-cam-drv = <(CAM_DDR_DRV | CAM_CLK_DRV)>; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x9230>; + priority-lut-high-offset = <0x9234>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x9430>; + priority-lut-high-offset = <0x9434>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x9630>; + priority-lut-high-offset = <0x9634>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <11>; + node-name = "level1-rt4-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x9830>; + priority-lut-high-offset = <0x9834>; + }; + + level1_rt0_rd: level1-rt0-rd { + cell-index = <12>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt1_wr: level1-nrt1-wr { + cell-index = <14>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt3_rd: level1-nrt3-rd { + cell-index = <15>; + node-name = "level1-nrt3-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt1_rd: level1-nrt1-rd { + cell-index = <16>; + node-name = "level1-nrt1-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <17>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <18>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <19>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <20>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <21>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <22>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <23>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe0_all_wr: sfe0-all-wr { + cell-index = <24>; + node-name = "sfe0-all-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe1_all_wr: sfe1-all-wr { + cell-index = <25>; + node-name = "sfe1-all-wr"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe2_all_wr: sfe2-all-wr { + cell-index = <26>; + node-name = "sfe2-all-wr"; + client-name = "sfe2"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + custom0_wr: custom0-wr { + cell-index = <27>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_wr>; + }; + + custom1_wr: custom1-wr { + cell-index = <28>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_pdaf_linear_wr: ife0-pdaf-linear-wr { + cell-index = <29>; + node-name = "ife0-pdaf-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_linear_wr: ife1-pdaf-linear-wr { + cell-index = <30>; + node-name = "ife1-pdaf-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_linear_wr: ife2-pdaf-linear-wr { + cell-index = <31>; + node-name = "ife2-pdaf-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <32>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <33>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <34>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <35>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <36>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <37>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + sfe1_all_rd: sfe1-all-rd { + cell-index = <38>; + node-name = "sfe1-all-rd"; + client-name = "sfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + sfe2_all_rd: sfe2-all-rd { + cell-index = <39>; + node-name = "sfe2-all-rd"; + client-name = "sfe2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + custom0_all_rd: custom0-rd { + cell-index = <40>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd>; + }; + + custom1_rd: custom1-rd { + cell-index = <41>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <42>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <43>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <44>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <45>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <46>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + + jpeg_enc1_all_wr: jpeg-enc1-all-wr { + cell-index = <47>; + node-name = "jpeg-enc1-all-wr"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + jpeg_dma1_all_wr: jpeg-dma1-all-wr { + cell-index = <48>; + node-name = "jpeg-dma1-all-wr"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <49>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt3_rd>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <50>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt3_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <51>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <52>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + + jpeg_enc1_all_rd: jpeg1-enc1-all-rd { + cell-index = <53>; + node-name = "jpeg-enc1-rd"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + jpeg_dma1_all_rd: jpeg1-dma1-all-rd { + cell-index = <54>; + node-name = "jpeg-dma1-rd"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <55>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <56>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <57>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <58>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <59>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <60>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm4_all_rd: rt-cdm4-all-rd { + cell-index = <61>; + node-name = "rt-cdm4-all-rd"; + client-name = "rt-cdm4"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <62>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac25000 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac26000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac26000 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac27000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac27000 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x27000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2", "dualife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac28000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac28000 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x28000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm4@ac29000 { + cell-index = <4>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac29000 0x580>; + reg-names = "rt-cdm4"; + reg-cam-base = <0x29000>; + interrupt-names = "rt-cdm4"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife4"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <30>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe880"; + reg-names = "sfe0"; + reg = <0xac9e000 0x8000>; + reg-cam-base = <0x9e000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe0"; + interrupts = ; + regulator-names = "gdsc", "sfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe0-supply = <&cam_cc_sfe_0_gdsc>; + clock-names = + "sfe_0_fast_ahb", + "sfe_0_clk_src", + "sfe_0_clk", + "cam_cc_cpas_sfe_0_clk"; + clocks = + <&camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK>, + <&camcc CAM_CC_CPAS_SFE_0_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_0_clk_src"; + cam_hw_pid = <11 0>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe1: qcom,sfe1@aca6000 { + cell-index = <1>; + compatible = "qcom,sfe880"; + reg-names = "sfe1"; + reg = <0xaca6000 0x8000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe1"; + interrupts = ; + regulator-names = "gdsc", "sfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe1-supply = <&cam_cc_sfe_1_gdsc>; + clock-names = + "sfe_1_fast_ahb", + "sfe_1_clk_src", + "sfe_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clocks = + <&camcc CAM_CC_SFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_1_CLK_SRC>, + <&camcc CAM_CC_SFE_1_CLK>, + <&camcc CAM_CC_CPAS_SFE_1_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_1_clk_src"; + cam_hw_pid = <12 1>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe2: qcom,sfe2@acae000 { + cell-index = <2>; + compatible = "qcom,sfe880"; + reg-names = "sfe2"; + reg = <0xacae000 0x8000>; + reg-cam-base = <0xae000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe2"; + interrupts = ; + regulator-names = "gdsc", "sfe2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe2-supply = <&cam_cc_sfe_2_gdsc>; + clock-names = + "sfe_2_fast_ahb", + "sfe_2_clk_src", + "sfe_2_clk", + "cam_cc_cpas_sfe_2_clk"; + clocks = + <&camcc CAM_CC_SFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_SFE_2_CLK_SRC>, + <&camcc CAM_CC_SFE_2_CLK>, + <&camcc CAM_CC_CPAS_SFE_2_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_2_clk_src"; + cam_hw_pid = <13 2>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid880"; + reg-names = "csid", "csid_top"; + reg = <0xacb8000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb8000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe880"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac62000 0xf000>, + <0xac19000 0xac80>; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "gdsc", "ife0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clocks = + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_0_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 20 24 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acb9000 { + cell-index = <1>; + compatible = "qcom,csid880"; + reg-names = "csid", "csid_top"; + reg = <0xacba000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xba000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac71000 { + cell-index = <1>; + compatible = "qcom,vfe880"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac71000 0xf000>, + <0xac19000 0xac80>; + reg-cam-base = <0x71000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "gdsc", "ife1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clocks = + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_1_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 21 25 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acbb000 { + cell-index = <2>; + compatible = "qcom,csid880"; + reg-names = "csid", "csid_top"; + reg = <0xacbc000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xbc000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@ac80000 { + cell-index = <2>; + compatible = "qcom,vfe880"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac80000 0xf000>, + <0xac19000 0xac80>; + reg-cam-base = <0x80000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife2"; + interrupts = ; + regulator-names = "gdsc", "ife2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_fast_ahb", + "ife_2_clk_src", + "ife_2_clk", + "cam_cc_cpas_ife_2_clk"; + clocks = + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>; + clock-rates = + <0 466000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_2_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <18 22 26 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acca000 { + cell-index = <3>; + compatible = "qcom,csid-lite880"; + reg-names = "csid-lite"; + reg = <0xaccb000 0xa00>; + reg-cam-base = <0xcb000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acca000 { + cell-index = <3>; + compatible = "qcom,vfe-lite880"; + reg-names = "ife-lite"; + reg = <0xaccb000 0x2800>; + reg-cam-base = <0xcb000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@accf000 { + cell-index = <4>; + compatible = "qcom,csid-lite880"; + reg-names = "csid-lite"; + reg = <0xacd0000 0xa00>; + reg-cam-base = <0xd0000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@accf000 { + cell-index = <4>; + compatible = "qcom,vfe-lite880"; + reg-names = "ife-lite"; + reg = <0xacd0000 0x2800>; + reg-cam-base = <0xd0000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <28>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xacf7000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf7000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xacf8000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf8000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + cam_icp: qcom,icp@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0xac01000 0x1000>, + <0x0ac04000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x1000 0x4000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x808>; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CPAS_IPE_NPS_CLK>; + clock-rates = + <0 0 0 455000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 13 31>; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps680"; + reg = <0xac2c000 0xb000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_CPAS_BPS_CLK>; + clock-rates = + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 480000000 0 0>, + <0 0 785000000 0 0>, + <0 0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <6 30>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc"; + reg = <0xac2a000 0x1000>, + <0xac19000 0xac80>; + reg-cam-base = <0x2a000 0x19000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@ac2b000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg = <0xac2b000 0x1000>, + <0xac19000 0xac80>; + reg-cam-base = <0x2b000 0x19000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +}; diff --git a/scuba-camera-sensor-idp.dtsi b/scuba-camera-sensor-idp.dtsi new file mode 100644 index 00000000..fa24a485 --- /dev/null +++ b/scuba-camera-sensor-idp.dtsi @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm2250_flash0>; + torch-source = <&pm2250_torch0>; + switch-source = <&pm2250_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm2250_flash0>; + torch-source = <&pm2250_torch0>; + switch-source = <&pm2250_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi new file mode 100644 index 00000000..9843c2c4 --- /dev/null +++ b/scuba-camera.dtsi @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C52000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C53000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x53000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 22 0>, + <&tlmm 23 0>, + <&tlmm 29 0>, + <&tlmm 30 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x400 0x000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x000>, + <&apps_smmu 0x840 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cam-smmu-label = "ope", "ope-cdm0"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>; + cam-smmu-label = "cpas-cdm0"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x11000 0x13000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,cx-ipeak-gpu-limit = <921600000>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", + "lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1", + "svs_l1", "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "cci0", + "csid0", "csid1", "tfe0", + "tfe1", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_0"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-client-names = "tfe0", "tfe1"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_0"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <240000000 0 0 0 256000000 0>, + <384000000 0 0 0 460800000 0>, + <426400000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <4>; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <5>; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + cell-index = <1>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0xA00>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk_src", + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 0 200000000 0>, + <171428571 0 266600000 0>, + <240000000 0 465000000 0>, + <240000000 0 580000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + status = "ok"; + }; +}; diff --git a/shima-camera-sensor-idp.dtsi b/shima-camera-sensor-idp.dtsi new file mode 100644 index 00000000..9ea4a502 --- /dev/null +++ b/shima-camera-sensor-idp.dtsi @@ -0,0 +1,550 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_wide: qcom,actuator0 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_wide: qcom,eeprom0 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_vana1-supply = <&L5I>; + cam_vdig-supply = <&L1I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 2700000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3000000>; + rgltr-load-current = <5000 68000 74000 805000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom1 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear: qcom,eeprom4 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&BOB>; + cam_vdig-supply = <&S9B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3200000 1000000 0>; + rgltr-max-voltage = <1800000 3960000 1500000 0>; + rgltr-load-current = <15000 2000000 805000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* Rear (W) */ + qcom,cam-sensor0 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L5I>; + cam_vdig-supply = <&L1I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3960000>; + rgltr-load-current = <5000 68000 74000 805000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* Rear-aux (T) */ + qcom,cam-sensor1 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* Rear */ + qcom,cam-sensor4 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_rear>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&BOB>; + cam_vdig-supply = <&S9B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3200000 1000000 0>; + rgltr-max-voltage = <1800000 3960000 1500000 0>; + rgltr-load-current = <15000 2000000 805000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* TPG */ + qcom,cam-tpg0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* TPG */ + qcom,cam-tpg1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* TPG */ + qcom,cam-tpg2 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 17 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator2 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom2 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom3 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0>; + rgltr-max-voltage = <1800000 2900000 1150000 0>; + rgltr-load-current = <5000 35000 301000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* Rear-aux (UW) */ + qcom,cam-sensor2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + /* Front */ + qcom,cam-sensor3 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <5000 35000 301000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; diff --git a/shima-camera-sensor-qrd.dtsi b/shima-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..2be2ced6 --- /dev/null +++ b/shima-camera-sensor-qrd.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_wide: qcom,actuator0 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_wide: qcom,eeprom0 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 2700000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3000000>; + rgltr-load-current = <5000 68000 74000 805000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom1 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_v_custom1-supply = <&pm8008i_l5>; + cam_vdig-supply = <&pm8008i_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig","cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 1700000 1000000 0 3200000>; + rgltr-max-voltage = <1800000 3000000 1900000 1200000 0 3960000>; + rgltr-load-current = <5000 68000 74000 805000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 106 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator2 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2700000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_uw: qcom,eeprom2 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 2700000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom3 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0>; + rgltr-max-voltage = <1800000 2900000 1150000 0>; + rgltr-load-current = <5000 35000 301000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 16 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008j_l5>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2700000 950000 0 3200000>; + rgltr-max-voltage = <1800000 2900000 1150000 0 3960000>; + rgltr-load-current = <5000 35000 301000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + }; +}; diff --git a/shima-camera.dtsi b/shima-camera.dtsi new file mode 100644 index 00000000..b6d9f6e9 --- /dev/null +++ b/shima-camera.dtsi @@ -0,0 +1,1910 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy"; + reg = <0x0ac6a000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6a000>; + interrupts = ; + interrupt-names = "csiphy0"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy"; + reg = <0xac6c000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6c000>; + interrupts = ; + interrupt-names = "csiphy1"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy"; + reg = <0xac6e000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x6e000>; + interrupts = ; + interrupt-names = "csiphy2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy"; + reg = <0xac70000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x70000>; + interrupts = ; + interrupt-names = "csiphy3"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4 { + cell-index = <4>; + compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy"; + reg = <0xac72000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x72000>; + interrupts = ; + interrupt-names = "csiphy4"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5 { + cell-index = <5>; + compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy"; + reg = <0xac74000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x74000>; + interrupts = ; + interrupt-names = "csiphy5"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <266666667 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac4f000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4f000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 107 0>, + <&tlmm 108 0>, + <&tlmm 109 0>, + <&tlmm 110 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac50000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x50000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + gpios = <&tlmm 111 0>, + <&tlmm 112 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1000 0x440>, + <&apps_smmu 0x1040 0x440>, + <&apps_smmu 0x1400 0x440>, + <&apps_smmu 0x1440 0x440>; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent-hint-cached; + cam-smmu-label = "ife", "ife-cdm"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2840 0x400>, + <&apps_smmu 0x2C40 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent-hint-cached; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x28E2 0x400>, + <&apps_smmu 0x2CE2 0x400>, + <&apps_smmu 0x2800 0x400>, + <&apps_smmu 0x2C00 0x400>, + <&apps_smmu 0x2860 0x400>, + <&apps_smmu 0x2C60 0x400>, + <&apps_smmu 0x2820 0x400>, + <&apps_smmu 0x2C20 0x400>; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + dma-coherent-hint-cached; + iova-region-discard = <0xdff00000 0x300000>; + cam-smmu-label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x28C0 0x400>, + <&apps_smmu 0x2CC0 0x400>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent-hint-cached; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,cpas-cdm0 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm1_2"; + label = "cpas-cdm"; + reg = <0xac4d000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x4d000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife3", "ife4", "dualife"; + status = "ok"; + }; + + qcom,ife-cdm0 { + cell-index = <0>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacb4200 0x1000>; + reg-names = "ife-cdm0"; + reg-cam-base = <0xb4200>; + interrupts = ; + interrupt-names = "ife-cdm0"; + regulator-names = "camss","ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = "ife_0_ahb", + "ife_0_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife0"; + status = "ok"; + }; + + qcom,ife-cdm1 { + cell-index = <1>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacc3200 0x1000>; + reg-names = "ife-cdm1"; + reg-cam-base = <0xc3200>; + interrupts = ; + interrupt-names = "ife-cdm1"; + regulator-names = "camss","ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = "ife_1_ahb", + "ife_1_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife1"; + status = "ok"; + }; + + qcom,ife-cdm2 { + cell-index = <2>; + compatible = "qcom,cam-ife-cdm1_2"; + label = "ife-cdm"; + reg = <0xacef200 0x1000>; + reg-names = "ife-cdm2"; + reg-cam-base = <0xef200>; + interrupts = ; + interrupt-names = "ife-cdm2"; + regulator-names = "camss","ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = "ife_2_ahb", + "ife_2_areg", + "ife_clk", + "ife_axi_clk", + "cam_cc_cpas_ahb_clk"; + clocks = + <&camcc CAM_CC_IFE_2_AHB_CLK>, + <&camcc CAM_CC_IFE_2_AREG_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>, + <0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ife2"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + cell-index = <0>; + compatible = "qcom,csid580"; + reg-names = "csid"; + reg = <0xacb5200 0x1000>; + reg-cam-base = <0xb5200>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_0_areg", + "ife_0_ahb", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0 0 338000000 0 100000000 0 0>, + <400000000 0 0 0 475000000 0 200000000 0 0>, + <400000000 0 0 0 600000000 0 300000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0 { + cell-index = <0>; + compatible = "qcom,vfe580"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb4000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xb4000 0x42000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_ahb", + "ife_0_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 100000000 338000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 600000000 0 0>, + <0 400000000 720000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_0_areg"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1016 0x1026>; + cam_hw_pid = < 28 4 16 8 >; + status = "ok"; + }; + + cam_csid1: qcom,csid1 { + cell-index = <1>; + compatible = "qcom,csid580"; + reg-names = "csid"; + reg = <0xacc4200 0x1000>; + reg-cam-base = <0xc4200>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_1_areg", + "ife_1_ahb", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0 0 338000000 0 100000000 0 0>, + <400000000 0 0 0 475000000 0 200000000 0 0>, + <400000000 0 0 0 600000000 0 300000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1 { + cell-index = <1>; + compatible = "qcom,vfe580"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacc3000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xc3000 0x42000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_ahb", + "ife_1_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 100000000 338000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 600000000 0 0>, + <0 400000000 720000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_1_areg"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <720000000>; + ubwc-static-cfg = <0x1016 0x1026>; + cam_hw_pid = < 29 5 17 9 >; + status = "ok"; + }; + + cam_csid2: qcom,csid2 { + cell-index = <2>; + compatible = "qcom,csid580"; + reg-names = "csid"; + reg = <0xacf0200 0x1000>; + reg-cam-base = <0xf0200>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_2_areg", + "ife_2_ahb", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AREG_CLK>, + <&camcc CAM_CC_IFE_2_AHB_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <400000000 0 0 0 338000000 0 100000000 0 0>, + <400000000 0 0 0 475000000 0 200000000 0 0>, + <400000000 0 0 0 600000000 0 300000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>, + <400000000 0 0 0 720000000 0 400000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2 { + cell-index = <2>; + compatible = "qcom,vfe580"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacef000 0xd000>, + <0xac42000 0x8000>; + reg-cam-base = <0xef000 0x42000>; + interrupt-names = "ife2"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_ahb", + "ife_2_areg", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_AHB_CLK>, + <&camcc CAM_CC_IFE_2_AREG_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <0 100000000 338000000 0 0>, + <0 200000000 475000000 0 0>, + <0 300000000 600000000 0 0>, + <0 400000000 720000000 0 0>, + <0 400000000 720000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + scl-clk-names = "ife_2_areg"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1016 0x1026>; + cam_hw_pid = < 30 6 18 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0 { + cell-index = <3>; + compatible = "qcom,csid-lite580"; + reg-names = "csid-lite"; + reg = <0xacd9200 0x1000>; + reg-cam-base = <0xd9200>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0 { + cell-index = <3>; + compatible = "qcom,vfe-lite580"; + reg-names = "ife-lite"; + reg = <0xacd9000 0x2200>; + reg-cam-base = <0xd9000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 20 >; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1 { + cell-index = <4>; + compatible = "qcom,csid-lite580"; + reg-names = "csid-lite"; + reg = <0xacdb400 0x1000>; + reg-cam-base = <0xdb400>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_lite_ahb", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1 { + cell-index = <4>; + compatible = "qcom,vfe-lite580"; + reg-names = "ife-lite"; + reg = <0xacdb200 0x2200>; + reg-cam-base = <0xdb200>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_lite_ahb", + "ife_lite_axi", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <0 0 400000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>, + <0 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = < 19 >; + status = "ok"; + }; + + cam_csiphy_tpg0: qcom,tpg0@ac97000 { + cell-index = <0>; + compatible = "qcom,tpg102"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xac97000 0x1000>, + <0xac40000 0x1000>; + reg-cam-base = <0x97000 0x40000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-rates = + <400000000 0 300000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg1: qcom,tpg1@ac98000 { + cell-index = <1>; + compatible = "qcom,tpg102"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xac98000 0x1000>, + <0xac40000 0x1000>; + reg-cam-base = <0x98000 0x40000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-rates = + <400000000 0 300000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi1phytimer_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + + clock-rates = + <100000000 0 400000000 0>, + <200000000 0 480000000 0>, + <300000000 0 600000000 0>, + <400000000 0 600000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-ipe-fetch-cfg = <0x7073 0x707b>; + ubwc-ipe-write-cfg = <0x161cf 0x161ef>; + ubwc-bps-fetch-cfg = <0x7073 0x707b>; + ubwc-bps-write-cfg = <0x161cf 0x161ef>; + qos-val = <0x00000A0A>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac9a000 0x12000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x9a000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 450000000 0>, + <0 0 0 450000000 0>, + <0 0 0 450000000 0>, + <0 0 0 450000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac7a000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x7a000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac53000 0x4000>; + reg-cam-base = <0x53000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <25 26>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac57000 0x4000>; + reg-cam-base = <0x57000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <24 27>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + qcom,cam-cpas { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac40000 0x1000>, + <0xac42000 0x8000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x40000 0x42000 0x0BBF0000>; + cam_hw_fuse = , + ; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + /* + * GCC throttle rt/nrt clock is added as a workaround in shima. + * Normally, This clock should be turned on/off along with + * GCC HF/SF clock + */ + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "gcc_rt_throttle_clk", + "gcc_nrt_throttle_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&gcc GCC_TITAN_RT_THROTTLE_CORE_CLK>, + <&gcc GCC_TITAN_NRT_THROTTLE_CORE_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0 0 0 0>, + <0 0 0 0 0 80000000 0 0 300000000 0>, + <0 0 0 0 0 80000000 0 0 300000000 0>, + <0 0 0 0 0 80000000 0 0 342855555 0>, + <0 0 0 0 0 80000000 0 0 400000000 0>, + <0 0 0 0 0 80000000 0 0 400000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", + "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", + "ipe0", "cam-cdm-intf0","ife-cdm0", "ife-cdm1", + "ife-cdm2", "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", + "jpeg-enc0", "tpg0", "tpg1"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-rt0-wr1"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <10>; + node-name = "level1-rt0-rd0"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <11>; + node-name = "level1-rt0-wr2"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <12>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <13>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr1: level1-nrt0-wr1 { + cell-index = <14>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <15>; + node-name = "level1-nrt0-rd2"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife2_ubwc_stats_wr: ife2-ubwc-stats-wr { + cell-index = <16>; + node-name = "ife2-ubwc-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_ubwc_stats_wr: ife0-ubwc-stats-wr { + cell-index = <17>; + node-name = "ife0-ubwc-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_stats_wr: ife1-ubwc-stats-wr { + cell-index = <18>; + node-name = "ife1-ubwc-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_linear_pdaf_wr: ife0-linear-pdaf-wr { + cell-index = <19>; + node-name = "ife0-linear-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_linear_pdaf_wr: ife1-linear-pdaf-wr { + cell-index = <20>; + node-name = "ife1-linear-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_linear_pdaf_wr: ife2-linear-pdaf-wr { + cell-index = <21>; + node-name = "ife2-linear-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_rdi_all_rd: ife0-rdi-all-rd { + cell-index = <22>; + node-name = "ife0-rdi-all-rd"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife1_rdi_all_rd: ife1-rdi-all-rd { + cell-index = <23>; + node-name = "ife1-rdi-all-rd"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife2_rdi_all_rd: ife2-rdi-all-rd { + cell-index = <24>; + node-name = "ife2-rdi-all-rd"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <27>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <28>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife4_rdi_all_wr: ife4-rdi-all-wr { + cell-index = <29>; + node-name = "ife4-rdi-all-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <30>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <31>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <32>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <33>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <34>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <35>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <36>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr1>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <37>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <38>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <39>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <40>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; +}; diff --git a/waipio-camera-overlay-v2.dts b/waipio-camera-overlay-v2.dts new file mode 100644 index 00000000..616b8ce1 --- /dev/null +++ b/waipio-camera-overlay-v2.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +/ { + model = "Qualcomm Technologies, Inc. Waipio v2 SoC"; + compatible = "qcom,waipio", "qcom,waipiop"; + qcom,msm-id = <457 0x20000>, <482 0x20000>; + qcom,board-id = <8 0>, <0x10008 0>, <0x03010008 0x03>, <0x04010008 0x04>; + + fragment@0 { + target = <&cam_sfe0>; + __overlay__ { + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + }; + }; + + fragment@1 { + target = <&cam_sfe1>; + __overlay__ { + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + }; + }; + + fragment@2 { + target = <&cam_vfe0>; + __overlay__ { + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + }; + }; + + fragment@3 { + target = <&cam_vfe1>; + __overlay__ { + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + }; + }; + + fragment@4 { + target = <&cam_vfe2>; + __overlay__ { + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 727000000 0 0>, + <0 727000000 0 0>; + }; + }; + + fragment@5 { + target = <&cam_csiphy0>; + __overlay__ { + rgltr-enable-sync = <0>; + }; + }; + + fragment@6 { + target = <&cam_csiphy1>; + __overlay__ { + rgltr-enable-sync = <0>; + }; + }; + + fragment@7 { + target = <&cam_csiphy2>; + __overlay__ { + rgltr-enable-sync = <0>; + }; + }; + + fragment@8 { + target = <&cam_csiphy3>; + __overlay__ { + rgltr-enable-sync = <0>; + }; + }; + + fragment@9 { + target = <&cam_csiphy4>; + __overlay__ { + rgltr-enable-sync = <0>; + }; + }; + + fragment@10 { + target = <&cam_csiphy5>; + __overlay__ { + rgltr-enable-sync = <0>; + }; + }; +}; diff --git a/waipio-camera-sensor-cdp.dts b/waipio-camera-sensor-cdp.dts new file mode 100644 index 00000000..8aec26f7 --- /dev/null +++ b/waipio-camera-sensor-cdp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "waipio-camera-sensor-cdp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Waipio CDP"; + compatible = "qcom,waipio", "qcom,waipiop"; + qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>; + qcom,board-id = <1 0>, <0x10001 0>; +}; \ No newline at end of file diff --git a/waipio-camera-sensor-cdp.dtsi b/waipio-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..aabc2d98 --- /dev/null +++ b/waipio-camera-sensor-cdp.dtsi @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_ois: qcom,actuator2 { + cell-index = <9>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + cam_v_custom2-supply = <&L6I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000 2800000 0>; + rgltr-max-voltage = <3000000 2896000 0>; + rgltr-load-current = <103000 90000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom7: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1704000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1896000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <20000 90000 550000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140400 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom9 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <155000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <20000 90000 550000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140400 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom7>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1704000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1896000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_triple_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_vana", "cam_v_custom1", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1050000 2900000 1800000 0>; + rgltr-max-voltage = <1800000 1200000 3000000 1896000 0>; + rgltr-load-current = <155000 872000 96000 88000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3000000>; + rgltr-load-current = <10000 139300 90100 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <20000 90000 550000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + regulator-names = "cam_vio", "cam_vana","cam_clk", "cam_vdig"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <10000 14720 0 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 3000000 0 3960000>; + rgltr-load-current = <10000 139300 90100 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <20000 90000 550000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_clk", "cam_vdig", + "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <10000 14720 0 30000 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/waipio-camera-sensor-mtp.dts b/waipio-camera-sensor-mtp.dts new file mode 100644 index 00000000..33d5d897 --- /dev/null +++ b/waipio-camera-sensor-mtp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "waipio-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Waipio MTP"; + compatible = "qcom,waipio", "qcom,waipiop"; + qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>; + qcom,board-id = <8 0>, <0x10008 0>, <0x02010008 0>, <0x03010008 0x03>, <0x04010008 0x04>; +}; \ No newline at end of file diff --git a/waipio-camera-sensor-mtp.dtsi b/waipio-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..e5959843 --- /dev/null +++ b/waipio-camera-sensor-mtp.dtsi @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_ois: qcom,actuator2 { + cell-index = <9>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + ois0: qcom,ois0 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&L7I>; + cam_v_custom2-supply = <&L6I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vaf", "cam_v_custom2", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000 2800000 0>; + rgltr-max-voltage = <3000000 2896000 0>; + rgltr-load-current = <103000 90000 0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom7: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1704000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1896000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <20000 90000 550000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140400 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom8: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + csiphy-sd-index = <0>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1100000 0 2904000 1800000 2800000>; + rgltr-max-voltage = <1800000 1200000 0 2904000 1896000 3000000>; + rgltr-load-current = <11000 415200 0 40600 20400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_ois: qcom,eeprom9 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <155000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <20000 90000 550000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140400 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom7>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1000000 0 2800000 1704000>; + rgltr-max-voltage = <1800000 1200000 0 2800000 1896000>; + rgltr-load-current = <155000 872000 0 52000 88000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom8>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1100000 0 2904000 1800000>; + rgltr-max-voltage = <1800000 1200000 0 2904000 1896000>; + rgltr-load-current = <11000 415200 0 40600 20400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_ois>; + actuator-src = <&actuator_triple_ois>; + ois-src = <&ois0>; + led-flash-src = <&led_flash_triple_rear>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&L1J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_vana", "cam_v_custom1", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1050000 2900000 1800000 0>; + rgltr-max-voltage = <1800000 1200000 3000000 1896000 0>; + rgltr-load-current = <155000 872000 96000 88000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3000000>; + rgltr-load-current = <10000 139300 90100 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <20000 90000 550000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + regulator-names = "cam_vio", "cam_vana","cam_clk", "cam_vdig"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <10000 14720 0 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 3000000 0 3960000>; + rgltr-load-current = <10000 139300 90100 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <20000 90000 550000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_clk", "cam_vdig", + "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <10000 14720 0 30000 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/waipio-camera-sensor-qrd.dts b/waipio-camera-sensor-qrd.dts new file mode 100644 index 00000000..4c78dd88 --- /dev/null +++ b/waipio-camera-sensor-qrd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "waipio-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Waipio QRD"; + compatible = "qcom,waipio", "qcom,waipiop"; + qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>; + qcom,board-id = <0x1000b 0>, <0x2000b 0>, <0x1001f 0>; +}; diff --git a/waipio-camera-sensor-qrd.dtsi b/waipio-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..3f6ce17d --- /dev/null +++ b/waipio-camera-sensor-qrd.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <20000 90000 550000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140400 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3J>; + cam_vdig-supply = <&S12B>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6J>; + cam_v_custom1-supply = <&L7J>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1350000 0 2800000 3304000>; + rgltr-load-current = <155000 680000 0 50000 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <20000 90000 550000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L4I>; + cam_vdig-supply = <&L2I>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 3000000 0 3960000>; + rgltr-load-current = <10000 52000 140400 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L7I>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 0 2960000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3000000>; + rgltr-load-current = <10000 139300 90100 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <20000 90000 550000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + regulator-names = "cam_vio", "cam_vana","cam_clk", "cam_vdig"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <10000 14720 0 30000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L3I>; + cam_v_custom1-supply = <&L4J>; + cam_vdig-supply = <&L1J>; + cam_vaf-supply = <&L7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1", + "cam_vdig", "cam_vaf", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1800000 1104000 2704000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 3000000 0 3960000>; + rgltr-load-current = <10000 139300 90100 872000 103000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&L3J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <128000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 106 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET4"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L6I>; + cam_vdig-supply = <&L2I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <20000 90000 550000 0 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&L3J>; + cam_vana-supply = <&L5J>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vdig-supply = <&L2J>; + cam_bob-supply = <&BOB>; + regulator-names = "cam_vio", "cam_vana", "cam_clk", "cam_vdig", + "cam_bob"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <10000 14720 0 30000 7070000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 104 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET6"; + cci-master = ; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/waipio-camera.dts b/waipio-camera.dts new file mode 100644 index 00000000..18f3a7fb --- /dev/null +++ b/waipio-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "waipio-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Waipio v1 SoC"; + compatible = "qcom,waipio", "qcom,waipiop"; + qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>, <552 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/waipio-camera.dtsi b/waipio-camera.dtsi new file mode 100644 index 00000000..2208b04a --- /dev/null +++ b/waipio-camera.dtsi @@ -0,0 +1,2698 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio110","gpio111"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio110","gpio111"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio110","gpio111"; + function = "cci_i2c"; + }; + + config { + pins = "gpio110","gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio112","gpio113"; + function = "cci_i2c"; + }; + + config { + pins = "gpio112","gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112","gpio113"; + function = "cci_i2c"; + }; + + config { + pins = "gpio112","gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio114","gpio115"; + function = "cci_i2c"; + }; + + config { + pins = "gpio114","gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114","gpio115"; + function = "cci_i2c"; + }; + + config { + pins = "gpio114","gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "cci_i2c"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "cci_i2c"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + qcom,remote; + }; + + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_mclk"; + }; + + config { + pins = "gpio104"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_mclk"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 6 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + /* RESET REAR */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + /* RESET REAR */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + /* RESET 2 */ + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + /* RESET 2 */ + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 3 */ + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 3 */ + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 4 */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 4 */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + /* RESET 5 */ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + /* RESET 5 */ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + /* RESET 6 */ + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + /* RESET 6 */ + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; + +&soc { + + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = < 0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xacea000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xea000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xacec000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY4_CLK>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@acee000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xacee000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xee000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-enable-sync = <1>; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 59400 147000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY5_CLK>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac15000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupt-names = "cci0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci0_active>; + pinctrl-1 = <&cci0_suspend>; + pinctrl-2 = <&cci1_active>; + pinctrl-3 = <&cci1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac16000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupt-names = "cci1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + pinctrl-2 = <&cci3_active>; + pinctrl-3 = <&cci3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + force_cache_allocs; + need_shared_buffer_padding; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x460>, + <&apps_smmu 0x820 0x460>, + <&apps_smmu 0xC00 0x460>, + <&apps_smmu 0xC20 0x460>, + <&apps_smmu 0x840 0x460>, + <&apps_smmu 0x860 0x460>, + <&apps_smmu 0xC40 0x460>, + <&apps_smmu 0xC60 0x460>; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20E0 0x400>, + <&apps_smmu 0x24E0 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2020 0x420>, + <&apps_smmu 0x2000 0x420>, + <&apps_smmu 0x2420 0x420>, + <&apps_smmu 0x2400 0x420>, + <&apps_smmu 0x2040 0x420>, + <&apps_smmu 0x2060 0x420>, + <&apps_smmu 0x2440 0x420>, + <&apps_smmu 0x2460 0x420>, + <&apps_smmu 0x2100 0x420>, + <&apps_smmu 0x2500 0x420>, + <&apps_smmu 0x2080 0x400>, + <&apps_smmu 0x2480 0x400>, + <&apps_smmu 0x2120 0x420>, + <&apps_smmu 0x2520 0x420>; + cam-smmu-label = "icp"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is ~250MB long */ + iova-region-name = "shared"; + iova-region-start = <0x800000>; + iova-region-len = <0xFC00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 7MB long */ + iova-region-name = "fw_uncached"; + iova-region-start = <0x10400000>; + iova-region-len = <0x700000>; + iova-region-id = <0x6>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x0400>, + <&apps_smmu 0x24C0 0x0400>, + <&apps_smmu 0x20A0 0x0400>, + <&apps_smmu 0x24A0 0x0400>; + cam-smmu-label = "cpas-cdm", "rt-cdm"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent; + multiple-client-devices; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac13000 0x1000>, + <0xac19000 0x9000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CORE_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 100000000 0 300000000 0>, + <0 0 0 80000000 0 0 200000000 0 400000000 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_axi_clk_src"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "csid0", "csid1", "csid2", "csid3", "csid4", + "csid5", "csid6", "csid7", "ife0", "ife1", "ife2", "ife3", "ife4", + "ife5", "ife6", "ife7", "sfe0", "sfe1", "custom0", "custom1", + "ipe0", "cpas-cdm0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "cam-cdm-intf0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "tpg13", + "tpg14", "tpg15"; + sys-cache-names = "small-1", "small-2"; + sys-cache-uids = <34 38>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-ife-ubwc-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-ife-rdi-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <10>; + node-name = "level1-ife-pdaf"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <11>; + node-name = "level1-ife01-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <12>; + node-name = "level1-ife2-linear-stats"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr5: level1-rt0-wr5 { + cell-index = <13>; + node-name = "level1-ifelite"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <14>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <15>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <16>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <17>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <18>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <19>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <20>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <21>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <22>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <23>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + sfe0_rdi_stats_nrdi_wr: sfe0-rdi-stats-nrdi-wr { + cell-index = <24>; + node-name = "sfe0-rdi-stats-nrdi-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + sfe1_rdi_stats_nrdi_wr: sfe1-rdi-stats-nrdi-wr { + cell-index = <25>; + node-name = "sfe1-rdi-stats-nrdi-wr"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + custom0_wr: custom0-wr { + cell-index = <26>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <27>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_pdaf_wr: ife1-pdaf-wr { + cell-index = <28>; + node-name = "ife1-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife2_pdaf_wr: ife2-pdaf-wr { + cell-index = <29>; + node-name = "ife2-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_linear_stats_wr: ife0-linear-stats-wr { + cell-index = <30>; + node-name = "ife0-linear-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife1_linear_stats_wr: ife1-linear-stats-wr { + cell-index = <31>; + node-name = "ife1-linear-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife2_linear_stats_wr: ife2-linear-stats-wr { + cell-index = <32>; + node-name = "ife2-linear-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + custom1_wr: custom1-wr { + cell-index = <33>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife7_rdi_stats_pixel_raw_wr: ife7-rdi-stats-pixel-raw-wr { + cell-index = <34>; + node-name = "ife7-rdi-stats-pixel-raw-wr"; + client-name = "ife7"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife6_rdi_stats_pixel_raw_wr: ife6-rdi-stats-pixel-raw-wr { + cell-index = <35>; + node-name = "ife6-rdi-stats-pixel-raw-wr"; + client-name = "ife6"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife5_rdi_stats_pixel_raw_wr: ife5-rdi-stats-pixel-raw-wr { + cell-index = <36>; + node-name = "ife5-rdi-stats-pixel-raw-wr"; + client-name = "ife5"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <37>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <38>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr5>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <39>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + sfe1_all_rd: sfe1-all-rd { + cell-index = <40>; + node-name = "sfe1-all-rd"; + client-name = "sfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom0_rd: custom0-rd { + cell-index = <41>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom1_rd: custom1-rd { + cell-index = <42>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <43>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <44>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <45>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <46>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <47>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <48>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <49>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <50>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <51>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <52>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <53>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <54>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <55>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <56>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac24000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_1"; + label = "cpas-cdm"; + reg = <0xac24000 0x400>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x24000>; + interrupt-names = "cpas-cdm"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + nrt-device; + cdm-client-names = "ife3", "ife4", "ife5", "ife6", "ife7"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac25000 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac26000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac26000 0x400>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac27000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac27000 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x27000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2", "dualife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe680"; + reg-names = "sfe0"; + reg = <0xac9e000 0x8000>; + reg-cam-base = <0x9e000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe"; + interrupts = ; + regulator-names = "gdsc", "sfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe0-supply = <&cam_cc_sfe_0_gdsc>; + clock-names = + "sfe_0_fast_ahb", + "sfe_0_clk_src", + "sfe_0_clk", + "cam_cc_cpas_sfe_0_clk"; + clocks = + <&clock_camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_CLK>, + <&clock_camcc CAM_CC_CPAS_SFE_0_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_0_clk_src"; + cam_hw_pid = <11 24>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe1: qcom,sfe1@aca6000 { + cell-index = <1>; + compatible = "qcom,sfe680"; + reg-names = "sfe1"; + reg = <0xaca6000 0x8000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe"; + interrupts = ; + regulator-names = "gdsc", "sfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe1-supply = <&cam_cc_sfe_1_gdsc>; + clock-names = + "sfe_1_fast_ahb", + "sfe_1_clk_src", + "sfe_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clocks = + <&clock_camcc CAM_CC_SFE_1_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_1_CLK>, + <&clock_camcc CAM_CC_CPAS_SFE_1_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_1_clk_src"; + cam_hw_pid = <12 25>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top"; + reg = <0xacb7000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb7000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac62000 0xf000>, + <0xac19000 0x9000>; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_0_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 28 20 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acb9000 { + cell-index = <1>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top"; + reg = <0xacb9000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb9000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac71000 { + cell-index = <1>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac71000 0xf000>, + <0xac19000 0x9000>; + reg-cam-base = <0x71000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_1_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 29 21 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acbb000 { + cell-index = <2>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top"; + reg = <0xacbb000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xbb000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@ac80000 { + cell-index = <2>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac80000 0xf000>, + <0xac19000 0x9000>; + reg-cam-base = <0x80000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_2_fast_ahb", + "ife_2_clk_src", + "ife_2_clk", + "cam_cc_cpas_ife_2_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_2_CLK>; + clock-rates = + <0 432000000 0 0>, + <0 594000000 0 0>, + <0 675000000 0 0>, + <0 785000000 0 0>, + <0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_2_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <18 30 22 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acc6000 { + cell-index = <3>; + compatible = "qcom,csid-lite680"; + reg-names = "csid-lite"; + reg = <0xacc6000 0xa00>; + reg-cam-base = <0xc6000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acc6000 { + cell-index = <3>; + compatible = "qcom,vfe-lite680"; + reg-names = "ife-lite"; + reg = <0xacc6000 0x2800>; + reg-cam-base = <0xc6000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <0>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@acca000 { + cell-index = <4>; + compatible = "qcom,csid-lite680"; + reg-names = "csid-lite"; + reg = <0xacca000 0xa00>; + reg-cam-base = <0xca000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@acca000 { + cell-index = <4>; + compatible = "qcom,vfe-lite680"; + reg-names = "ife-lite"; + reg = <0xacca000 0x2800>; + reg-cam-base = <0xca000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <1>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xacf7000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf7000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg103"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xacf8000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf8000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v2"; + icp-version = <0x0200>; + reg = <0xac01000 0x400>, + <0xac01800 0x400>, + <0x0ac04000 0x1000>; + reg-names = "icp_csr", "icp_cirq", "icp_wd0"; + reg-cam-base = <0x1000 0x1800 0x4000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>, + <&clock_camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x00000A0A>; + cam_hw_pid = <9>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x16000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clocks = + <&clock_camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_CLK>, + <&clock_camcc CAM_CC_CPAS_IPE_NPS_CLK>; + + clock-rates = + <0 0 0 364000000 0 0 0>, + <0 0 0 500000000 0 0 0>, + <0 0 0 600000000 0 0 0>, + <0 0 0 700000000 0 0 0>, + <0 0 0 700000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <22 23 30>; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps680"; + reg = <0xac2c000 0x7800>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clocks = + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>, + <&clock_camcc CAM_CC_CPAS_BPS_CLK>; + + clock-rates = + <0 0 200000000 0 0>, + <0 0 400000000 0 0>, + <0 0 480000000 0 0>, + <0 0 600000000 0 0>, + <0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <10 16>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_680"; + reg-names = "jpege_hw", "cam_camnoc"; + reg = <0xac2a000 0x1000>, + <0x0ac19000 0x9000>; + reg-cam-base = <0x2a000 0x19000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <12 14>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac2b000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_680"; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg = <0xac2b000 0x1000>, + <0x0ac19000 0x9000>; + reg-cam-base = <0x2b000 0x19000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <13 15>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; +}; diff --git a/yupik-camera.dtsi b/yupik-camera.dtsi new file mode 100644 index 00000000..9208b732 --- /dev/null +++ b/yupik-camera.dtsi @@ -0,0 +1,1651 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x0ace0000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe0000>; + interrupts = ; + interrupt-names = "csiphy0"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xace2000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe2000>; + interrupts = ; + interrupt-names = "csiphy1"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = ; + interrupt-names = "csiphy2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupts = ; + interrupt-names = "csiphy3"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4 { + cell-index = <4>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupts = ; + interrupt-names = "csiphy4"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L10C>; + regulator-names = "gdscr", "refgen", "csi-vdd-1p2", + "csi-vdd-0p9"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 1200000 880000>; + rgltr-max-voltage = <0 0 1260000 1050000>; + rgltr-load-current = <0 0 54000 96400>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs"; + clock-rates = + <300000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 69 0>, + <&tlmm 70 0>, + <&tlmm 71 0>, + <&tlmm 72 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + gpios = <&tlmm 73 0>, + <&tlmm 74 0>, + <&tlmm 75 0>, + <&tlmm 76 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x4E0>, + <&apps_smmu 0x820 0x4E0>, + <&apps_smmu 0x840 0x4E0>, + <&apps_smmu 0x860 0x4E0>, + <&apps_smmu 0x880 0x4E0>, + <&apps_smmu 0x8A0 0x4E0>, + <&apps_smmu 0x8C0 0x4E0>, + <&apps_smmu 0x8E0 0x4E0>, + <&apps_smmu 0xC00 0x4E0>, + <&apps_smmu 0xC20 0x4E0>, + <&apps_smmu 0xC40 0x4E0>, + <&apps_smmu 0xC60 0x4E0>, + <&apps_smmu 0xC80 0x4E0>, + <&apps_smmu 0xCA0 0x4E0>, + <&apps_smmu 0xCC0 0x4E0>, + <&apps_smmu 0xCE0 0x4E0>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + cam-smmu-label = "ife"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x20>, + <&apps_smmu 0x20E0 0x20>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2000 0x20>, + <&apps_smmu 0x2020 0x20>, + <&apps_smmu 0x2062 0x0>, + <&apps_smmu 0x2080 0x20>, + <&apps_smmu 0x20A0 0x20>, + <&apps_smmu 0x2140 0x0>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + dma-coherent-hint-cached; + iova-region-discard = <0xdff00000 0x300000>; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.7 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xdff00000 0x300000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2040 0x0>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2100 0x20>, + <&apps_smmu 0x2120 0x20>; + cam-smmu-label = "lrme"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x100000>; + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife0", "ife1", "ife2", + "ife3", "ife4", "dualife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0 { + cell-index = <0>; + compatible = "qcom,csid165_204"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <300000000 0 0 380000000 0 0>, + <400000000 0 0 510000000 0 0>, + <400000000 0 0 637000000 0 0>, + <400000000 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0 { + cell-index = <0>; + compatible = "qcom,vfe165_160"; + reg-names = "ife"; + reg = <0xacaf000 0x5200>; + reg-cam-base = <0xaf000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <760000000>; + cam_hw_pid = <24 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1 { + cell-index = <1>; + compatible = "qcom,csid165_204"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <300000000 0 0 380000000 0 0>, + <400000000 0 0 510000000 0 0>, + <400000000 0 0 637000000 0 0>, + <400000000 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1 { + cell-index = <1>; + compatible = "qcom,vfe165_160"; + reg-names = "ife"; + reg = <0xacb6000 0x5200>; + reg-cam-base = <0xb6000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <760000000>; + cam_hw_pid = <25 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2 { + cell-index = <2>; + compatible = "qcom,csid165_204"; + reg-names = "csid"; + reg = <0x0acc1000 0x1000>; + reg-cam-base = <0xc1000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <300000000 0 0 380000000 0 0>, + <400000000 0 0 510000000 0 0>, + <400000000 0 0 637000000 0 0>, + <400000000 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,vfe2 { + cell-index = <2>; + compatible = "qcom,vfe165_160"; + reg-names = "ife"; + reg = <0x0acbd000 0x5200>; + reg-cam-base = <0xbd000>; + interrupt-names = "ife2"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <760000000>; + cam_hw_pid = <3 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0 { + cell-index = <3>; + compatible = "qcom,csid-lite165"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_0_CLK>; + clock-rates = + <300000000 0 0 320000000 0>, + <400000000 0 0 400000000 0>, + <400000000 0 0 480000000 0>, + <400000000 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,vfe-lite0 { + cell-index = <3>; + compatible = "qcom,vfe-lite165"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x5000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_0_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1 { + cell-index = <4>; + compatible = "qcom,csid-lite165"; + reg-names = "csid-lite"; + reg = <0x0accf000 0x1000>; + reg-cam-base = <0xcf000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_1_CLK>; + clock-rates = + <300000000 0 0 320000000 0>, + <400000000 0 0 400000000 0>, + <400000000 0 0 480000000 0>, + <400000000 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,vfe-lite1 { + cell-index = <4>; + compatible = "qcom,vfe-lite165"; + reg-names = "ife-lite"; + reg = <0x0accb000 0x5000>; + reg-cam-base = <0xcb000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_1_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <12>; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + cam_icp: qcom,icp { + cell-index = <0>; + compatible = "qcom,cam-icp_v1"; + icp-version = <0x0100>; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "icp_qgic", "icp_sierra", "icp_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "icp"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + src-clock-name = "icp_clk_src"; + clocks = + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK>; + clock-rates = + <100000000 0 400000000 0>, + <200000000 0 400000000 0>, + <300000000 0 600000000 0>, + <400000000 0 600000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + fw_name = "CAMERA_ICP_170.elf"; + ubwc-ipe-fetch-cfg = <0x7073 0x707b>; + ubwc-ipe-write-cfg = <0x161cf 0x161ef>; + ubwc-bps-fetch-cfg = <0x7073 0x707b>; + ubwc-bps-write-cfg = <0x161cf 0x161ef>; + qos-val = <0x00000A0A>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0xa000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 430000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_165"; + reg-names = "jpege_hw", "cam_camnoc"; + reg = <0xac4e000 0x4000>, + <0x0ac9f000 0x10000>; + reg-cam-base = <0x4e000 0x9f000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <22 23>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <2>; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_165"; + reg-names = "jpegdma_hw", "cam_camnoc"; + reg = <0xac52000 0x4000>, + <0x0ac9f000 0x10000>; + reg-cam-base = <0x52000 0x9f000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + cam_hw_pid = <20 21>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <2>; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0x1000>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "lrme_clk_src", + "lrme_clk"; + clocks = <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-rates = <240000000 240000000>, + <300000000 300000000>, + <320000000 320000000>, + <400000000 400000000>, + <400000000 400000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; + + qcom,cam-cpas { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x0ac40000 0x1000>, + <0x0ac9f000 0x10000>; + reg-cam-base = <0x40000 0x9f000>; + cam_hw_fuse = , + , + , + , + ; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk", + "icp_ahb_clk", + "icp_clk"; + clocks = + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0 0>, + <0 0 80000000 0 150000000 0 0 0>, + <0 0 80000000 0 240000000 0 0 0>, + <0 0 80000000 0 320000000 0 0 0>, + <0 0 80000000 0 400000000 0 0 0>, + <0 0 80000000 0 480000000 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &cnoc2 SLAVE_CAMERA_CFG>; + cam-ahb-num-cases = <7>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", + "lowsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "ipe0", "cam-cdm-intf0", "cpas-cdm0", + "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "lrmecpas0"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_wr_sum: level3-rt0-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_sum: level3-nrt1-rd-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <3>; + camnoc-max-needed; + level2_rt0_write0: level2-rt0-write0 { + cell-index = <3>; + node-name = "level2-rt0-write0"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt1_write0: level2-rt1-write0 { + cell-index = <4>; + node-name = "level2-rt1-write0"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_write0: level2-nrt0-write0 { + cell-index = <5>; + node-name = "level2-nrt0-write0"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_read0: level2-nrt0-read0 { + cell-index = <6>; + node-name = "level2-nrt0-read0"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_read0: level2-nrt1-read0 { + cell-index = <7>; + node-name = "level2-nrt1-read0"; + parent-node = <&level3_nrt1_rd_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_write0: level1-rt0-write0 { + cell-index = <8>; + node-name = "level1-rt0-write0"; + parent-node = <&level2_rt0_write0>; + traffic-merge-type = + ; + }; + + level1_rt1_write0: level1-rt1-write0 { + cell-index = <9>; + node-name = "level1-rt1-write0"; + parent-node = <&level2_rt1_write0>; + traffic-merge-type = + ; + }; + + level1_rt1_write1: level1-rt1-write1 { + cell-index = <10>; + node-name = "level1-rt1-write1"; + parent-node = <&level2_rt1_write0>; + traffic-merge-type = + ; + }; + + level1_nrt0_write0: level1-nrt0-write0 { + cell-index = <11>; + node-name = "level1-nrt0-write0"; + parent-node = <&level2_nrt0_write0>; + traffic-merge-type = + ; + }; + + level1_nrt0_read0: level1-nrt0-read0 { + cell-index = <12>; + node-name = "level1-nrt0-read0"; + parent-node = <&level2_nrt0_read0>; + traffic-merge-type = + ; + }; + + level1_nrt1_write0: level1-nrt1-write0 { + cell-index = <13>; + node-name = "level1-nrt1-write0"; + parent-node = <&level2_nrt0_write0>; + traffic-merge-type = + ; + }; + + level1_nrt1_read0: level1-nrt1-read0 { + cell-index = <14>; + node-name = "level1-nrt1-read0"; + parent-node = <&level2_nrt0_read0>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_rdi_wr: ife0-rdi-wr { + cell-index = <16>; + node-name = "ife0-rdi-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife1_rdi_wr: ife1-rdi-wr { + cell-index = <17>; + node-name = "ife1-rdi-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife2_rdi_wr: ife2-rdi-wr { + cell-index = <18>; + node-name = "ife2-rdi-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife3_rdi_wr: ife3-rdi-wr { + cell-index = <19>; + node-name = "ife3-rdi-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife4_rdi_wr: ife4-rdi-wr { + cell-index = <20>; + node-name = "ife4-rdi-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_write0>; + }; + + ife0_pixelall_wr: ife0-pixelall-wr { + cell-index = <21>; + node-name = "ife0-pixelall-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_write0>; + }; + + ife1_pixelall_wr: ife1-pixelall-wr { + cell-index = <22>; + node-name = "ife1-pixelall-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_write0>; + }; + + ife2_pixelall_wr: ife2-pixelall-wr { + cell-index = <23>; + node-name = "ife2-pixelall-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_write1>; + }; + + ipe0_ref_wr: ipe0-ref-wr { + cell-index = <24>; + node-name = "ipe0-ref-wr"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <25>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <26>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe0_viddisp_wr: ipe0-viddisp-wr { + cell-index = <27>; + node-name = "ipe0-viddisp-wr"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_write0>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <28>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_read0>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <29>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_read0>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <30>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_read0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <31>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_write0>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <32>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_read0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <33>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_write0>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <34>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_read0>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <35>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_read0>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <36>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_read0>; + }; + }; + }; + }; +}; From 127d0dc73807ad9c6804d189cb13c064b18c1b8d Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Thu, 7 Sep 2023 15:15:34 -0700 Subject: [PATCH 003/274] ARM: diff catchup Change-Id: I11aa1e8bf669c77769243b0d601b93397fda10f1 Signed-off-by: Savita Patted --- bindings/msm-cam-cpas.txt | 1 + kalama-sg-hhg-camera-sensor.dtsi | 1 + kona-camera-sensor-mtp.dtsi | 1 + kona-camera-sensor-qrd.dtsi | 1 + kona-camera-sensor-xr.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index 33c70f51..179a4e76 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -593,3 +593,4 @@ Example: }; }; }; + diff --git a/kalama-sg-hhg-camera-sensor.dtsi b/kalama-sg-hhg-camera-sensor.dtsi index dbbb4ce2..a51af11e 100644 --- a/kalama-sg-hhg-camera-sensor.dtsi +++ b/kalama-sg-hhg-camera-sensor.dtsi @@ -91,3 +91,4 @@ status = "ok"; }; }; + diff --git a/kona-camera-sensor-mtp.dtsi b/kona-camera-sensor-mtp.dtsi index a35e40d1..8b99c31f 100644 --- a/kona-camera-sensor-mtp.dtsi +++ b/kona-camera-sensor-mtp.dtsi @@ -678,3 +678,4 @@ clock-rates = <24000000>; }; }; + diff --git a/kona-camera-sensor-qrd.dtsi b/kona-camera-sensor-qrd.dtsi index 8dea38e6..632cc084 100644 --- a/kona-camera-sensor-qrd.dtsi +++ b/kona-camera-sensor-qrd.dtsi @@ -676,3 +676,4 @@ clock-rates = <24000000>; }; }; + diff --git a/kona-camera-sensor-xr.dtsi b/kona-camera-sensor-xr.dtsi index 5708e84f..f0bbfdcb 100644 --- a/kona-camera-sensor-xr.dtsi +++ b/kona-camera-sensor-xr.dtsi @@ -689,3 +689,4 @@ }; }; + From 0d551b2a7f8a2d1e628d63df128d747524b7cbc6 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Thu, 7 Sep 2023 15:16:30 -0700 Subject: [PATCH 004/274] Snap for drop 08/29/2023 mainline 1045 LA.VENDOR.14.3.0.AU343. Change-Id: Ia71e758765fbb3af09343ea2add076fde670e7c1 Signed-off-by: Savita Patted From 5ebd1384a506e4db724dfe5616875795511c1b21 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Thu, 7 Sep 2023 15:17:17 -0700 Subject: [PATCH 005/274] Snap for drop 08/31/2023 mainline 1046 LA.VENDOR.14.3.0.AU343. Change-Id: I7ff7bc0731ae2eeed32921c54e0e881b387a90c4 Signed-off-by: Savita Patted From 2f03a4a4b7adf51814a809e0dc399473d4d44985 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Thu, 7 Sep 2023 15:17:56 -0700 Subject: [PATCH 006/274] Snap for drop 09/01/2023 mainline 1047 LA.VENDOR.14.3.0.AU343. Change-Id: Ia7bf895ccc4c83ece19d3de3d469c601fbb84a5d Signed-off-by: Savita Patted From 504a69200958394ef6d9033bc162625a18929b03 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Thu, 7 Sep 2023 15:18:40 -0700 Subject: [PATCH 007/274] Snap for drop 09/01/2023 mainline 1048 LA.VENDOR.14.3.0.AU343. Change-Id: Iaa81f5645af4b0f2cfab9ebd2eded19dfeb798aa Signed-off-by: Savita Patted From 4fae3ba694c2fb7e0213136d5028c3a8d1792e11 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Thu, 7 Sep 2023 15:23:50 -0700 Subject: [PATCH 008/274] Snap for drop 09/05/2023 mainline 1049 LA.VENDOR.14.3.0.AU343. Change-Id: I9b27e2e200b454a3146d57e3b09f45bacce3d9be Signed-off-by: Savita Patted From 76d677d0369fd9a58d7aee0388137e394abee79f Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 7 Sep 2023 10:52:39 -0700 Subject: [PATCH 009/274] Snap for drop 09/06/2023 mainline 1050 LA.VENDOR.14.3.0.AU343. Change-Id: I7daf9e8b558ed6d7dc566884564c6e7900bfc3cb Signed-off-by: hchintal From 189d0ad66ef5cad1a2a7b02d622b99f2e6f7c80b Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 7 Sep 2023 16:13:42 -0700 Subject: [PATCH 010/274] Snap for drop 09/07/2023 mainline 1051 LA.VENDOR.14.3.0.AU343. Change-Id: Id76e4ced286b53106f0dbd6468069ed8705eab0d Signed-off-by: hchintal From c119c7cc6a52481c72747409ff6f9e8b0460dad5 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 12 Sep 2023 15:16:04 -0700 Subject: [PATCH 011/274] Snap for drop 09/11/2023 mainline 1053 LA.VENDOR.14.3.0.AU343. Change-Id: Ic27af6b0dfc8e4ced80efffa11dd2702dc636b63 Signed-off-by: hchintal From cb187ef978bf99f56af04c197a3001076f18567f Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 13 Sep 2023 09:20:22 -0700 Subject: [PATCH 012/274] Snap for drop 09/12/2023 mainline 1054 LA.VENDOR.14.3.0.AU343. Change-Id: I8218765ea0bcbb0a3069caa3bf2460eb3ceb2695 Signed-off-by: hchintal From 5283ca55fdce08d3c77af3b4394d4adc17660945 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 15 Sep 2023 17:09:18 -0700 Subject: [PATCH 013/274] Snap for drop 09/15/2023 mainline 1056 LA.VENDOR.14.3.0.AU343. Change-Id: Id6d5beac567bda413b88e74056dd5a7387d1ea9b Signed-off-by: hchintal From 542b5cebf46bc36906d9f2703f048a373e5bcd84 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 21 Sep 2023 15:53:16 -0700 Subject: [PATCH 014/274] Snap for drop 09/20/2023 mainline 1059 LA.VENDOR.14.3.0.AU343. Change-Id: Ifef1ef605abfe3f582f289b0e80fcd27c670c239 Signed-off-by: hchintal From 9e3540ea84f1b7c27aac0ab349352d87bb3fd372 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 25 Sep 2023 15:21:56 -0700 Subject: [PATCH 015/274] Snap for drop 09/25/2023 mainline 1061 LA.VENDOR.14.3.0.AU343. Change-Id: I0421f932301e51a0ba918102285949f03abca999 Signed-off-by: hchintal From 4acbd71fcdd9f3e2ff7b0733bc2ad2424ce31e1d Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 27 Sep 2023 15:00:39 -0700 Subject: [PATCH 016/274] Snap for drop 09/26/2023 mainline 1062 LA.VENDOR.14.3.0.AU343. Change-Id: If677ce812e88a8e0e228be4d8702447a7d435db0 Signed-off-by: hchintal From 15bfa1b95b5d69e9bd52b46f7c230ecca15d9210 Mon Sep 17 00:00:00 2001 From: hchintal Date: Fri, 29 Sep 2023 14:52:48 -0700 Subject: [PATCH 017/274] Snap for drop 09/27/2023 mainline 1063 LA.VENDOR.14.3.0.AU343. Change-Id: Icef16a216e2c68f30b539241ac7cfe3f2cf601c8 Signed-off-by: hchintal From 1ac262d23734898041aaa32dcbdb0f71c93f7a00 Mon Sep 17 00:00:00 2001 From: hchintal Date: Fri, 29 Sep 2023 14:52:51 -0700 Subject: [PATCH 018/274] Snap for drop 09/28/2023 mainline 1064 LA.VENDOR.14.3.0.AU343. Change-Id: Ie57ba7f71a9281684436081a7bdd8ec52ac7f528 Signed-off-by: hchintal From 49b7b980f38d3cfbb50008a4dd8d7b36f751df0e Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 2 Oct 2023 10:36:59 -0700 Subject: [PATCH 019/274] Snap for drop 09/29/2023 mainline 1065 LA.VENDOR.14.3.0.AU343. Change-Id: Ifc4ed11a1f0f21e1ba52739bc0d99263f79d9d83 Signed-off-by: hchintal From fae58a38f473dbf7eaf076845dbd956d618ad34c Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 3 Oct 2023 12:57:23 -0700 Subject: [PATCH 020/274] Snap for drop 10/02/2023 mainline 1066 LA.VENDOR.14.3.0.AU343. Change-Id: I8198d841bf6bc6d958c15e3f569674bd7872ef53 Signed-off-by: hchintal From a93d821a67d0b263c7aabb4bdafec7ef6acff89f Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 3 Oct 2023 17:51:33 -0700 Subject: [PATCH 021/274] Snap for drop 10/03/2023 mainline 1067 LA.VENDOR.14.3.0.AU343. Change-Id: I8fd34d4470b27f904c75f311a62ba8dd388d4f60 Signed-off-by: hchintal From c3dfc4d1bf307d55a22d7e19900d3a961d59f179 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 12 Oct 2023 16:28:06 -0700 Subject: [PATCH 022/274] Snap for drop 10/05/2023 mainline 1069 LA.VENDOR.14.3.0.AU383. Change-Id: I8c371414b66b9c0c65e10442399ac3a6e2592d7b Signed-off-by: hchintal From ecdf9b6711488daf5a97b78a6b6a74c7df3b3927 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 12 Oct 2023 16:28:09 -0700 Subject: [PATCH 023/274] Snap for drop 10/06/2023 mainline 1070 LA.VENDOR.14.3.0.AU383. Change-Id: I79e7b42e15b1d9e1dd5af5baa7bee5872c8db505 Signed-off-by: hchintal From 19b255277581302611dc1e321cc88ad98ab02332 Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 16 Oct 2023 15:58:24 -0700 Subject: [PATCH 024/274] Snap for drop 10/12/2023 mainline 1074 LA.VENDOR.14.3.0.AU383. Change-Id: I682867e36f8ec63a9f74befd66ad0ae5d5797809 Signed-off-by: hchintal From afd20e8d8dbd37dde96b58a19f549ec7fc7946c4 Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 16 Oct 2023 15:58:26 -0700 Subject: [PATCH 025/274] Snap for drop 10/13/2023 mainline 1075 LA.VENDOR.14.3.0.AU383. Change-Id: I47ef143e9dd57f1f237df3870bf73de640e9bfbf Signed-off-by: hchintal From f0f99a97aaf48561032d07982315bdfe11d302a7 Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 18 Oct 2023 16:57:46 -0700 Subject: [PATCH 026/274] Snap for drop 10/17/2023 mainline 1077 LA.VENDOR.14.3.0.AU383. Change-Id: Id16978a3b5eb6a3f9a97b6493a28f1993bd71298 Signed-off-by: hchintal From 8020f1e421ebf5dc10080f8b9e37569457931aeb Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 19 Oct 2023 11:36:37 -0700 Subject: [PATCH 027/274] Snap for drop 10/18/2023 mainline 1078 LA.VENDOR.14.3.0.AU383. Change-Id: I9d76683fb2bcdc25ed4f6fb3a6a7fcf6d9ab0acc Signed-off-by: hchintal From 09a762082c03dd1035c4bf61069e6cfe87a88e7c Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 24 Oct 2023 10:48:51 -0700 Subject: [PATCH 028/274] Snap for drop 10/23/2023 mainline 1081 LA.VENDOR.14.3.0.AU383. Change-Id: I67aa0b15e9730f4f3ee8b78230db97c80ca9c981 Signed-off-by: hchintal From 4156fcd3b5a5a57b310b0dd1536f63dbcc012ee9 Mon Sep 17 00:00:00 2001 From: hchintal Date: Sun, 29 Oct 2023 22:00:14 -0700 Subject: [PATCH 029/274] Snap for drop 10/27/2023 mainline 1084 LA.VENDOR.14.3.0.AU383. Change-Id: I729c4c743c428107cee41e3e15c519858f54bb9a Signed-off-by: hchintal From 03de579f03485e53d624f25af785eecdc7d2e512 Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 1 Nov 2023 10:51:34 -0700 Subject: [PATCH 030/274] Snap for drop 10/31/2023 mainline 1086 LA.VENDOR.14.3.0.AU383. Change-Id: I48a0e528e4b820ad463499053d245ea0315b61dc Signed-off-by: hchintal From 81de41a7eee2224abcfd5f788341f54a50207756 Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 1 Nov 2023 14:53:40 -0700 Subject: [PATCH 031/274] Snap for drop 11/01/2023 mainline 1087 LA.VENDOR.14.3.0.AU383. Change-Id: I5ed5edfe15d04875c3050f0bac104aeb167df2d4 Signed-off-by: hchintal From 92c283726a4ebd7689d360a11b72f3951c8c8edb Mon Sep 17 00:00:00 2001 From: chengxue Date: Thu, 2 Nov 2023 15:26:53 -0700 Subject: [PATCH 032/274] ARM: dts: msm: Add trustedvm camera item support Add standalone files for trustedvm camera config and dts configuration. CRs-Fixed: 3494729 Change-Id: I96eff41b7555b9b88769860d4d176f927154a78d Signed-off-by: chengxue --- config/pineapple_tuivm.mk | 3 + trustedvm-pineapple-camera-sensor-cdp.dts | 19 + trustedvm-pineapple-camera-sensor-cdp.dtsi | 250 ++ trustedvm-pineapple-camera-sensor-mtp.dts | 19 + trustedvm-pineapple-camera-sensor-mtp.dtsi | 250 ++ trustedvm-pineapple-camera-sensor-qrd.dts | 19 + trustedvm-pineapple-camera-sensor-qrd.dtsi | 250 ++ trustedvm-pineapple-camera.dtsi | 2581 ++++++++++++++++++++ 8 files changed, 3391 insertions(+) create mode 100644 config/pineapple_tuivm.mk create mode 100644 trustedvm-pineapple-camera-sensor-cdp.dts create mode 100644 trustedvm-pineapple-camera-sensor-cdp.dtsi create mode 100644 trustedvm-pineapple-camera-sensor-mtp.dts create mode 100644 trustedvm-pineapple-camera-sensor-mtp.dtsi create mode 100644 trustedvm-pineapple-camera-sensor-qrd.dts create mode 100644 trustedvm-pineapple-camera-sensor-qrd.dtsi create mode 100644 trustedvm-pineapple-camera.dtsi diff --git a/config/pineapple_tuivm.mk b/config/pineapple_tuivm.mk new file mode 100644 index 00000000..e68ed047 --- /dev/null +++ b/config/pineapple_tuivm.mk @@ -0,0 +1,3 @@ +dtbo-$(CONFIG_ARCH_PINEAPPLE) := trustedvm-pineapple-camera-sensor-mtp.dtbo \ + trustedvm-pineapple-camera-sensor-cdp.dtbo \ + trustedvm-pineapple-camera-sensor-qrd.dtbo \ No newline at end of file diff --git a/trustedvm-pineapple-camera-sensor-cdp.dts b/trustedvm-pineapple-camera-sensor-cdp.dts new file mode 100644 index 00000000..75717ea8 --- /dev/null +++ b/trustedvm-pineapple-camera-sensor-cdp.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "trustedvm-pineapple-camera.dtsi" +#include "trustedvm-pineapple-camera-sensor-cdp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple CDP/RCM - TrustedVM"; + compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,cdp", "qcom,rcm", "qcom,pineapple-rcm"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x10001 0>, <21 0>; +}; diff --git a/trustedvm-pineapple-camera-sensor-cdp.dtsi b/trustedvm-pineapple-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..4a13f9e2 --- /dev/null +++ b/trustedvm-pineapple-camera-sensor-cdp.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + status = "ok"; + }; +}; diff --git a/trustedvm-pineapple-camera-sensor-mtp.dts b/trustedvm-pineapple-camera-sensor-mtp.dts new file mode 100644 index 00000000..6e7e233b --- /dev/null +++ b/trustedvm-pineapple-camera-sensor-mtp.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "trustedvm-pineapple-camera.dtsi" +#include "trustedvm-pineapple-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple MTP - TrustedVM"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,mtp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x10008 0>, <0x50008 0>; +}; diff --git a/trustedvm-pineapple-camera-sensor-mtp.dtsi b/trustedvm-pineapple-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..4a13f9e2 --- /dev/null +++ b/trustedvm-pineapple-camera-sensor-mtp.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + status = "ok"; + }; +}; diff --git a/trustedvm-pineapple-camera-sensor-qrd.dts b/trustedvm-pineapple-camera-sensor-qrd.dts new file mode 100644 index 00000000..607b9df4 --- /dev/null +++ b/trustedvm-pineapple-camera-sensor-qrd.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "trustedvm-pineapple-camera.dtsi" +#include "trustedvm-pineapple-camera-sensor-qrd.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple QRD - TrustedVM"; + compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,qrd"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <15 0>, <0x1000B 0>, <0x5000B 0>, <0x1f 0>; +}; diff --git a/trustedvm-pineapple-camera-sensor-qrd.dtsi b/trustedvm-pineapple-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..4a13f9e2 --- /dev/null +++ b/trustedvm-pineapple-camera-sensor-qrd.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + status = "ok"; + }; +}; diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi new file mode 100644 index 00000000..44889a9d --- /dev/null +++ b/trustedvm-pineapple-camera.dtsi @@ -0,0 +1,2581 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci_i2c_sda3_active { + mux { + pins = "gpio12"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio12"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { + mux { + pins = "gpio12"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci_i2c_scl3_active { + mux { + pins = "gpio13"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio13"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { + mux { + pins = "gpio13"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda4_active: cci_i2c_sda4_active { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda4_suspend: cci_i2c_sda4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_active: cci_i2c_scl4_active { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl4_suspend: cci_i2c_scl4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_active: cci_i2c_sda5_active { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda5_suspend: cci_i2c_sda5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_active: cci_i2c_scl5_active { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl5_suspend: cci_i2c_scl5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_aon_mclk2"; + }; + + config { + pins = "gpio102"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_aon_mclk2"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_aon_mclk4"; + }; + + config { + pins = "gpio104"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_aon_mclk4"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio108"; + function = "cam_mclk"; + }; + + config { + pins = "gpio108"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio108"; + function = "cam_mclk"; + }; + + config { + pins = "gpio108"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_active: cam_sensor_mclk7_active { + /* MCLK7 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_suspend: cam_sensor_mclk7_suspend { + /* MCLK7 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst7: cam_sensor_active_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst7: cam_sensor_suspend_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_ponv_front_active: cam_sensor_ponv_front_active { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_front_suspend: cam_sensor_ponv_front_suspend { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_ponv_rear_active: cam_sensor_ponv_rear_active { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_rear_suspend: cam_sensor_ponv_rear_suspend { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + cam-bypass-driver = <(CAM_BYPASS_RGLTR | + CAM_BYPASS_RGLTR_MODE | + CAM_BYPASS_CLKS | + CAM_BYPASS_CESTA | + CAM_BYPASS_ICC)>; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0766>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xacea000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xea000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xacec000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@acee000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xacee000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xee000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac15000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac16000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac17000 { + cell-index = <2>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac17000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x17000>; + interrupt-names = "CCI2"; + interrupts = ; + regulator-names = "gdscr"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>; + pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; + pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; + pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci2: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x808 0x20>; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0xf 0xffe00000>; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x18C0 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1880 0x00>; + cam-smmu-label = "icp"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0xf9500000 0xf 0x06a00000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xc0700000 */ + iova-region-start = <0x0 0xc0700000>; + /* Length: 0x38e00000 */ + iova-region-len = <0x0 0x38e00000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0xc0200000 */ + iova-region-start = <0x0 0xc0200000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0xc0300000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0xc0200000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x2>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0xc0100000>; + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0xc0100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf9500000 */ + iova-region-start = <0x0 0xf9500000>; + /* Length: 0xf06a00000 */ + iova-region-len = <0xf 0x06a00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0xc0000000 */ + iova-region-start = <0x0 0xc0000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1861 0x00>; + cam-smmu-label = "rt-cdm"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + multiple-client-devices; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac13000 0x1000>, + <0xac19000 0xac80>; + reg-cam-base = <0x13000 0x19000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "gdsc"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_axi_rt_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", + "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = ; + interconnect-names = "cam_ahb"; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "csiphy6","csiphy7", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "sfe0", "sfe1", "sfe2", "custom0", "custom1", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", + "cam-cdm-intf0", "bps0", "icp0", "cre0", + "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", + "tpg13", "tpg14", "tpg15"; + enable-smart-qos; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-name = "cam_hf"; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv"; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf"; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_icp"; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x9230>; + priority-lut-high-offset = <0x9234>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x9430>; + priority-lut-high-offset = <0x9434>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x9630>; + priority-lut-high-offset = <0x9634>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <11>; + node-name = "level1-rt4-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x9830>; + priority-lut-high-offset = <0x9834>; + }; + + level1_rt0_rd: level1-rt0-rd { + cell-index = <12>; + node-name = "level1-sfe-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt1_wr: level1-nrt1-wr { + cell-index = <14>; + node-name = "level1-nrt0-wr1"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt3_rd: level1-nrt3-rd { + cell-index = <15>; + node-name = "level1-nrt3-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt1_rd: level1-nrt1-rd { + cell-index = <16>; + node-name = "level1-nrt1-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <17>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <18>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <19>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <20>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <21>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <22>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <23>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe0_all_wr: sfe0-all-wr { + cell-index = <24>; + node-name = "sfe0-all-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe1_all_wr: sfe1-all-wr { + cell-index = <25>; + node-name = "sfe1-all-wr"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + sfe2_all_wr: sfe2-all-wr { + cell-index = <26>; + node-name = "sfe2-all-wr"; + client-name = "sfe2"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + custom0_wr: custom0-wr { + cell-index = <27>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_wr>; + }; + + custom1_wr: custom1-wr { + cell-index = <28>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_pdaf_linear_wr: ife0-pdaf-linear-wr { + cell-index = <29>; + node-name = "ife0-pdaf-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_linear_wr: ife1-pdaf-linear-wr { + cell-index = <30>; + node-name = "ife1-pdaf-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_linear_wr: ife2-pdaf-linear-wr { + cell-index = <31>; + node-name = "ife2-pdaf-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <32>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <33>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <34>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <35>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <36>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <37>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + sfe1_all_rd: sfe1-all-rd { + cell-index = <38>; + node-name = "sfe1-all-rd"; + client-name = "sfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + sfe2_all_rd: sfe2-all-rd { + cell-index = <39>; + node-name = "sfe2-all-rd"; + client-name = "sfe2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt0_rd>; + }; + + custom0_all_rd: custom0-rd { + cell-index = <40>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd>; + }; + + custom1_rd: custom1-rd { + cell-index = <41>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <42>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <43>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <44>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <45>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <46>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + + jpeg_enc1_all_wr: jpeg-enc1-all-wr { + cell-index = <47>; + node-name = "jpeg-enc1-all-wr"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + jpeg_dma1_all_wr: jpeg-dma1-all-wr { + cell-index = <48>; + node-name = "jpeg-dma1-all-wr"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <49>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt3_rd>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <50>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt3_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <51>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <52>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + + jpeg_enc1_all_rd: jpeg1-enc1-all-rd { + cell-index = <53>; + node-name = "jpeg-enc1-rd"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + jpeg_dma1_all_rd: jpeg1-dma1-all-rd { + cell-index = <54>; + node-name = "jpeg-dma1-rd"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt1_rd>; + }; + + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <55>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <56>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <57>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <58>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <59>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <60>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + rt_cdm4_all_rd: rt-cdm4-all-rd { + cell-index = <61>; + node-name = "rt-cdm4-all-rd"; + client-name = "rt-cdm4"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <62>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac25000 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + nrt-device; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac26000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac26000 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + nrt-device; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac27000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac27000 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x27000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + nrt-device; + cdm-client-names = "ife2", "dualife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac28000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac28000 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x28000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm4@ac29000 { + cell-index = <4>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac29000 0x580>; + reg-names = "rt-cdm4"; + reg-cam-base = <0x29000>; + interrupt-names = "rt-cdm4"; + interrupts = ; + regulator-names = "gdsc"; + nrt-device; + cdm-client-names = "ife4"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <30>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe880"; + reg-names = "sfe0"; + reg = <0xac9e000 0x8000>; + reg-cam-base = <0x9e000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe0"; + interrupts = ; + regulator-names = "gdsc", "sfe0"; + cam_hw_pid = <11 0>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe1: qcom,sfe1@aca6000 { + cell-index = <1>; + compatible = "qcom,sfe880"; + reg-names = "sfe1"; + reg = <0xaca6000 0x8000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe1"; + interrupts = ; + regulator-names = "gdsc", "sfe1"; + cam_hw_pid = <12 1>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe2: qcom,sfe2@acae000 { + cell-index = <2>; + compatible = "qcom,sfe880"; + reg-names = "sfe2"; + reg = <0xacae000 0x8000>; + reg-cam-base = <0xae000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "sfe2"; + interrupts = ; + regulator-names = "gdsc", "sfe2"; + cam_hw_pid = <13 2>; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid880"; + reg-names = "csid", "csid_top"; + reg = <0xacb8000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xb8000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe880"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac62000 0xf000>, + <0xac19000 0xac80>; + reg-cam-base = <0x62000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife0"; + interrupts = ; + regulator-names = "gdsc", "ife0"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 20 24 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acb9000 { + cell-index = <1>; + compatible = "qcom,csid880"; + reg-names = "csid", "csid_top"; + reg = <0xacba000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xba000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac71000 { + cell-index = <1>; + compatible = "qcom,vfe880"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac71000 0xf000>, + <0xac19000 0xac80>; + reg-cam-base = <0x71000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife1"; + interrupts = ; + regulator-names = "gdsc", "ife1"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 21 25 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acbb000 { + cell-index = <2>; + compatible = "qcom,csid880"; + reg-names = "csid", "csid_top"; + reg = <0xacbc000 0xd00>, + <0xacb6000 0x1000>; + reg-cam-base = <0xbc000 0xb6000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@ac80000 { + cell-index = <2>; + compatible = "qcom,vfe880"; + reg-names = "ife", "cam_camnoc"; + reg = <0xac80000 0xf000>, + <0xac19000 0xac80>; + reg-cam-base = <0x80000 0x19000>; + rt-wrapper-base = <0x62000>; + interrupt-names = "ife2"; + interrupts = ; + regulator-names = "gdsc", "ife2"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <18 22 26 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acca000 { + cell-index = <3>; + compatible = "qcom,csid-lite880"; + reg-names = "csid-lite"; + reg = <0xaccb000 0xa00>; + reg-cam-base = <0xcb000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acca000 { + cell-index = <3>; + compatible = "qcom,vfe-lite880"; + reg-names = "ife-lite"; + reg = <0xaccb000 0x2800>; + reg-cam-base = <0xcb000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <27>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@accf000 { + cell-index = <4>; + compatible = "qcom,csid-lite880"; + reg-names = "csid-lite"; + reg = <0xacd0000 0xa00>; + reg-cam-base = <0xd0000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "gdsc"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@accf000 { + cell-index = <4>; + compatible = "qcom,vfe-lite880"; + reg-names = "ife-lite"; + reg = <0xacd0000 0x2800>; + reg-cam-base = <0xd0000>; + rt-wrapper-base = <0xca000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "gdsc"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <28>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@acf6000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "gdsc"; + interrupt-names = "tpg0"; + interrupts = ; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@acf7000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xacf7000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf7000 0x13000>; + regulator-names = "gdsc"; + interrupt-names = "tpg1"; + interrupts = ; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@acf8000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xacf8000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf8000 0x13000>; + regulator-names = "gdsc"; + interrupt-names = "tpg2"; + interrupts = ; + status = "ok"; + }; +}; + From 602b314d6e82320df4aa612073d8bf4f5675f162 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 2 Nov 2023 15:52:18 -0700 Subject: [PATCH 033/274] Snap for drop 11/02/2023 mainline 1088 LA.VENDOR.14.3.0.AU383 44aa026 Merge 'ARM: dts: msm: Add trustedvm camera item support' into camera-kernel.lnx.dev Change-Id: I98dcb8b17771c8d6b486d60082f618bafc06e312 Signed-off-by: hchintal From 15f0d910060bd9d378ef189574ad7613fb3b1b40 Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 7 Nov 2023 12:06:38 -0800 Subject: [PATCH 034/274] Snap for drop 11/06/2023 mainline 1090 LA.VENDOR.14.3.0.AU383 Change-Id: Iaa1dcb701b5165aefe2313bdfed08fb65a4180d4 Signed-off-by: hchintal From 3d725b5858fdcf6752f94e1dd94ba25818144e58 Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Tue, 7 Nov 2023 18:43:40 -0800 Subject: [PATCH 035/274] ARM: dts: msm: Add interconnect path names for pineapple Add interconnect path names separately in camera bus nodes, so that they can be matched to interconnects in top level cpas node. This is done to ensure compatibility with of_icc_get during creation of path handles for ahb and axi voting. CRs-Fixed: 3656156 Change-Id: I669e1c6b05735d2162867d954af927baca1a829d Signed-off-by: Mukund Madhusudan Atre --- pineapple-camera.dtsi | 46 +++++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/pineapple-camera.dtsi b/pineapple-camera.dtsi index 68d3e191..ba0cd546 100644 --- a/pineapple-camera.dtsi +++ b/pineapple-camera.dtsi @@ -1614,9 +1614,28 @@ camnoc-axi-clk-bw-margin-perc = <20>; domain-id = , ; - interconnect-names = "cam_ahb"; - interconnects =<&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_CAMERA_CFG>; + cam-icc-path-names = "cam_ahb"; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv", + "cam_sf_0", + "cam_sf_icp"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>, + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; rpmh-bcm-info = <13 0x4 0x800 0 4>; cam-ahb-num-cases = <8>; cam-ahb-bw-KBps = @@ -1673,19 +1692,10 @@ ib-bw-voting-needed; rt-axi-port; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0", + cam-icc-path-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; - interconnects = - <&mmss_noc MASTER_CAMNOC_HF - &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 - &mc_virt SLAVE_EBI1_CAM_IFE_0>, - <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 - &mc_virt SLAVE_EBI1_CAM_IFE_1>, - <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 - &mc_virt SLAVE_EBI1_CAM_IFE_2>; }; }; @@ -1695,10 +1705,7 @@ traffic-merge-type = ; qcom,axi-port-mnoc { - interconnect-names = "cam_sf_0"; - interconnects = - <&mmss_noc MASTER_CAMNOC_SF - &mc_virt SLAVE_EBI1>; + cam-icc-path-names = "cam_sf_0"; }; }; @@ -1708,11 +1715,8 @@ traffic-merge-type = ; qcom,axi-port-mnoc { - interconnect-names = + cam-icc-path-names = "cam_sf_icp"; - interconnects = - <&mmss_noc MASTER_CAMNOC_ICP - &mc_virt SLAVE_EBI1>; }; }; }; From abfc61bc8317c1327c766e516f593259dbdacd58 Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 7 Nov 2023 18:56:24 -0800 Subject: [PATCH 036/274] Snap for drop 11/07/2023 mainline 1091 LA.VENDOR.14.3.0.AU383 camera-devicetree: d1fe6cc Merge 'ARM: dts: msm: Add interconnect path names for pineapple' into camera-kernel.lnx.dev Change-Id: I2aed2b9a05ef48f2d4dde4256faae654fe6af29a Signed-off-by: hchintal From 28ba146d6b8461c99f0162bca9cdbe4b496c6367 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Thu, 9 Nov 2023 14:50:11 -0800 Subject: [PATCH 037/274] ARM: dts: msm: Add devicetree changes for Sun dtsi Update camera devicetree for changes in memory, regulators, interrupts, clocks for CCI, CSIPHY, CPAS, CDM, TPG, VFE, CSID, IPE, BPS, JPEG, VFE-lite and CSID-lite nodes. CRs-Fixed: 3648309 Change-Id: Ice6673d49cbd3958169c03863c34d40bf08317ee Signed-off-by: Soumen Ghosh --- config/sun.mk | 1 + sun-camera.dts | 16 + sun-camera.dtsi | 3317 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 3334 insertions(+) create mode 100644 config/sun.mk create mode 100644 sun-camera.dts create mode 100644 sun-camera.dtsi diff --git a/config/sun.mk b/config/sun.mk new file mode 100644 index 00000000..a9127f8e --- /dev/null +++ b/config/sun.mk @@ -0,0 +1 @@ +dtbo-$(CONFIG_ARCH_SUN) := sun-camera.dtbo diff --git a/sun-camera.dts b/sun-camera.dts new file mode 100644 index 00000000..2c762bf7 --- /dev/null +++ b/sun-camera.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sun-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <8 0>, <15 0>; +}; diff --git a/sun-camera.dtsi b/sun-camera.dtsi new file mode 100644 index 00000000..2c3c2698 --- /dev/null +++ b/sun-camera.dtsi @@ -0,0 +1,3317 @@ +#include +#include + +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci_i2c_scl3_active { + mux { + pins = "gpio12"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio12"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { + mux { + pins = "gpio12"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci_i2c_sda3_active { + mux { + pins = "gpio13"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio13"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { + mux { + pins = "gpio13"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda4_active: cci_i2c_sda4_active { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda4_suspend: cci_i2c_sda4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_active: cci_i2c_scl4_active { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl4_suspend: cci_i2c_scl4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_active: cci_i2c_sda5_active { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda5_suspend: cci_i2c_sda5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_active: cci_i2c_scl5_active { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl5_suspend: cci_i2c_scl5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio89"; + function = "cam_mclk"; + }; + + config { + pins = "gpio89"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio89"; + function = "cam_mclk"; + }; + + config { + pins = "gpio89"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio90"; + function = "cam_mclk"; + }; + + config { + pins = "gpio90"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio90"; + function = "cam_mclk"; + }; + + config { + pins = "gpio90"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio91"; + function = "cam_asc_mclk2"; + }; + + config { + pins = "gpio91"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio91"; + function = "cam_asc_mclk2"; + }; + + config { + pins = "gpio91"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio92"; + function = "cam_mclk"; + }; + + config { + pins = "gpio92"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio92"; + function = "cam_mclk"; + }; + + config { + pins = "gpio92"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio93"; + function = "cam_asc_mclk4"; + }; + + config { + pins = "gpio93"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio93"; + function = "cam_asc_mclk4"; + }; + + config { + pins = "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio94"; + function = "cam_mclk"; + }; + + config { + pins = "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio94"; + function = "cam_mclk"; + }; + + config { + pins = "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + + config { + pins = "gpio96"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + + config { + pins = "gpio96"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_active: cam_sensor_mclk7_active { + /* MCLK7 */ + mux { + pins = "gpio95"; + function = "cam_mclk"; + }; + + config { + pins = "gpio95"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_suspend: cam_sensor_mclk7_suspend { + /* MCLK7 */ + mux { + pins = "gpio95"; + function = "cam_mclk"; + }; + + config { + pins = "gpio95"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst7: cam_sensor_active_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst7: cam_sensor_suspend_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_ponv_front_active: cam_sensor_ponv_front_active { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_front_suspend: cam_sensor_ponv_front_suspend { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_ponv_rear_active: cam_sensor_ponv_rear_active { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_rear_suspend: cam_sensor_ponv_rear_suspend { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0858>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + cam_csiphy0: qcom,csiphy0@ada9000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0ada9000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xa9000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32000>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@adab000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xadab000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xab000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@adad000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xadad000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xad000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@adaf000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xadaf000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xaf000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@adb1000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xadb1000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xb1000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18600 37900>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@adb3000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + reg = <0xadb3000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xb3000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3I>; + csi-vdd-0p9-supply = <&L2I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 912000>; + rgltr-load-current = <0 18000 32200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac7b000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac7b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7b000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac7c000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac7c000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7c000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_scl3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_scl3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac7d000 { + cell-index = <2>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac7d000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7d000>; + interrupt-names = "CCI2"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_2_clk_src", + "cci_2_clk"; + clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_2_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>; + pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; + pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; + pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci2: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1C00 0x00>; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0xf 0xffe00000>; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + cam-smmu-label = "ife"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x00>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1800 0xC0>, + <&apps_smmu 0x1980 0x00>; + cam-smmu-label = "icp", "icp1"; + multiple-client-devices; + multiple-same-region-clients = "icp", "icp1"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0xf1400000 0xf 0x0ec00000>; + dma-coherent; + icp_iova_mem_map: iova-mem-map { + + iova-mem-region-shared1 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0x80c00000 */ + iova-region-start = <0x0 0x80c00000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-shared2 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xb9000000 */ + iova-region-start = <0x0 0xb9000000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region1 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80200000 */ + iova-region-start = <0x0 0x80200000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80300000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80200000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-region-fwuncached-region2 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80700000 */ + iova-region-start = <0x0 0x80700000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80800000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80700000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + + iova-mem-region-ipc-hwmutex { + iova-region-name = "ipc_hwmutex"; + iova-region-start = <0x0 0x80101000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x2>; + phy-addr = <0x1f4b000>; + }; + + iova-mem-region-global_cntr { + iova-region-name = "global_cntr"; + iova-region-start = <0x0 0x80102000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x4>; + phy-addr = <0xc220000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf1400000 */ + iova-region-start = <0x0 0xf1400000>; + /* Length: 0xf0ec00000 */ + iova-region-len = <0xf 0x0ec00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0x80000000 */ + iova-region-start = <0x0 0x80000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x37790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; + dma-coherent; + multiple-client-devices; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + qti,smmu-proxy-cb-id = ; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh", "cam_cesta"; + reg = <0xac04000 0x1000>, + <0x0ac62000 0x9200>, + <0x0ad90000 0x9000>, + <0xbbf0000 0x1f00>, + <0xadcb000 0x5000>; + reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000 0xadcb000>; + interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt"; + interrupts = , + ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "top-gdsc"; + top-gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_top_fast_ahb_clk", + "camnoc_rt_axi_clk_src", + "camnoc_rt_axi_clk", + "camnoc_nrt_axi_clk", + "cam_cc_drv_xo_clk", + "cam_cc_pll0", + "cam_cc_qdss_debug_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>, + <&camcc CAM_CC_PLL0>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_rt_axi_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = , + ; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <13 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", + "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", + "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", + "tpg13", "tpg14", "tpg15"; + enable-smart-qos; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x4830>; + priority-lut-high-offset = <0x4834>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x4A30>; + priority-lut-high-offset = <0x4A34>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <11>; + node-name = "level1-rt4-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x5230>; + priority-lut-high-offset = <0x5234>; + }; + + level1_rt3_rd: level1-rt3-rd { + cell-index = <12>; + node-name = "level1-rt3-cdm-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_wr: level1-nrt6-wr { + cell-index = <14>; + node-name = "level1-nrt6-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_rd: level1-nrt6-rd { + cell-index = <15>; + node-name = "level1-nrt6-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <16>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt5_rd: level1-nrt5-rd { + cell-index = <17>; + node-name = "level1-nrt5-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt4_rd: level1-nrt4-rd { + cell-index = <18>; + node-name = "level1-nrt4-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt3_wr: level1-nrt3-wr { + cell-index = <19>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt9_rd: level1-nrt9-rd { + cell-index = <20>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <21>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <22>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <23>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <24>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pdaf_linear_wr: ife0-pdaf-linear-wr { + cell-index = <27>; + node-name = "ife0-pdaf-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_linear_wr: ife1-pdaf-linear-wr { + cell-index = <28>; + node-name = "ife1-pdaf-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_linear_wr: ife2-pdaf-linear-wr { + cell-index = <29>; + node-name = "ife2-pdaf-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <30>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <31>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <32>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <33>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <34>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <35>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <36>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <37>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <38>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + + jpeg_enc1_all_wr: jpeg-enc1-all-wr { + cell-index = <39>; + node-name = "jpeg-enc1-all-wr"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_dma1_all_wr: jpeg-dma1-all-wr { + cell-index = <40>; + node-name = "jpeg-dma1-all-wr"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <41>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt5_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <42>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <43>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + + jpeg_enc1_all_rd: jpeg1-enc1-all-rd { + cell-index = <44>; + node-name = "jpeg-enc1-rd"; + client-name = "jpeg-enc1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + jpeg_dma1_all_rd: jpeg1-dma1-all-rd { + cell-index = <45>; + node-name = "jpeg-dma1-rd"; + client-name = "jpeg-dma1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <46>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <47>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <48>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <49>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <50>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <51>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm4_all_rd: rt-cdm4-all-rd { + cell-index = <52>; + node-name = "rt-cdm4-all-rd"; + client-name = "rt-cdm4"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <53>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + icp1_all_rd: icp1-all-rd { + cell-index = <54>; + node-name = "icp1-all-rd"; + client-name = "icp1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + ofe0_linear_wr: ofe0-linear-wr { + cell-index = <55>; + node-name = "ofe0-linear-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt2_wr>; + }; + + ofe0_in_rd: ofe0-in-rd { + cell-index = <56>; + node-name = "ofe0-in-rd"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt4_rd>; + }; + + ofe0_ubwc_wr: ofe0-ubwc-wr { + cell-index = <57>; + node-name = "ofe0-ubwc-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt3_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac7f000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0xac7f000 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x7f000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac80000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0xac80000 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x80000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac81000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0xac81000 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x81000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac82000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0xac82000 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x82000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm4@ac83000 { + cell-index = <4>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0xac83000 0x580>; + reg-names = "rt-cdm4"; + reg-cam-base = <0x83000>; + interrupt-names = "rt-cdm4"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife4"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <28>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "mc_tfe"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@ad26000 { + cell-index = <0>; + compatible = "qcom,csid980"; + reg-names = "csid"; + reg = <0xad27000 0x2b00>; + reg-cam-base = <0x27000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac86000{ + cell-index = <0>; + compatible = "qcom,mc_tfe980"; + reg-names = "ife", "cam_camnoc_rt"; + reg = <0xac86000 0x10000>, + <0x0ad90000 0x9000>; + reg-cam-base = <0x86000 0x19000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "gdsc", "tfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe0-supply = <&cam_cc_tfe_0_gdsc>; + clock-names = + "tfe_0_main_fast_ahb", + "tfe_0_clk_src", + "tfe_0_main_clk", + "cam_cc_camnoc_rt_tfe_0_main_clk", + "tfe_0_bayer_fast_ahb", + "tfe_0_bayer_clk", + "cam_cc_camnoc_rt_tfe_0_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK>; + clock-rates = + <0 360000000 0 0 0 0 0>, + <0 480000000 0 0 0 0 0>, + <0 630000000 0 0 0 0 0>, + <0 716000000 0 0 0 0 0>, + <0 833000000 0 0 0 0 0>, + <0 833000000 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_0_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <8 13 16 4>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@ad29000 { + cell-index = <1>; + compatible = "qcom,csid980"; + reg-names = "csid"; + reg = <0xad2a000 0x2b00>; + reg-cam-base = <0x2a000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac96000 { + cell-index = <1>; + compatible = "qcom,mc_tfe980"; + reg-names = "ife", "cam_camnoc_rt"; + reg = <0xac96000 0x10000>, + <0x0ad90000 0x9000>; + reg-cam-base = <0x96000 0x19000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "gdsc", "tfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe1-supply = <&cam_cc_tfe_1_gdsc>; + clock-names = + "tfe_1_main_fast_ahb", + "tfe_1_clk_src", + "tfe_1_main_clk", + "cam_cc_camnoc_rt_tfe_1_main_clk", + "tfe_1_bayer_fast_ahb", + "tfe_1_bayer_clk", + "cam_cc_camnoc_rt_tfe_1_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK>; + clock-rates = + <0 360000000 0 0 0 0 0>, + <0 480000000 0 0 0 0 0>, + <0 630000000 0 0 0 0 0>, + <0 716000000 0 0 0 0 0>, + <0 833000000 0 0 0 0 0>, + <0 833000000 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_1_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <9 14 17 5>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@ad2c000 { + cell-index = <2>; + compatible = "qcom,csid980"; + reg-names = "csid"; + reg = <0xad2d000 0x2b00>; + reg-cam-base = <0x2d000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@aca6000 { + cell-index = <2>; + compatible = "qcom,mc_tfe980"; + reg-names = "ife", "cam_camnoc_rt"; + reg = <0xaca6000 0x10000>, + <0x0ad90000 0x9000>; + reg-cam-base = <0xa6000 0x19000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "gdsc", "tfe2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe2-supply = <&cam_cc_tfe_2_gdsc>; + clock-names = + "tfe_2_main_fast_ahb", + "tfe_2_clk_src", + "tfe_2_main_clk", + "cam_cc_camnoc_rt_tfe_2_main_clk", + "tfe_2_bayer_fast_ahb", + "tfe_2_bayer_clk", + "cam_cc_camnoc_rt_tfe_2_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK>; + clock-rates = + <0 360000000 0 0 0 0 0>, + <0 480000000 0 0 0 0 0>, + <0 630000000 0 0 0 0 0>, + <0 716000000 0 0 0 0 0>, + <0 833000000 0 0 0 0 0>, + <0 833000000 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_2_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <10 12 18 6>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,csid-lite980"; + reg-names = "csid-lite"; + reg = <0xad6d000 0xa00>; + reg-cam-base = <0x6d000>; + rt-wrapper-base = <0x6c000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,vfe-lite980"; + reg-names = "ife-lite"; + reg = <0xad6d000 0x2800>; + reg-cam-base = <0x6d000>; + rt-wrapper-base = <0x6c000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <19>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@ad71000 { + cell-index = <4>; + compatible = "qcom,csid-lite980"; + reg-names = "csid-lite"; + reg = <0xad72000 0xa00>; + reg-cam-base = <0x72000>; + rt-wrapper-base = <0x6c000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@ad71000 { + cell-index = <4>; + compatible = "qcom,vfe-lite980"; + reg-names = "ife-lite"; + reg = <0xad72000 0x2800>; + reg-cam-base = <0x72000>; + rt-wrapper-base = <0x6c000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <20>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@ad8b000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xad8b000 0x400>, + <0xac04000 0x1000>; + reg-cam-base = <0x8b000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@ad8c000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xad8c000 0x400>, + <0xac04000 0x1000>; + reg-cam-base = <0x8c000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@ad8d000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xad8d000 0x400>, + <0xac04000 0x1000>; + reg-cam-base = <0x8d000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp0 { + compatible = "qcom,cam-icp0"; + cell-index = <0>; + compat-hw-name = "qcom,icp0", + "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + qcom,cam-icp1 { + compatible = "qcom,cam-icp1"; + cell-index = <1>; + compat-hw-name = "qcom,icp1", + "qcom,ofe"; + num-icp = <1>; + num-ofe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + cam_icp0: qcom,icp0@ac05000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0xac06000 0x1000>, + <0x0ac09000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x6000 0x9000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_0_AHB_CLK>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 300000000 0 0>, + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x3f083 0x3f083>; + ubwc-ipe-write-cfg = <0x1620F 0x1620F>; + qos-val = <0x808>; + fw-pas-id = <33>; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_icp1: qcom,icp1@ac150000 { + cell-index = <1>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0xac16000 0x1000>, + <0xac19000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x16000 0x19000>; + interrupt-names = "icp1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_2_mem>; + clock-names = + "icp_1_ahb_clk", + "icp_1_clk_src", + "icp_1_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_1_AHB_CLK>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 300000000 0 0>, + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_1_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_1"; + ubwc-ofe-fetch-cfg = <0x3f083 0x3f083>; + ubwc-ofe-write-cfg = <0x16209 0x16209>; + qos-val = <0x808>; + fw-pas-id = <50>; + cam_hw_pid = <10>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_camnoc_nrt_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>; + clock-rates = + <0 0 0 455000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 26 27>; + status = "ok"; + }; + + cam_ofe: qcom,ofe@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam-ofe"; + reg = <0xac2a000 0x18000>; + reg-names = "ofe0_top"; + reg-cam-base = <0x2a000>; + regulator-names = "ofe0-vdd"; + ofe0-vdd-supply = <&cam_cc_ofe_gdsc>; + clock-names = + "camnoc_nrt_ofe_anchor", + "camnoc_nrt_ofe_hdr", + "ofe_clk_src", + "ofe_main_clk", + "camnoc_nrt_ofe_main_clk", + "ofe_ahb_clk", + "ofe_anchor_clk", + "ofe_anchor_fast_ahb", + "ofe_hdr_fast_ahb", + "ofe_hdr_clk", + "ofe_main_fast_ahb"; + clocks = + <&camcc CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_OFE_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>, + <&camcc CAM_CC_OFE_AHB_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>; + clock-rates = + <0 0 338000000 0 0 0 0 0 0 0 0>, + <0 0 484000000 0 0 0 0 0 0 0 0>, + <0 0 586000000 0 0 0 0 0 0 0 0>, + <0 0 688000000 0 0 0 0 0 0 0 0>, + <0 0 841000000 0 0 0 0 0 0 0 0>, + <0 0 841000000 0 0 0 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ofe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <13 28 6>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc"; + reg = <0xac25000 0x1000>, + <0xac19000 0xac80>; + reg-cam-base = <0x2a000 0x19000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_0_clk", + "jpegenc_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@ac26000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc_nrt"; + reg = <0xac2b000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x2b000 0x62000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_0_clk", + "jpegdma_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +}; From d2536ff52251c023fee10f5794a3ab0ffd1ace36 Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Thu, 9 Nov 2023 14:50:13 -0800 Subject: [PATCH 038/274] ARM: dts: msm: Add interconnect path names for sun Add interconnect path names separately in camera bus nodes, so that they can be matched to interconnects in top level cpas node. This is done to ensure compatibility with of_icc_get during creation of path handles for ahb and axi voting. CRs-Fixed: 3656156 Change-Id: Ia8ed566eadab413c38755af82d70a50196ae5f06 Signed-off-by: Mukund Madhusudan Atre --- sun-camera.dtsi | 46 +++++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 2c3c2698..a8aed9c9 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1652,9 +1652,28 @@ camnoc-axi-clk-bw-margin-perc = <20>; domain-id = , ; - interconnect-names = "cam_ahb"; - interconnects =<&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_CAMERA_CFG>; + cam-icc-path-names = "cam_ahb"; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv", + "cam_sf_0", + "cam_sf_icp"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>, + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF + &mc_virt SLAVE_EBI1>; rpmh-bcm-info = <13 0x4 0x800 0 4>; cam-ahb-num-cases = <8>; cam-ahb-bw-KBps = @@ -1706,19 +1725,10 @@ ib-bw-voting-needed; rt-axi-port; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0", + cam-icc-path-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; - interconnects = - <&mmss_noc MASTER_CAMNOC_HF - &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 - &mc_virt SLAVE_EBI1_CAM_IFE_0>, - <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 - &mc_virt SLAVE_EBI1_CAM_IFE_1>, - <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 - &mc_virt SLAVE_EBI1_CAM_IFE_2>; }; }; @@ -1728,10 +1738,7 @@ traffic-merge-type = ; qcom,axi-port-mnoc { - interconnect-names = "cam_sf_0"; - interconnects = - <&mmss_noc MASTER_CAMNOC_SF - &mc_virt SLAVE_EBI1>; + cam-icc-path-names = "cam_sf_0"; }; }; @@ -1741,11 +1748,8 @@ traffic-merge-type = ; qcom,axi-port-mnoc { - interconnect-names = + cam-icc-path-names = "cam_sf_icp"; - interconnects = - <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF - &mc_virt SLAVE_EBI1>; }; }; }; From 6ba7e91eb695cc4aed141fb1b9cfbe45427f3543 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 9 Nov 2023 16:01:23 -0800 Subject: [PATCH 039/274] Snap for drop 11/09/2023 mainline 1093 LA.VENDOR.14.3.0.AU383 camera-devicetree: aae9aa1 Merge 'ARM: dts: msm: Add interconnect path names for sun' into camera-kernel.lnx.dev cf5c0c5 Merge 'ARM: dts: msm: Add devicetree changes for Sun dtsi' into camera-kernel.lnx.dev Change-Id: I518c47a913d1801542ac60e935ff87934cc4e74b Signed-off-by: hchintal From b5f23016f0d7d9a3bd8220a5a52f599eec28e327 Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 14 Nov 2023 13:45:38 -0800 Subject: [PATCH 040/274] Snap for drop 11/10/2023 mainline 1094 LA.VENDOR.14.3.0.AU383 Change-Id: I50ec8f6bb339530d55598cf1f54a89f7fc60bf09 Signed-off-by: hchintal From 60777a40a34fe3fa17eb456297868aaa78b08e7f Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 15 Nov 2023 15:22:56 -0800 Subject: [PATCH 041/274] Snap for drop 11/14/2023 mainline 1095 LA.VENDOR.14.3.0.AU383 Change-Id: Ic7a1a1520dbcd59d66c16269fa9272e135734eed Signed-off-by: hchintal From 98659863abc117a33d7a8282ef427ee247c8d120 Mon Sep 17 00:00:00 2001 From: Atiya Kailany Date: Wed, 15 Nov 2023 15:22:59 -0800 Subject: [PATCH 042/274] ARM: dts: msm: move hdk platform dtsi files to opensoure Move HDK platform dtsi files to appropriate project and adding required licensing. CRs-Fixed: 3599138 Change-Id: I35172180a9ce45cdc74b46fd3a181a5a5664f6e7 Signed-off-by: Atiya Kailany --- config/pineapple.mk | 1 + pineapple-camera-sensor-hdk.dts | 21 + pineapple-camera-sensor-hdk.dtsi | 765 +++++++++++++++++++++++++++++++ 3 files changed, 787 insertions(+) create mode 100644 pineapple-camera-sensor-hdk.dts create mode 100644 pineapple-camera-sensor-hdk.dtsi diff --git a/config/pineapple.mk b/config/pineapple.mk index 1e4e05b2..adbbe08f 100644 --- a/config/pineapple.mk +++ b/config/pineapple.mk @@ -2,4 +2,5 @@ dtbo-$(CONFIG_ARCH_PINEAPPLE) := pineapple-camera.dtbo dtbo-$(CONFIG_ARCH_PINEAPPLE) += pineapple-camera-v2.dtbo \ pineapple-camera-sensor-cdp.dtbo \ pineapple-camera-sensor-mtp.dtbo \ + pineapple-camera-sensor-hdk.dtbo \ pineapple-camera-sensor-qrd.dtbo diff --git a/pineapple-camera-sensor-hdk.dts b/pineapple-camera-sensor-hdk.dts new file mode 100644 index 00000000..9fca32e0 --- /dev/null +++ b/pineapple-camera-sensor-hdk.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "pineapple-camera-sensor-hdk.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Pineapple HDK"; + compatible = "qcom,pineapple-hdk", "qcom,pineapple", "qcom,hdk"; + qcom,msm-id = <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x1f 0>; +}; diff --git a/pineapple-camera-sensor-hdk.dtsi b/pineapple-camera-sensor-hdk.dtsi new file mode 100644 index 00000000..f82a13b0 --- /dev/null +++ b/pineapple-camera-sensor-hdk.dtsi @@ -0,0 +1,765 @@ + // SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_aon_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&S1C>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_v_custom1", + "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1200000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1352000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + actuator_triple_uw: qcom,actuator1 { + cell-index = <1>; + reg = <0x0E>; + compatible = "qcom,cam-i2c-actuator"; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + eeprom_aon_front: qcom,eeprom4 { + cell-index = <4>; + reg = <0x50>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + reg = <0x51>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + reg = <0x1A>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon_front>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000>; + rgltr-load-current = <6000 454000 0 77900 29400>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4 + &cam_sensor_ponv_front_active>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4 + &cam_sensor_ponv_front_suspend>; + gpios = <&tlmm 104 0>, + <&tlmm 7 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + reg = <0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 644000 0 77900 82900 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c2 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_i3c_triple_wide: qcom,actuator@c { + cell-index = <8>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + eeprom_i3c_wide: qcom,eeprom@50 { + cell-index = <8>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + ois_i3c_wide: qcom,ois@72 { + cell-index = <8>; + reg = <0x72 0x00 0x10>; + compatible = "qcom,cam-i2c-ois"; + cam_vio-supply = <&L3N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio" ,"cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 119000 0>; + status = "ok"; + }; + + qcom,cam-sensor@34,36007660000 { + cell-index = <8>; + reg = <0x34 0x360 0x07660000>; + assigned-address = <0xa>; + scl-hz = <4000000>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_i3c_triple_wide>; + eeprom-src = <&eeprom_i3c_wide>; + ois-src = <&ois_i3c_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L5M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_wide>; + actuator-src = <&actuator_i3c_triple_wide>; + led-flash-src = <&led_flash_aon_rear>; + cam_vio-supply = <&L3N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 102 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; From af1cd91c0134765d7991ccf21854b67941cb73c7 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Wed, 15 Nov 2023 23:38:18 -0800 Subject: [PATCH 043/274] Snap for drop 11/14/2023 mainline 1096 LA.VENDOR.14.3.0.AU383 camera-devicetree: 76d4ebb Merge 'ARM: dts: msm: move hdk platform dtsi files to opensoure' into camera-kernel.lnx.dev Change-Id: I30ac990c68ece93336b6937d7af5ee458527bf43 Signed-off-by: Savita Patted From d2056a0025e0c148963bdc904e91fac106795dda Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 16 Nov 2023 18:42:47 -0800 Subject: [PATCH 044/274] Snap for drop 11/16/2023 mainline 1098 LA.VENDOR.14.3.0.AU383 Change-Id: Id2e18d1978301b0e9f9cae15e9fd8c1b5a0dc97d Signed-off-by: hchintal From 4cfd998b246cb1a565ce062cf052c436b13af4dc Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 20 Nov 2023 12:48:39 -0800 Subject: [PATCH 045/274] Snap for drop 11/20/2023 mainline 1099 LA.VENDOR.14.3.0.AU383 Change-Id: I19fb19e1194b8dea05aaa55388068dcdbd019c0d Signed-off-by: hchintal From b2fa77def5b8cef2f236d0bf4645f582e14f2a87 Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Mon, 20 Nov 2023 17:41:33 -0800 Subject: [PATCH 046/274] ARM: dts: msm: Add cam sensor devicetree for sun Add device tree changes to support for sensor, eeprom, OIS & actuator for sun camera sensor. CRs-Fixed: 3656092 Change-Id: I97d5c4976f531b6cba48211feb676eae424e75e2 Signed-off-by: Lokesh Kumar Aakulu --- config/sun.mk | 4 + sun-camera-sensor-cdp.dts | 17 + sun-camera-sensor-cdp.dtsi | 776 ++++++++++++++++++++++++++++++++++++ sun-camera-sensor-mtp.dts | 17 + sun-camera-sensor-mtp.dtsi | 776 ++++++++++++++++++++++++++++++++++++ sun-camera-sensor-qrd.dts | 17 + sun-camera-sensor-qrd.dtsi | 776 ++++++++++++++++++++++++++++++++++++ sun-camera-sensor-rumi.dts | 17 + sun-camera-sensor-rumi.dtsi | 776 ++++++++++++++++++++++++++++++++++++ sun-camera.dts | 2 +- sun-camera.dtsi | 47 ++- 11 files changed, 3200 insertions(+), 25 deletions(-) create mode 100644 sun-camera-sensor-cdp.dts create mode 100644 sun-camera-sensor-cdp.dtsi create mode 100644 sun-camera-sensor-mtp.dts create mode 100644 sun-camera-sensor-mtp.dtsi create mode 100644 sun-camera-sensor-qrd.dts create mode 100644 sun-camera-sensor-qrd.dtsi create mode 100644 sun-camera-sensor-rumi.dts create mode 100644 sun-camera-sensor-rumi.dtsi diff --git a/config/sun.mk b/config/sun.mk index a9127f8e..020533b5 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -1 +1,5 @@ dtbo-$(CONFIG_ARCH_SUN) := sun-camera.dtbo +dtbo-$(CONFIG_ARCH_SUN) += sun-camera-sensor-mtp.dtbo \ + sun-camera-sensor-rumi.dtbo \ + sun-camera-sensor-cdp.dtbo \ + sun-camera-sensor-qrd.dtbo diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts new file mode 100644 index 00000000..e307ddf3 --- /dev/null +++ b/sun-camera-sensor-cdp.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "sun-camera-sensor-cdp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <1 0>, <21 0>; +}; diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..c52c909b --- /dev/null +++ b/sun-camera-sensor-cdp.dtsi @@ -0,0 +1,776 @@ +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_asc_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5M>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 220000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c3 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_UW_asc_rear: qcom,actuator@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_asc_rear: qcom,eeprom@50 { + cell-index = <6>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_i3c_UltraWide: qcom,eeprom@52 { + cell-index = <1>; + reg = <0x52 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@33,36008580000 { + cell-index = <1>; + reg = <0x33 0x360 0x08580000>; + assigned-address = <0xa>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_UltraWide>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_i3cSelect_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_i3cSelect_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_I3CSELECT"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_asc_rear>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_asc_rear>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts new file mode 100644 index 00000000..1fb05ebe --- /dev/null +++ b/sun-camera-sensor-mtp.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "sun-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun MTP"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <8 0>; +}; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..c52c909b --- /dev/null +++ b/sun-camera-sensor-mtp.dtsi @@ -0,0 +1,776 @@ +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_asc_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5M>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 220000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c3 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_UW_asc_rear: qcom,actuator@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_asc_rear: qcom,eeprom@50 { + cell-index = <6>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_i3c_UltraWide: qcom,eeprom@52 { + cell-index = <1>; + reg = <0x52 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@33,36008580000 { + cell-index = <1>; + reg = <0x33 0x360 0x08580000>; + assigned-address = <0xa>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_UltraWide>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_i3cSelect_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_i3cSelect_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_I3CSELECT"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_asc_rear>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_asc_rear>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts new file mode 100644 index 00000000..eb858650 --- /dev/null +++ b/sun-camera-sensor-qrd.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "sun-camera-sensor-qrd.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun QRD"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <11 0>; +}; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..c52c909b --- /dev/null +++ b/sun-camera-sensor-qrd.dtsi @@ -0,0 +1,776 @@ +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_asc_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5M>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 220000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c3 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_UW_asc_rear: qcom,actuator@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_asc_rear: qcom,eeprom@50 { + cell-index = <6>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_i3c_UltraWide: qcom,eeprom@52 { + cell-index = <1>; + reg = <0x52 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@33,36008580000 { + cell-index = <1>; + reg = <0x33 0x360 0x08580000>; + assigned-address = <0xa>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_UltraWide>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_i3cSelect_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_i3cSelect_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_I3CSELECT"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_asc_rear>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_asc_rear>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/sun-camera-sensor-rumi.dts b/sun-camera-sensor-rumi.dts new file mode 100644 index 00000000..e0190d72 --- /dev/null +++ b/sun-camera-sensor-rumi.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "sun-camera-sensor-rumi.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun RUMI"; + compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <15 0>; +}; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi new file mode 100644 index 00000000..c52c909b --- /dev/null +++ b/sun-camera-sensor-rumi.dtsi @@ -0,0 +1,776 @@ +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_asc_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5M>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 220000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c3 { + se-clock-frequency = <100000000>; + i3c-scl-hz = <12500000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_UW_asc_rear: qcom,actuator@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_asc_rear: qcom,eeprom@50 { + cell-index = <6>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_i3c_UltraWide: qcom,eeprom@52 { + cell-index = <1>; + reg = <0x52 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@33,36008580000 { + cell-index = <1>; + reg = <0x33 0x360 0x08580000>; + assigned-address = <0xa>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_UltraWide>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + i3c-target; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_i3cSelect_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_i3cSelect_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_I3CSELECT"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_asc_rear>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_asc_rear>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/sun-camera.dts b/sun-camera.dts index 2c762bf7..37e5bc68 100644 --- a/sun-camera.dts +++ b/sun-camera.dts @@ -12,5 +12,5 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <618 0x20000>; - qcom,board-id = <8 0>, <15 0>; + qcom,board-id = <0 0>; }; diff --git a/sun-camera.dtsi b/sun-camera.dtsi index a8aed9c9..790ad2fc 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -178,12 +178,12 @@ cci_i2c_scl3_active: cci_i2c_scl3_active { mux { - pins = "gpio12"; + pins = "gpio164"; function = "cci_i2c_scl3"; }; config { - pins = "gpio12"; + pins = "gpio164"; bias-pull-up; /* PULL UP*/ drive-strength = <2>; /* 2 MA */ qcom,i2c_pull; @@ -192,12 +192,12 @@ cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { mux { - pins = "gpio12"; + pins = "gpio111"; function = "cci_i2c_sda3"; }; config { - pins = "gpio12"; + pins = "gpio111"; bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ }; @@ -205,12 +205,12 @@ cci_i2c_sda3_active: cci_i2c_sda3_active { mux { - pins = "gpio13"; + pins = "gpio111"; function = "cci_i2c_sda3"; }; config { - pins = "gpio13"; + pins = "gpio111"; bias-pull-up; /* PULL UP*/ drive-strength = <2>; /* 2 MA */ qcom,i2c_pull; @@ -219,12 +219,12 @@ cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { mux { - pins = "gpio13"; + pins = "gpio164"; function = "cci_i2c_scl3"; }; config { - pins = "gpio13"; + pins = "gpio164"; bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ }; @@ -790,21 +790,21 @@ }; }; - cam_sensor_ponv_front_active: cam_sensor_ponv_front_active { - mux { - pins = "gpio6"; - function = "gpio"; - }; - - config { - pins = "gpio6"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - qcom,apps; - }; - }; - - cam_sensor_ponv_front_suspend: cam_sensor_ponv_front_suspend { + cam_sensor_i3cSelect_active: cam_sensor_i3cSelect_active { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_i3cSelect_suspend: cam_sensor_i3cSelect_suspend { mux { pins = "gpio6"; function = "gpio"; @@ -815,7 +815,6 @@ bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ output-low; - qcom,remote; }; }; From ea69728e84ee7d99544274239fde6310c8e18253 Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 20 Nov 2023 17:41:38 -0800 Subject: [PATCH 047/274] Snap for drop 11/20/2023 mainline 1100 LA.VENDOR.14.3.0.AU383 Camera-devicetree: eb7f043 Merge 'ARM: dts: msm: Add cam sensor devicetree for sun' into camera-kernel.lnx.dev Change-Id: I4e21cd72aa3416ba4325b908dfcbc1f365c96432 Signed-off-by: hchintal From 85cc560988a6beaa39fb98b3eed8ccde81abfc13 Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Wed, 29 Nov 2023 11:46:59 -0800 Subject: [PATCH 048/274] ARM: dts: msm: Correct MCLK on sun Master Clock handle needs to updated with bist handle and update correct vreg for csiphy. CRs-Fixed: 3656092 Change-Id: Ib2e8bb69ded52a07d0b9ef9ad9b25f892b1f2fbe Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dtsi | 32 ++++++++++---------- sun-camera-sensor-mtp.dtsi | 32 ++++++++++---------- sun-camera-sensor-qrd.dtsi | 32 ++++++++++---------- sun-camera-sensor-rumi.dtsi | 32 ++++++++++---------- sun-camera.dtsi | 58 ++++++++++++++++++------------------- 5 files changed, 93 insertions(+), 93 deletions(-) diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi index c52c909b..36894e32 100644 --- a/sun-camera-sensor-cdp.dtsi +++ b/sun-camera-sensor-cdp.dtsi @@ -123,7 +123,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -159,7 +159,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -195,7 +195,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -236,7 +236,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -280,7 +280,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -323,7 +323,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -374,7 +374,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -416,7 +416,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -455,7 +455,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -496,7 +496,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -537,7 +537,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -576,7 +576,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -634,7 +634,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -669,7 +669,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -718,7 +718,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_I3CSELECT"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -767,7 +767,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index c52c909b..36894e32 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -123,7 +123,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -159,7 +159,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -195,7 +195,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -236,7 +236,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -280,7 +280,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -323,7 +323,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -374,7 +374,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -416,7 +416,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -455,7 +455,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -496,7 +496,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -537,7 +537,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -576,7 +576,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -634,7 +634,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -669,7 +669,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -718,7 +718,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_I3CSELECT"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -767,7 +767,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi index c52c909b..36894e32 100644 --- a/sun-camera-sensor-qrd.dtsi +++ b/sun-camera-sensor-qrd.dtsi @@ -123,7 +123,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -159,7 +159,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -195,7 +195,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -236,7 +236,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -280,7 +280,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -323,7 +323,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -374,7 +374,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -416,7 +416,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -455,7 +455,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -496,7 +496,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -537,7 +537,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -576,7 +576,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -634,7 +634,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -669,7 +669,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -718,7 +718,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_I3CSELECT"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -767,7 +767,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi index c52c909b..36894e32 100644 --- a/sun-camera-sensor-rumi.dtsi +++ b/sun-camera-sensor-rumi.dtsi @@ -123,7 +123,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -159,7 +159,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -195,7 +195,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -236,7 +236,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -280,7 +280,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -323,7 +323,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -374,7 +374,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -416,7 +416,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -455,7 +455,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -496,7 +496,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -537,7 +537,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -576,7 +576,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET4"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -634,7 +634,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -669,7 +669,7 @@ gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -718,7 +718,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_I3CSELECT"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; @@ -767,7 +767,7 @@ gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY"; - clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 790ad2fc..4e0bc10c 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -881,12 +881,12 @@ interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <&cam_cc_titan_top_gdsc>; - csi-vdd-1p2-supply = <&L3I>; - csi-vdd-0p9-supply = <&L2I>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; - rgltr-max-voltage = <0 1200000 912000>; - rgltr-load-current = <0 18000 32000>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy0_clk", @@ -906,7 +906,7 @@ cam_csiphy1: qcom,csiphy1@adab000 { cell-index = <1>; - compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; reg = <0xadab000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xab000>; @@ -914,12 +914,12 @@ interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <&cam_cc_titan_top_gdsc>; - csi-vdd-1p2-supply = <&L3I>; - csi-vdd-0p9-supply = <&L2I>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; - rgltr-max-voltage = <0 1200000 912000>; - rgltr-load-current = <0 18000 32200>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy1_clk", @@ -939,7 +939,7 @@ cam_csiphy2: qcom,csiphy2@adad000 { cell-index = <2>; - compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; reg = <0xadad000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xad000>; @@ -947,12 +947,12 @@ interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <&cam_cc_titan_top_gdsc>; - csi-vdd-1p2-supply = <&L3I>; - csi-vdd-0p9-supply = <&L2I>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L3I>; rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; - rgltr-max-voltage = <0 1200000 912000>; - rgltr-load-current = <0 18000 32200>; + rgltr-max-voltage = <0 1256000 912000>; + rgltr-load-current = <0 6200 88200>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy2_clk", @@ -972,7 +972,7 @@ cam_csiphy3: qcom,csiphy3@adaf000 { cell-index = <3>; - compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; reg = <0xadaf000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xaf000>; @@ -980,12 +980,12 @@ interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <&cam_cc_titan_top_gdsc>; - csi-vdd-1p2-supply = <&L3I>; - csi-vdd-0p9-supply = <&L2I>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; - rgltr-max-voltage = <0 1200000 912000>; - rgltr-load-current = <0 18000 32200>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy3_clk", @@ -1005,7 +1005,7 @@ cam_csiphy4: qcom,csiphy4@adb1000 { cell-index = <4>; - compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; reg = <0xadb1000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xb1000>; @@ -1013,12 +1013,12 @@ interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <&cam_cc_titan_top_gdsc>; - csi-vdd-1p2-supply = <&L3I>; - csi-vdd-0p9-supply = <&L2I>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L3I>; rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; - rgltr-max-voltage = <0 1200000 912000>; - rgltr-load-current = <0 18600 37900>; + rgltr-max-voltage = <0 1256000 912000>; + rgltr-load-current = <0 6200 88200>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy4_clk", @@ -1038,7 +1038,7 @@ cam_csiphy5: qcom,csiphy5@adb3000 { cell-index = <5>; - compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; reg = <0xadb3000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xb3000>; @@ -1046,12 +1046,12 @@ interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <&cam_cc_titan_top_gdsc>; - csi-vdd-1p2-supply = <&L3I>; - csi-vdd-0p9-supply = <&L2I>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; - rgltr-max-voltage = <0 1200000 912000>; - rgltr-load-current = <0 18000 32200>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy5_clk", From 4e95c94660aa249c66a3ffbaae111f9ce59eec9f Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 29 Nov 2023 11:47:01 -0800 Subject: [PATCH 049/274] Snap for drop 11/22/2023 mainline 1101 LA.VENDOR.14.3.0.AU383 Camera-devicetree: ba129cd Merge 'ARM: dts: msm: Correct MCLK on sun' into camera-kernel.lnx.dev Change-Id: Ie4e247c2b13518827ad4fea29ae063abe498a4cc Signed-off-by: hchintal From ee1b0f86638ccbb91e8f83014487184336aa7d23 Mon Sep 17 00:00:00 2001 From: chengxue Date: Wed, 29 Nov 2023 11:47:03 -0800 Subject: [PATCH 050/274] ARM: dts: msm: Add cpas and csid register base for trustedvm Add cpas secure register base to set cdm/ife to secure on cpas, and add csid secure register base to set all csid path to trusted vm domain id. CRs-Fixed: 3653701 Change-Id: I4812490e4cb5c890fa286bb8d6d5d9321f22800b Signed-off-by: chengxue --- trustedvm-pineapple-camera.dtsi | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index 44889a9d..fd532198 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -1353,10 +1353,11 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top", "cam_camnoc"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_cpas_secure"; reg = <0xac13000 0x1000>, - <0xac19000 0xac80>; - reg-cam-base = <0x13000 0x19000>; + <0xac19000 0xac80>, + <0xac10000 0xFF0>; + reg-cam-base = <0x13000 0x19000 0x10000>; interrupt-names = "cpas_camnoc"; interrupts = ; camnoc-axi-min-ib-bw = <3000000000>; @@ -2377,10 +2378,11 @@ cam_csid0: qcom,csid0@acb7000 { cell-index = <0>; compatible = "qcom,csid880"; - reg-names = "csid", "csid_top"; + reg-names = "csid", "csid_top", "csid_sec"; reg = <0xacb8000 0xd00>, - <0xacb6000 0x1000>; - reg-cam-base = <0xb8000 0xb6000>; + <0xacb6000 0x1000>, + <0xacb7000 0x30>; + reg-cam-base = <0xb8000 0xb6000 0xb7000>; rt-wrapper-base = <0x62000>; interrupt-names = "csid0"; interrupts = ; @@ -2409,10 +2411,11 @@ cam_csid1: qcom,csid1@acb9000 { cell-index = <1>; compatible = "qcom,csid880"; - reg-names = "csid", "csid_top"; + reg-names = "csid", "csid_top", "csid_sec"; reg = <0xacba000 0xd00>, - <0xacb6000 0x1000>; - reg-cam-base = <0xba000 0xb6000>; + <0xacb6000 0x1000>, + <0xacb9000 0x30>; + reg-cam-base = <0xba000 0xb6000 0xb9000>; rt-wrapper-base = <0x62000>; interrupt-names = "csid1"; interrupts = ; @@ -2441,10 +2444,11 @@ cam_csid2: qcom,csid2@acbb000 { cell-index = <2>; compatible = "qcom,csid880"; - reg-names = "csid", "csid_top"; + reg-names = "csid", "csid_top", "csid_sec"; reg = <0xacbc000 0xd00>, - <0xacb6000 0x1000>; - reg-cam-base = <0xbc000 0xb6000>; + <0xacb6000 0x1000>, + <0xacbb000 0x30>; + reg-cam-base = <0xbc000 0xb6000 0xbb000>; rt-wrapper-base = <0x62000>; interrupt-names = "csid2"; interrupts = ; From d57904377fb60a19d2842237f54af9903e249e3f Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Wed, 29 Nov 2023 11:47:05 -0800 Subject: [PATCH 051/274] ARM: dts: msm: Adjust max volt for S7I regulator There are few consumers for S7I regulator like BT and Wlan where there min voltage was greater than 1.256v hence adjust max voltage to accommodate other clients. CRs-Fixed: 3656092 Change-Id: Ieedc7eb70b8f16c7c051dbe1ca7cd2d9841f6c4e Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dtsi | 8 ++++---- sun-camera-sensor-mtp.dtsi | 8 ++++---- sun-camera-sensor-qrd.dtsi | 8 ++++---- sun-camera-sensor-rumi.dtsi | 8 ++++---- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi index 36894e32..3c1fbd5c 100644 --- a/sun-camera-sensor-cdp.dtsi +++ b/sun-camera-sensor-cdp.dtsi @@ -107,7 +107,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -220,7 +220,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -439,7 +439,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -480,7 +480,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index 36894e32..3c1fbd5c 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -107,7 +107,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -220,7 +220,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -439,7 +439,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -480,7 +480,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi index 36894e32..3c1fbd5c 100644 --- a/sun-camera-sensor-qrd.dtsi +++ b/sun-camera-sensor-qrd.dtsi @@ -107,7 +107,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -220,7 +220,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -439,7 +439,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -480,7 +480,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi index 36894e32..3c1fbd5c 100644 --- a/sun-camera-sensor-rumi.dtsi +++ b/sun-camera-sensor-rumi.dtsi @@ -107,7 +107,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -220,7 +220,7 @@ "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -439,7 +439,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -480,7 +480,7 @@ "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; - rgltr-max-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; rgltr-load-current = <155000 680000 0 50000 30000 2500000>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; From e37e56ba227d07e3bf487a63675f479c249fb378 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Wed, 29 Nov 2023 11:47:06 -0800 Subject: [PATCH 052/274] Snap for drop 11/28/2023 mainline 1102 LA.VENDOR.14.3.0.AU383 d8c1b88 Merge 'ARM: dts: msm: Adjust max volt for S7I regulator' into camera-kernel.lnx.dev 8917bf4 Merge 'ARM: dts: msm: Add cpas and csid register base for trustedvm' into camera-kernel.lnx.dev Change-Id: Id432b4ff8517668fc7f33501bce359126b5794c0 Signed-off-by: Savita Patted From bc0fbbde26c593ca0091a9c166198053933fe3b7 Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 4 Dec 2023 17:42:19 -0800 Subject: [PATCH 053/274] Snap for drop 12/01/2023 mainline 1104 LA.VENDOR.14.3.0.AU383 Change-Id: I5035ff07a903c9e838d92a7ed89c9203ee4e760b Signed-off-by: hchintal From 600c92672a818d730eaebfa2994a8e0f7ca1b56c Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Mon, 4 Dec 2023 17:42:20 -0800 Subject: [PATCH 054/274] ARM: dts: msm: Fix axi constituent paths for ofe in sun dtsi Add missing paths in ofe camera bus nodes for axi bw voting. Fix incorrect path in ofe read node. CRs-Fixed: 3648309 Change-Id: I3e528c34e51102dc71f4b801aa7a9c4458a44f9e Signed-off-by: Mukund Madhusudan Atre --- sun-camera.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 4e0bc10c..0c2a3034 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -2394,7 +2394,8 @@ ; + CAM_CPAS_PATH_DATA_OFE_WR_IDEALRAW + CAM_CPAS_PATH_DATA_OFE_WR_STATS>; parent-node = <&level1_nrt2_wr>; }; @@ -2407,8 +2408,9 @@ traffic-transaction-type = ; constituent-paths = - ; + ; parent-node = <&level1_nrt4_rd>; }; @@ -2423,7 +2425,8 @@ constituent-paths = ; + CAM_CPAS_PATH_DATA_OFE_WR_IR + CAM_CPAS_PATH_DATA_OFE_WR_HDR_LTM>; parent-node = <&level1_nrt3_wr>; }; }; From 2f2c63ebb979ed79100daaa142db7231657a3df9 Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 4 Dec 2023 17:42:22 -0800 Subject: [PATCH 055/274] Snap for drop 12/04/2023 mainline 1105 LA.VENDOR.14.3.0.AU383 camera-devicetree: Merge 'ARM: dts: msm: Fix axi constituent paths for ofe in sun dtsi' into camera-kernel.lnx.dev Change-Id: Ib269ce7aec15b333b9139084961468bc8a22da4c Signed-off-by: hchintal From 85d3584ee4b3d97f347af0ca1b057cc7079badf3 Mon Sep 17 00:00:00 2001 From: Vijay Kumar Tumati Date: Tue, 5 Dec 2023 16:04:48 -0800 Subject: [PATCH 056/274] ARM: dts: msm: Add aon cam id for eligible sensor node Add aon camera ID for the sensor node so that we can turn on the mux and source MCLK for APPS. CRs-Fixed: 3656092 Change-Id: I04c26cc01255ed44e9db52c213d41685b7b12d0e Signed-off-by: Vijay Kumar Tumati Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dtsi | 1 + sun-camera-sensor-mtp.dtsi | 1 + sun-camera-sensor-qrd.dtsi | 1 + sun-camera-sensor-rumi.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi index 3c1fbd5c..94ddcf35 100644 --- a/sun-camera-sensor-cdp.dtsi +++ b/sun-camera-sensor-cdp.dtsi @@ -696,6 +696,7 @@ regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", "cam_vaf"; rgltr-cntrl-support; + aon-camera-id = ; i3c-target; rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index 3c1fbd5c..94ddcf35 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -696,6 +696,7 @@ regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", "cam_vaf"; rgltr-cntrl-support; + aon-camera-id = ; i3c-target; rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi index 3c1fbd5c..94ddcf35 100644 --- a/sun-camera-sensor-qrd.dtsi +++ b/sun-camera-sensor-qrd.dtsi @@ -696,6 +696,7 @@ regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", "cam_vaf"; rgltr-cntrl-support; + aon-camera-id = ; i3c-target; rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi index 3c1fbd5c..94ddcf35 100644 --- a/sun-camera-sensor-rumi.dtsi +++ b/sun-camera-sensor-rumi.dtsi @@ -696,6 +696,7 @@ regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", "cam_vaf"; rgltr-cntrl-support; + aon-camera-id = ; i3c-target; rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; From 46c6252c9bed2a53aa0ac13ac6e6aed501ee8940 Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 5 Dec 2023 16:04:51 -0800 Subject: [PATCH 057/274] Snap for drop 12/05/2023 mainline 1106 LA.VENDOR.14.3.0.AU383 camera-devicetree: 4df20ab Merge 'ARM: dts: msm: Add aon cam id for eligible sensor node' into camera-kernel.lnx.dev Change-Id: I4cbf1efe0e8b52a0114b4dd3313318c92f1a8b19 Signed-off-by: hchintal From 633c96e1f0dd784f99d8ed96fc2bd66aa43c4eeb Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Wed, 6 Dec 2023 17:19:12 -0800 Subject: [PATCH 058/274] ARM: dts: msm: Add camera dtsi files on sun qrd target Add dtsi support for sensor, eeprom & actuator for sun target. CRs-Fixed: 3660319 Change-Id: Ic31e9baadd39f5e7163f590c49c9316773e503af Signed-off-by: Pengfei Liu --- sun-camera-sensor-qrd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index eb858650..92c931ad 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun QRD"; compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; qcom,msm-id = <618 0x10000>, <618 0x20000>; - qcom,board-id = <11 0>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; }; From 7c53ee0421ebd5085ade5dac83c59304d9ce956e Mon Sep 17 00:00:00 2001 From: Suraj Dongre Date: Wed, 6 Dec 2023 17:19:14 -0800 Subject: [PATCH 059/274] ARM: dts: msm: Fix jpeg dma reset for sun Corrected register base start for jpeg dma on sun. This impacts jpeg dma reset. CRs-Fixed: 3648309 Change-Id: I43cbadac319f208cfb1f10158eb9d27e9c6eb734 Signed-off-by: Suraj Dongre Signed-off-by: Mukund Madhusudan Atre --- sun-camera.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 0c2a3034..23369829 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -3263,10 +3263,10 @@ cam_jpeg_enc0: qcom,jpegenc0@ac25000 { cell-index = <0>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw", "cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc_nrt"; reg = <0xac25000 0x1000>, - <0xac19000 0xac80>; - reg-cam-base = <0x2a000 0x19000>; + <0x0ac62000 0x9200>; + reg-cam-base = <0x25000 0x62000>; interrupt-names = "jpeg_enc0"; interrupts = ; regulator-names = "gdsc"; @@ -3294,9 +3294,9 @@ cell-index = <0>; compatible = "qcom,cam_jpeg_dma_780"; reg-names = "jpegdma_hw", "cam_camnoc_nrt"; - reg = <0xac2b000 0x1000>, + reg = <0xac26000 0x1000>, <0x0ac62000 0x9200>; - reg-cam-base = <0x2b000 0x62000>; + reg-cam-base = <0x26000 0x62000>; interrupt-names = "jpeg_dma0"; interrupts = ; regulator-names = "gdsc"; From 16de731f783793c7458cecae887a9ba0527fdaf2 Mon Sep 17 00:00:00 2001 From: hchintal Date: Wed, 6 Dec 2023 18:09:03 -0800 Subject: [PATCH 060/274] Snap for drop 12/06/2023 mainline 1107 LA.VENDOR.14.3.0.AU383 camera-devicetree: bb3d916 Merge 'ARM: dts: msm: Fix jpeg dma reset for sun' into camera-kernel.lnx.dev 9a8fd2a Merge 'ARM: dts: msm: Add camera dtsi files on sun qrd target' into camera-kernel.lnx.dev Change-Id: I2c2a4e23b23be4d6b7f30f2646fa27962385d219 Signed-off-by: hchintal From 99de4ed965f986ea9e11a3cb3c72af696f21cdd2 Mon Sep 17 00:00:00 2001 From: hchintal Date: Mon, 11 Dec 2023 15:54:22 -0800 Subject: [PATCH 061/274] Snap for drop 12/11/2023 mainline 1108 LA.VENDOR.14.3.0.AU383 Change-Id: I951a22ede7d2bb42b26c2ef9c10451a027b1a035 Signed-off-by: hchintal From 752fc4bd498d4519ebc1e49124991b9654cd5b70 Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 12 Dec 2023 15:27:02 -0800 Subject: [PATCH 062/274] Snap for drop 12/12/2023 mainline 1109 LA.VENDOR.14.3.0.AU383 Change-Id: Icb8817113058d3efc6d72751b1af10216403c4ed Signed-off-by: hchintal From 0136278f1f18878789e0f783ef55be921083681d Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Thu, 14 Dec 2023 11:11:12 -0800 Subject: [PATCH 063/274] ARM: dts: msm: Add new socid for sun camera Add APQ socid for sun camera device tree nodes including all targets. CRs-Fixed: 3656092 Change-Id: I8f217bbd57910cfdcdf8c9d3cb8ce2e6c4e18eb8 Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dts | 2 +- sun-camera-sensor-mtp.dts | 2 +- sun-camera-sensor-qrd.dts | 2 +- sun-camera.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index e307ddf3..9366d97e 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <1 0>, <21 0>; }; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 1fb05ebe..a2cdbbf3 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <8 0>; }; diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 92c931ad..95472e51 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Sun QRD"; compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; }; diff --git a/sun-camera.dts b/sun-camera.dts index 37e5bc68..80cb1c7f 100644 --- a/sun-camera.dts +++ b/sun-camera.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0 0>; }; From 3de907f313cd56685f78112e290f780a779c2a38 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 14 Dec 2023 11:11:14 -0800 Subject: [PATCH 064/274] Snap for drop 12/13/2023 mainline 1110 LA.VENDOR.14.3.0.AU383 camera-devicetree: a5d4867 Merge 'ARM: dts: msm: Add new socid for sun camera' into camera-kernel.lnx.dev Change-Id: I8d0f264d5fff97603a8d33e356099a750bbe5176 Signed-off-by: hchintal From 421853f929ce3b2666fea6c08ef01c571daf3a41 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 14 Dec 2023 20:07:57 -0800 Subject: [PATCH 065/274] Snap for drop 12/14/2023 mainline 1111 LA.VENDOR.14.3.0.AU383 Change-Id: Iefe2ad49e43e684a289a6a42e782a7d8ed52dc40 Signed-off-by: hchintal From 89c7bba2469ab9347e6cac99e113e6dc4086d386 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 18 Dec 2023 15:20:42 -0800 Subject: [PATCH 066/274] CAMX: Snap for drop 12/18/2023 mainline 1112 LA.VENDOR.14.3.0.AU383 Change-Id: I1a7eaf9c7d9e05dcb471f64c284e43c7f80454af Signed-off-by: Wasim Khan From 124d3ea763f973c039e8fdb40e45ba8a624affcb Mon Sep 17 00:00:00 2001 From: Haochen Yang Date: Wed, 20 Dec 2023 10:04:42 -0800 Subject: [PATCH 067/274] ARM: dts: msm: Fix ipe source clk rate for sun This change fixes ipe0 src clk rate and adds lowsvs_d1 level that is newly introduced. CRs-Fixed: 3677567 Change-Id: I8fe98582faec4ba17b192d467e522beb700ea93d Signed-off-by: Haochen Yang --- sun-camera.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 23369829..79537b72 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -3189,12 +3189,13 @@ <&camcc CAM_CC_IPE_PPS_CLK>, <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>; clock-rates = - <0 0 0 455000000 0 0 0>, + <0 0 0 332500000 0 0 0>, + <0 0 0 475000000 0 0 0>, <0 0 0 575000000 0 0 0>, <0 0 0 675000000 0 0 0>, <0 0 0 825000000 0 0 0>, <0 0 0 825000000 0 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + clock-cntl-level = "lowsvs_d1", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; From e8ede127369a0bd5655f1a62275a3e184e4679f4 Mon Sep 17 00:00:00 2001 From: Savita Patted Date: Wed, 20 Dec 2023 14:38:53 -0800 Subject: [PATCH 068/274] CAMX: Snap for drop 12/20/2023 mainline 1113 LA.VENDOR.14.3.0.AU383 561bb8a Merge 'ARM: dts: msm: Fix ipe source clk rate for sun' into camera-kernel.lnx.dev Change-Id: Idc021ea2e3daf80011d0ab06536544733beebfef Signed-off-by: Savita Patted From 1c63ed6b0ac5c75db88708f9127911a1280e3035 Mon Sep 17 00:00:00 2001 From: chengxue Date: Wed, 3 Jan 2024 12:33:13 -0800 Subject: [PATCH 069/274] ARM: dts: msm: Add properties for trustedvm camera heap sizes Add device and session heap size properties on trustedvm camera dtsi file. CRs-Fixed: 3661586 Change-Id: Ie83e5dd1951760d6d402118c5c5cf40557a5b6c1 Signed-off-by: chengxue --- bindings/msm-camera.txt | 33 ++++++++++++++++++++++++++++----- trustedvm-pineapple-camera.dtsi | 2 ++ 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/bindings/msm-camera.txt b/bindings/msm-camera.txt index cbbb136b..0ef6a6b7 100644 --- a/bindings/msm-camera.txt +++ b/bindings/msm-camera.txt @@ -3,14 +3,37 @@ Required properties: - compatible : - "qcom,cam-req-mgr", "qcom,cam-sync" -- qcom,sensor-manual-probe : specify if sensor probes at kernel boot time or user driven + +- cam-bypass-driver : + Usage: optional + Value type: + Definition: should contain drivers that required to bypass on camera, + including rgltr, rgltr_mode, clks, cesta, icc. + +- device-heap-size : + Usage: optional + Value type: + Definition: heap size used for camera internal allocations (exa - hfi memory) which stay forever. + +- session-heap-size : + Usage: optional + Value type: + Definition: heap size used for session based allocations. These allocations must be freed at the + end of session and the session-heap memory will be released to PVM at the end of usecase. Example: - qcom,cam-req-mgr { - compatible = "qcom,cam-req-mgr"; - qcom,sensor-manual-probe; - }; + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + cam-bypass-driver = <(CAM_BYPASS_RGLTR | + CAM_BYPASS_RGLTR_MODE | + CAM_BYPASS_CLKS | + CAM_BYPASS_CESTA | + CAM_BYPASS_ICC)>; + device-heap-size = <0x400000>; + session-heap-size = <0xC800000>; + status = "ok"; + }; qcom,cam-sync { compatible = "qcom,cam-sync"; diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index fd532198..ca15437e 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -862,6 +862,8 @@ CAM_BYPASS_CLKS | CAM_BYPASS_CESTA | CAM_BYPASS_ICC)>; + device-heap-size = <0x400000>; + session-heap-size = <0xC800000>; status = "ok"; }; From 6b7402cd329a31e65abcc75f4549305640a2287c Mon Sep 17 00:00:00 2001 From: Cherukuri Harika Date: Wed, 3 Jan 2024 12:33:15 -0800 Subject: [PATCH 070/274] CAMX: Snap for drop 12/28/2023 mainline 1114 LA.VENDOR.14.3.0.AU383 25bb0e4 Merge 'ARM: dts: msm: Add properties for trustedvm camera heap sizes' into camera-kernel.lnx.dev Change-Id: Ica5a80398499a3c1aeedf39d7f7a152f150f5e10 Signed-off-by: Cherukuri Harika From 7a4e0f90609bc3d0d5f8355409fa4444d17cd035 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Thu, 4 Jan 2024 13:29:23 -0800 Subject: [PATCH 071/274] ARM: dts: msm: Add v8 Power Grid DT support for sun Add device tree support for v8 Power Grid on MTP, CDP platforms for Sun SoC. CRs-Fixed: 3696784 Change-Id: Icefcf3981648cb08bd331691a64d3ca536f9c28c Signed-off-by: Soumen Ghosh --- sun-camera-sensor-cdp.dts | 2 +- sun-camera-sensor-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 9366d97e..8c06d501 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>; }; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index a2cdbbf3..5a655583 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>; + qcom,board-id = <8 0>, <0x20008 0>, <0x40008 0>, <0x50008 0>; }; From 7103074adc5ecaac5364d8e609d2fd8757fcc1aa Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Thu, 4 Jan 2024 13:29:25 -0800 Subject: [PATCH 072/274] ARM: dts: msm: change the voltage corner name soc util validation check was failing due to different name, to fix it change voltage corener label name from lowsvs_d1 to lowsvsd1. CRs-Fixed: 3696784 Change-Id: I5cb10f97292f09dea0fc0683fa60315c0cb5097d Signed-off-by: Soumen Ghosh --- sun-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 79537b72..69a79d94 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -3195,7 +3195,7 @@ <0 0 0 675000000 0 0 0>, <0 0 0 825000000 0 0 0>, <0 0 0 825000000 0 0 0>; - clock-cntl-level = "lowsvs_d1", "lowsvs", "svs", "svs_l1", "nominal", + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; From 31b69ddb9c95c41d436f2dd896a4c7af25378980 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 4 Jan 2024 13:29:26 -0800 Subject: [PATCH 073/274] Snap for drop 01/03/2023 mainline 1115 LA.VENDOR.14.3.0.AU383 camera-devicetree: edde84c Merge 'ARM: dts: msm: change the voltage corner name' into camera-kernel.lnx.dev 4013186 Merge 'ARM: dts: msm: Add v8 Power Grid DT support for sun' into camera-kernel.lnx.dev Change-Id: I7b0c0f22c68856787cbd737c4a5de66c546760e0 Signed-off-by: hchintal From d45664c4aa08a7cdf2612215b5e73f54ca7c7f9f Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 9 Jan 2024 12:23:12 -0800 Subject: [PATCH 074/274] CAMX: Snap for drop 01/09/2023 mainline 1119 LA.VENDOR.14.3.0.AU383 54a54d0 Merge 'ARM: dts: msm: Add cpas and cdm version parameter' into camera-kernel.lnx.dev 69821a7 Merge 'ARM: dts: msm: Add vmrm resource id parameter' into camera-kernel.lnx.dev Change-Id: I2d5bc9e18945d56aed2344cdb126b1fb94e1dd05 Signed-off-by: Wasim Khan From 1489fa7dc93e5f8c33f33b4161469dbe71217539 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 8 Jan 2024 17:17:27 -0800 Subject: [PATCH 075/274] CAMX: Snap for drop 01/04/2023 mainline 1116 LA.VENDOR.14.3.0.AU383 Change-Id: Ie12f21a5aeca0a9d9a53c20a378dee4cbcb560ce Signed-off-by: Wasim Khan From 9d8967c4be0825aea90fbedb6386a42ecb693067 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 8 Jan 2024 17:17:29 -0800 Subject: [PATCH 076/274] CAMX: Snap for drop 01/05/2023 mainline 1117 LA.VENDOR.14.3.0.AU383 Change-Id: Ifc9baecebd0775fca485f8bf01e16d030da4abfe Signed-off-by: Wasim Khan From 260448ed67b9f94046d637d793d9d8e93950dd81 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 8 Jan 2024 17:17:31 -0800 Subject: [PATCH 077/274] CAMX: Snap for drop 01/08/2023 mainline 1118 LA.VENDOR.14.3.0.AU383 Change-Id: I31c8f8aed8191622a03ec2f804941b7bc7af5f4c Signed-off-by: Wasim Khan From eb63869f6286f33faad20788b0e415a511c3e22a Mon Sep 17 00:00:00 2001 From: zhuo Date: Tue, 9 Jan 2024 15:03:32 -0800 Subject: [PATCH 078/274] ARM: dts: msm: Add vmrm resource id parameter Add vmrm resource id parameter for vmrm driver, parameter definition is memory label, memory tag, interrupt label. CRs-Fixed: 3683770 Change-Id: I3715f7fa32ff4ba1fd402c8294a40220678f287f Signed-off-by: zhuo --- bindings/msm-cam-cci.txt | 7 +++++ bindings/msm-cam-cdm.txt | 7 +++++ bindings/msm-cam-cpas.txt | 7 +++++ bindings/msm-cam-csiphy.txt | 7 +++++ bindings/msm-cam-eeprom.txt | 7 +++++ bindings/msm-cam-icp.txt | 10 +++++++ bindings/msm-cam-sfe.txt | 7 +++++ bindings/msm-cam-vfe.txt | 7 +++++ pineapple-camera-sensor-cdp.dtsi | 15 +++++++++++ pineapple-camera-sensor-mtp.dtsi | 15 +++++++++++ pineapple-camera-sensor-qrd.dtsi | 15 +++++++++++ pineapple-camera.dtsi | 31 ++++++++++++++++++++++ trustedvm-pineapple-camera-sensor-cdp.dtsi | 8 ++++++ trustedvm-pineapple-camera-sensor-mtp.dtsi | 8 ++++++ trustedvm-pineapple-camera-sensor-qrd.dtsi | 8 ++++++ trustedvm-pineapple-camera.dtsi | 28 +++++++++++++++++++ 16 files changed, 187 insertions(+) diff --git a/bindings/msm-cam-cci.txt b/bindings/msm-cam-cci.txt index f84f2c34..93f4eb02 100644 --- a/bindings/msm-cam-cci.txt +++ b/bindings/msm-cam-cci.txt @@ -126,6 +126,12 @@ First Level Node - CCI device Value type: Definition: should contain mmagic regulator used for mmagic clocks. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + ========================= CCI clock settings ========================= @@ -201,6 +207,7 @@ Example: pinctrl-1 = <&cci0_suspend>; pinctrl-2 = <&cci1_active>; pinctrl-3 = <&cci1_suspend>; + vmrm-resource-ids = <7 7 7>; i2c_freq_100Khz: qcom,i2c_standard_mode { hw-thigh = <78>; hw-tlow = <114>; diff --git a/bindings/msm-cam-cdm.txt b/bindings/msm-cam-cdm.txt index 0e188fec..4ecef893 100644 --- a/bindings/msm-cam-cdm.txt +++ b/bindings/msm-cam-cdm.txt @@ -150,6 +150,12 @@ to CDM interface node. Value type: Definition: Flag to indicate whether this is non real time device. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + Example: qcom,cpas-cdm0@ac48000 { cell-index = <0>; @@ -180,5 +186,6 @@ Example: config-fifo; fifo-depths = <64 0 0 0>; single-context-cdm; + vmrm-resource-ids = <12 12 12>; status = "ok"; }; diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index 179a4e76..e3d889e9 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -298,6 +298,12 @@ First Level Node - CAM CPAS device properties for those need to be included for this property to work. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + =================================================================== Third Level Node - CAMNOC Level nodes =================================================================== @@ -521,6 +527,7 @@ Example: rt-wr-lowstress-indicator-threshold = <0>; rt-wr-bw-ratio-scale-factor = <1>; enable-cam-drv; + vmrm-resource-ids = <10 10 10>; camera-bus-nodes { level3-nodes { level-index = <3>; diff --git a/bindings/msm-cam-csiphy.txt b/bindings/msm-cam-csiphy.txt index b6fc719d..dd6402e6 100644 --- a/bindings/msm-cam-csiphy.txt +++ b/bindings/msm-cam-csiphy.txt @@ -139,6 +139,12 @@ First Level Node - CSIPHY device Value type: Definition: List of 0 or 1 values indicating whether shared clk or not. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + Example: cam_csiphy0: qcom,csiphy0@ace4000 { @@ -171,5 +177,6 @@ cam_csiphy0: qcom,csiphy0@ace4000 { clock-cntl-level = "nominal"; clock-rates = <480000000 0 400000000 0>; + vmrm-resource-ids = <1 1 1>; status = "ok"; }; diff --git a/bindings/msm-cam-eeprom.txt b/bindings/msm-cam-eeprom.txt index d692385b..16485426 100644 --- a/bindings/msm-cam-eeprom.txt +++ b/bindings/msm-cam-eeprom.txt @@ -141,6 +141,12 @@ First Level Node - CAM EEPROM device Value type: Definition: List of clocks rates. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + Example: eeprom0: qcom,eeprom@0 { @@ -174,6 +180,7 @@ Example: clock-names = "cam_clk"; clock-cntl-level = "turbo"; clock-rates = <24000000>; + vmrm-resource-ids = <32 32>; }; ======================================================= diff --git a/bindings/msm-cam-icp.txt b/bindings/msm-cam-icp.txt index aada7cc7..021a8fe9 100644 --- a/bindings/msm-cam-icp.txt +++ b/bindings/msm-cam-icp.txt @@ -179,6 +179,12 @@ and name of firmware image. Value type: Definition: Flag to indicate whether this is non real time device. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + Examples: cam_a5: qcom,a5 { cell-index = <0>; @@ -258,6 +264,7 @@ cam_lx7: qcom,lx7 { ubwc-ipe-write-cfg = <0x161ef 0x1620f>; ubwc-bps-fetch-cfg = <0x707b 0x7083>; ubwc-bps-write-cfg = <0x161ef 0x1620f>; + vmrm-resource-ids = <29 29 29>; status = "ok"; }; @@ -299,6 +306,7 @@ cam_ipe0: qcom,ipe0@ac42000 { clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; + vmrm-resource-ids = <30 30 30>; status = "ok"; }; @@ -326,6 +334,7 @@ qcom,ipe1 { <0 0 0 0 600000000>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + vmrm-resource-ids = <31 31 31>; nrt-device; }; @@ -363,5 +372,6 @@ cam_bps: qcom,bps@ac2c000 { clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; + vmrm-resource-ids = <32 32 32>; status = "ok"; }; diff --git a/bindings/msm-cam-sfe.txt b/bindings/msm-cam-sfe.txt index 607bf02d..50bb675c 100644 --- a/bindings/msm-cam-sfe.txt +++ b/bindings/msm-cam-sfe.txt @@ -101,6 +101,12 @@ Required properties: Value type: Definition: Enable/Disable clk rate control. +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + Example: cam_sfe0: qcom,sfe0@ac9e000 { cell-index = <0>; @@ -133,5 +139,6 @@ cam_sfe0: qcom,sfe0@ac9e000 { src-clock-name = "sfe_clk_src"; scl-clk-names = "sfe_0_ahb"; clock-control-debugfs = "true"; + vmrm-resource-ids = <16 16 16>; status = "ok"; }; diff --git a/bindings/msm-cam-vfe.txt b/bindings/msm-cam-vfe.txt index cf3f7ffc..3f3e7000 100644 --- a/bindings/msm-cam-vfe.txt +++ b/bindings/msm-cam-vfe.txt @@ -132,6 +132,12 @@ Optional properties: Value type: Definition: HW unique Pid values +- vmrm-resource-ids + Usage: optional + Value type: + Definition: should specify vmrm resource id list order is mem label, + mem tag, irq1 label, irq2 label. + Example: cam_vfe0: qcom,ife0@ac62000 { cell-index = <0>; @@ -173,4 +179,5 @@ cam_vfe0: qcom,ife0@ac62000 { ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <16 28 20 8>; status = "ok"; + vmrm-resource-ids = <20 20 20>; }; diff --git a/pineapple-camera-sensor-cdp.dtsi b/pineapple-camera-sensor-cdp.dtsi index 24fd3fc1..e0f47524 100644 --- a/pineapple-camera-sensor-cdp.dtsi +++ b/pineapple-camera-sensor-cdp.dtsi @@ -110,6 +110,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <32 32>; status = "ok"; }; @@ -146,6 +147,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <33 33>; status = "ok"; }; @@ -187,6 +189,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <34 34>; status = "ok"; }; @@ -231,6 +234,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <35 35>; status = "ok"; }; @@ -282,6 +286,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <36 36>; status = "ok"; }; @@ -324,6 +329,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <37 37>; status = "ok"; }; @@ -363,6 +369,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <38 38>; status = "ok"; }; @@ -404,6 +411,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <39 39>; status = "ok"; }; }; @@ -460,6 +468,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <40 40>; status = "ok"; }; @@ -496,6 +505,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <41 41>; status = "ok"; }; @@ -542,6 +552,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <42 42>; status = "ok"; }; @@ -591,6 +602,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <43 43>; status = "ok"; }; }; @@ -649,6 +661,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <44 44>; status = "ok"; }; @@ -711,6 +724,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <45 45>; status = "ok"; }; @@ -760,6 +774,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <46 46>; status = "ok"; }; }; diff --git a/pineapple-camera-sensor-mtp.dtsi b/pineapple-camera-sensor-mtp.dtsi index 24fd3fc1..e0f47524 100644 --- a/pineapple-camera-sensor-mtp.dtsi +++ b/pineapple-camera-sensor-mtp.dtsi @@ -110,6 +110,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <32 32>; status = "ok"; }; @@ -146,6 +147,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <33 33>; status = "ok"; }; @@ -187,6 +189,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <34 34>; status = "ok"; }; @@ -231,6 +234,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <35 35>; status = "ok"; }; @@ -282,6 +286,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <36 36>; status = "ok"; }; @@ -324,6 +329,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <37 37>; status = "ok"; }; @@ -363,6 +369,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <38 38>; status = "ok"; }; @@ -404,6 +411,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <39 39>; status = "ok"; }; }; @@ -460,6 +468,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <40 40>; status = "ok"; }; @@ -496,6 +505,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <41 41>; status = "ok"; }; @@ -542,6 +552,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <42 42>; status = "ok"; }; @@ -591,6 +602,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <43 43>; status = "ok"; }; }; @@ -649,6 +661,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <44 44>; status = "ok"; }; @@ -711,6 +724,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <45 45>; status = "ok"; }; @@ -760,6 +774,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <46 46>; status = "ok"; }; }; diff --git a/pineapple-camera-sensor-qrd.dtsi b/pineapple-camera-sensor-qrd.dtsi index 24fd3fc1..e0f47524 100644 --- a/pineapple-camera-sensor-qrd.dtsi +++ b/pineapple-camera-sensor-qrd.dtsi @@ -110,6 +110,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <32 32>; status = "ok"; }; @@ -146,6 +147,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <33 33>; status = "ok"; }; @@ -187,6 +189,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <34 34>; status = "ok"; }; @@ -231,6 +234,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <35 35>; status = "ok"; }; @@ -282,6 +286,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <36 36>; status = "ok"; }; @@ -324,6 +329,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <37 37>; status = "ok"; }; @@ -363,6 +369,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <38 38>; status = "ok"; }; @@ -404,6 +411,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <39 39>; status = "ok"; }; }; @@ -460,6 +468,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <40 40>; status = "ok"; }; @@ -496,6 +505,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <41 41>; status = "ok"; }; @@ -542,6 +552,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <42 42>; status = "ok"; }; @@ -591,6 +602,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <43 43>; status = "ok"; }; }; @@ -649,6 +661,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <44 44>; status = "ok"; }; @@ -711,6 +724,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <45 45>; status = "ok"; }; @@ -760,6 +774,7 @@ clock-names = "cam_clk"; clock-cntl-level = "nominal"; clock-rates = <24000000>; + vmrm-resource-ids = <46 46>; status = "ok"; }; }; diff --git a/pineapple-camera.dtsi b/pineapple-camera.dtsi index ba0cd546..6ce7c0bc 100644 --- a/pineapple-camera.dtsi +++ b/pineapple-camera.dtsi @@ -907,6 +907,7 @@ clock-rates = <400000000 0 400000000 0>, <480000000 0 400000000 0>; + vmrm-resource-ids = <1 1 1>; status = "ok"; }; @@ -940,6 +941,7 @@ clock-rates = <400000000 0 400000000 0>, <480000000 0 400000000 0>; + vmrm-resource-ids = <2 2 2>; status = "ok"; }; @@ -973,6 +975,7 @@ clock-rates = <400000000 0 400000000 0>, <480000000 0 400000000 0>; + vmrm-resource-ids = <3 3 3>; status = "ok"; }; @@ -1006,6 +1009,7 @@ clock-rates = <400000000 0 400000000 0>, <480000000 0 400000000 0>; + vmrm-resource-ids = <4 4 4>; status = "ok"; }; @@ -1039,6 +1043,7 @@ clock-rates = <400000000 0 400000000 0>, <480000000 0 400000000 0>; + vmrm-resource-ids = <5 5 5>; status = "ok"; }; @@ -1072,6 +1077,7 @@ clock-rates = <400000000 0 400000000 0>, <480000000 0 400000000 0>; + vmrm-resource-ids = <6 6 6>; status = "ok"; }; @@ -1100,6 +1106,7 @@ pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + vmrm-resource-ids = <7 7 7>; status = "ok"; i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { @@ -1188,6 +1195,7 @@ pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + vmrm-resource-ids = <8 8 8>; status = "ok"; i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { @@ -1276,6 +1284,7 @@ pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + vmrm-resource-ids = <9 9 9>; status = "ok"; i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { @@ -1679,6 +1688,7 @@ rt-wr-highstress-indicator-threshold = <50>; rt-wr-lowstress-indicator-threshold = <0>; rt-wr-bw-ratio-scale-factor = <1>; + vmrm-resource-ids = <10 10 10>; status = "ok"; camera-bus-nodes { @@ -2515,6 +2525,7 @@ cam_hw_pid = <25>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <11 11 11>; status = "ok"; }; @@ -2540,6 +2551,7 @@ cam_hw_pid = <26>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <12 12 12>; status = "ok"; }; @@ -2565,6 +2577,7 @@ cam_hw_pid = <27>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <13 13 13>; status = "ok"; }; @@ -2590,6 +2603,7 @@ cam_hw_pid = <24>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <14 14 14>; status = "ok"; }; @@ -2615,6 +2629,7 @@ cam_hw_pid = <30>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <15 15 15>; status = "ok"; }; @@ -2657,6 +2672,7 @@ src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <11 0>; clock-control-debugfs = "true"; + vmrm-resource-ids = <16 16 16>; status = "ok"; }; @@ -2693,6 +2709,7 @@ src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <12 1>; clock-control-debugfs = "true"; + vmrm-resource-ids = <17 17 17>; status = "ok"; }; @@ -2729,6 +2746,7 @@ src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <13 2>; clock-control-debugfs = "true"; + vmrm-resource-ids = <18 18 18>; status = "ok"; }; @@ -2763,6 +2781,7 @@ "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <19 19 19>; status = "ok"; }; @@ -2801,6 +2820,7 @@ clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <16 20 24 8>; + vmrm-resource-ids = <20 20 20>; status = "ok"; }; @@ -2835,6 +2855,7 @@ "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <21 21 21>; status = "ok"; }; @@ -2873,6 +2894,7 @@ clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <17 21 25 9>; + vmrm-resource-ids = <22 22 22>; status = "ok"; }; @@ -2907,6 +2929,7 @@ "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <23 23 23>; status = "ok"; }; @@ -2945,6 +2968,7 @@ clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <18 22 26 10>; + vmrm-resource-ids = <24 24 24>; status = "ok"; }; @@ -2984,6 +3008,7 @@ "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <25 25 25>; status = "ok"; }; @@ -3024,6 +3049,7 @@ src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <27>; + vmrm-resource-ids = <26 26 26>; status = "ok"; }; @@ -3063,6 +3089,7 @@ "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <27 27 27>; status = "ok"; }; @@ -3103,6 +3130,7 @@ src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <28>; + vmrm-resource-ids = <28 28 28>; status = "ok"; }; @@ -3243,6 +3271,7 @@ ubwc-bps-write-cfg = <0x161ef 0x1620f>; qos-val = <0x808>; cam_hw_pid = <11>; + vmrm-resource-ids = <29 29 29>; status = "ok"; }; @@ -3282,6 +3311,7 @@ src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <15 14 13 31>; + vmrm-resource-ids = <30 30 30>; status = "ok"; }; @@ -3317,6 +3347,7 @@ src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <6 30>; + vmrm-resource-ids = <31 31 31>; status = "ok"; }; diff --git a/trustedvm-pineapple-camera-sensor-cdp.dtsi b/trustedvm-pineapple-camera-sensor-cdp.dtsi index 4a13f9e2..e6275269 100644 --- a/trustedvm-pineapple-camera-sensor-cdp.dtsi +++ b/trustedvm-pineapple-camera-sensor-cdp.dtsi @@ -67,6 +67,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; + vmrm-resource-ids = <32 32>; status = "ok"; }; @@ -87,6 +88,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; + vmrm-resource-ids = <33 33>; status = "ok"; }; @@ -112,6 +114,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = <0>; + vmrm-resource-ids = <34 34>; status = "ok"; }; @@ -140,6 +143,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; + vmrm-resource-ids = <35 35>; status = "ok"; }; @@ -170,6 +174,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; + vmrm-resource-ids = <36 36>; status = "ok"; }; @@ -197,6 +202,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; + vmrm-resource-ids = <37 37>; status = "ok"; }; @@ -220,6 +226,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; + vmrm-resource-ids = <38 38>; status = "ok"; }; @@ -245,6 +252,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; + vmrm-resource-ids = <39 39>; status = "ok"; }; }; diff --git a/trustedvm-pineapple-camera-sensor-mtp.dtsi b/trustedvm-pineapple-camera-sensor-mtp.dtsi index 4a13f9e2..e6275269 100644 --- a/trustedvm-pineapple-camera-sensor-mtp.dtsi +++ b/trustedvm-pineapple-camera-sensor-mtp.dtsi @@ -67,6 +67,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; + vmrm-resource-ids = <32 32>; status = "ok"; }; @@ -87,6 +88,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; + vmrm-resource-ids = <33 33>; status = "ok"; }; @@ -112,6 +114,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = <0>; + vmrm-resource-ids = <34 34>; status = "ok"; }; @@ -140,6 +143,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; + vmrm-resource-ids = <35 35>; status = "ok"; }; @@ -170,6 +174,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; + vmrm-resource-ids = <36 36>; status = "ok"; }; @@ -197,6 +202,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; + vmrm-resource-ids = <37 37>; status = "ok"; }; @@ -220,6 +226,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; + vmrm-resource-ids = <38 38>; status = "ok"; }; @@ -245,6 +252,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; + vmrm-resource-ids = <39 39>; status = "ok"; }; }; diff --git a/trustedvm-pineapple-camera-sensor-qrd.dtsi b/trustedvm-pineapple-camera-sensor-qrd.dtsi index 4a13f9e2..e6275269 100644 --- a/trustedvm-pineapple-camera-sensor-qrd.dtsi +++ b/trustedvm-pineapple-camera-sensor-qrd.dtsi @@ -67,6 +67,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = ; + vmrm-resource-ids = <32 32>; status = "ok"; }; @@ -87,6 +88,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; + vmrm-resource-ids = <33 33>; status = "ok"; }; @@ -112,6 +114,7 @@ gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; cci-master = <0>; + vmrm-resource-ids = <34 34>; status = "ok"; }; @@ -140,6 +143,7 @@ gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; cci-master = ; + vmrm-resource-ids = <35 35>; status = "ok"; }; @@ -170,6 +174,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; + vmrm-resource-ids = <36 36>; status = "ok"; }; @@ -197,6 +202,7 @@ gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3"; cci-master = ; + vmrm-resource-ids = <37 37>; status = "ok"; }; @@ -220,6 +226,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; + vmrm-resource-ids = <38 38>; status = "ok"; }; @@ -245,6 +252,7 @@ gpio-req-tbl-label = "CAMIF_MCLK5", "CAM_RESET5"; cci-master = ; + vmrm-resource-ids = <39 39>; status = "ok"; }; }; diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index ca15437e..7efe2a8c 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -889,6 +889,7 @@ interrupt-names = "CSIPHY0"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + vmrm-resource-ids = <1 1 1>; status = "ok"; }; @@ -901,6 +902,7 @@ interrupt-names = "CSIPHY1"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + vmrm-resource-ids = <2 2 2>; status = "ok"; }; @@ -913,6 +915,7 @@ interrupt-names = "CSIPHY2"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + vmrm-resource-ids = <3 3 3>; status = "ok"; }; @@ -925,6 +928,7 @@ interrupt-names = "CSIPHY3"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + vmrm-resource-ids = <4 4 4>; status = "ok"; }; @@ -937,6 +941,7 @@ interrupt-names = "CSIPHY4"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + vmrm-resource-ids = <5 5 5>; status = "ok"; }; @@ -949,6 +954,7 @@ interrupt-names = "CSIPHY5"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + vmrm-resource-ids = <6 6 6>; status = "ok"; }; @@ -969,6 +975,7 @@ pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + vmrm-resource-ids = <7 7 7>; status = "ok"; i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { @@ -1049,6 +1056,7 @@ pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + vmrm-resource-ids = <8 8 8>; status = "ok"; i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { @@ -1129,6 +1137,7 @@ pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + vmrm-resource-ids = <9 9 9>; status = "ok"; i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { @@ -1409,6 +1418,7 @@ rt-wr-highstress-indicator-threshold = <50>; rt-wr-lowstress-indicator-threshold = <0>; rt-wr-bw-ratio-scale-factor = <1>; + vmrm-resource-ids = <10 10 10>; status = "ok"; camera-bus-nodes { @@ -2243,6 +2253,7 @@ cam_hw_pid = <25>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <11 11 11>; status = "ok"; }; @@ -2263,6 +2274,7 @@ cam_hw_pid = <26>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <12 12 12>; status = "ok"; }; @@ -2283,6 +2295,7 @@ cam_hw_pid = <27>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <13 13 13>; status = "ok"; }; @@ -2303,6 +2316,7 @@ cam_hw_pid = <24>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <14 14 14>; status = "ok"; }; @@ -2323,6 +2337,7 @@ cam_hw_pid = <30>; cam-hw-mid = <0>; single-context-cdm; + vmrm-resource-ids = <15 15 15>; status = "ok"; }; @@ -2344,6 +2359,7 @@ regulator-names = "gdsc", "sfe0"; cam_hw_pid = <11 0>; clock-control-debugfs = "true"; + vmrm-resource-ids = <16 16 16>; status = "ok"; }; @@ -2359,6 +2375,7 @@ regulator-names = "gdsc", "sfe1"; cam_hw_pid = <12 1>; clock-control-debugfs = "true"; + vmrm-resource-ids = <17 17 17>; status = "ok"; }; @@ -2374,6 +2391,7 @@ regulator-names = "gdsc", "sfe2"; cam_hw_pid = <13 2>; clock-control-debugfs = "true"; + vmrm-resource-ids = <18 18 18>; status = "ok"; }; @@ -2391,6 +2409,7 @@ regulator-names = "gdsc"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <19 19 19>; status = "ok"; }; @@ -2407,6 +2426,7 @@ regulator-names = "gdsc", "ife0"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <16 20 24 8>; + vmrm-resource-ids = <20 20 20>; status = "ok"; }; @@ -2424,6 +2444,7 @@ regulator-names = "gdsc"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <21 21 21>; status = "ok"; }; @@ -2440,6 +2461,7 @@ regulator-names = "gdsc", "ife1"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <17 21 25 9>; + vmrm-resource-ids = <22 22 22>; status = "ok"; }; @@ -2457,6 +2479,7 @@ regulator-names = "gdsc"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <23 23 23>; status = "ok"; }; @@ -2473,6 +2496,7 @@ regulator-names = "gdsc", "ife2"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <18 22 26 10>; + vmrm-resource-ids = <24 24 24>; status = "ok"; }; @@ -2490,6 +2514,7 @@ "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <25 25 25>; status = "ok"; }; @@ -2506,6 +2531,7 @@ src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <27>; + vmrm-resource-ids = <26 26 26>; status = "ok"; }; @@ -2523,6 +2549,7 @@ "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; + vmrm-resource-ids = <27 27 27>; status = "ok"; }; @@ -2539,6 +2566,7 @@ src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <28>; + vmrm-resource-ids = <28 28 28>; status = "ok"; }; From 3731fcbe55be68097fa3ca43937416bdcb8bef53 Mon Sep 17 00:00:00 2001 From: zhuo Date: Tue, 9 Jan 2024 15:03:36 -0800 Subject: [PATCH 079/274] ARM: dts: msm: Add cpas and cdm version parameter Add cpas and cdm version parameter for probe stage using in tvm. CRs-Fixed: 3684173 Change-Id: I1668b603f7dbfab628ff8322f438f8019a6e3197 Signed-off-by: zhuo --- bindings/msm-cam-cdm.txt | 12 ++++++++++++ bindings/msm-cam-cpas.txt | 18 ++++++++++++++++++ trustedvm-pineapple-camera.dtsi | 13 +++++++++++++ 3 files changed, 43 insertions(+) diff --git a/bindings/msm-cam-cdm.txt b/bindings/msm-cam-cdm.txt index 4ecef893..7d9d7df7 100644 --- a/bindings/msm-cam-cdm.txt +++ b/bindings/msm-cam-cdm.txt @@ -156,6 +156,16 @@ to CDM interface node. Definition: should specify vmrm resource id list order is mem label, mem tag, irq1 label, irq2 label. +- override-cdm-family + Usage: optional + Value type: + Definition: should specify cdm family. + +- override-cdm-version + Usage: optional + Value type: + Definition: should specify cdm version. + Example: qcom,cpas-cdm0@ac48000 { cell-index = <0>; @@ -187,5 +197,7 @@ Example: fifo-depths = <64 0 0 0>; single-context-cdm; vmrm-resource-ids = <12 12 12>; + override-cdm-family = <0>; + override-cdm-version = <0x20020000>; status = "ok"; }; diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index e3d889e9..fa5d7c0d 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -304,6 +304,21 @@ First Level Node - CAM CPAS device Definition: should specify vmrm resource id list order is mem label, mem tag, irq1 label, irq2 label. +- cam-version + Usage: optional + Value type: + Definition: should specify camera version. + +- cpas-version + Usage: optional + Value type: + Definition: should specify cpas version. + +- camera-capability + Usage: optional + Value type: + Definition: should specify camera capability. + =================================================================== Third Level Node - CAMNOC Level nodes =================================================================== @@ -528,6 +543,9 @@ Example: rt-wr-bw-ratio-scale-factor = <1>; enable-cam-drv; vmrm-resource-ids = <10 10 10>; + cam-version = <0x80800>; + cpas-version = <0x10000000>; + camera-capability = <0x9fffedeb 0x8>; camera-bus-nodes { level3-nodes { level-index = <3>; diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index 7efe2a8c..0818592c 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -1419,6 +1419,9 @@ rt-wr-lowstress-indicator-threshold = <0>; rt-wr-bw-ratio-scale-factor = <1>; vmrm-resource-ids = <10 10 10>; + cam-version = <0x80800>; + cpas-version = <0x10000000>; + camera-capability = <0x9fffedeb 0x8>; status = "ok"; camera-bus-nodes { @@ -2254,6 +2257,8 @@ cam-hw-mid = <0>; single-context-cdm; vmrm-resource-ids = <11 11 11>; + override-cdm-family = <0>; + override-cdm-version = <0x20020000>; status = "ok"; }; @@ -2275,6 +2280,8 @@ cam-hw-mid = <0>; single-context-cdm; vmrm-resource-ids = <12 12 12>; + override-cdm-family = <0>; + override-cdm-version = <0x20020000>; status = "ok"; }; @@ -2296,6 +2303,8 @@ cam-hw-mid = <0>; single-context-cdm; vmrm-resource-ids = <13 13 13>; + override-cdm-family = <0>; + override-cdm-version = <0x20020000>; status = "ok"; }; @@ -2317,6 +2326,8 @@ cam-hw-mid = <0>; single-context-cdm; vmrm-resource-ids = <14 14 14>; + override-cdm-family = <0>; + override-cdm-version = <0x20020000>; status = "ok"; }; @@ -2338,6 +2349,8 @@ cam-hw-mid = <0>; single-context-cdm; vmrm-resource-ids = <15 15 15>; + override-cdm-family = <0>; + override-cdm-version = <0x20020000>; status = "ok"; }; From 3cecbc1b09c9b807cc209f94c70b2c9c37472d5b Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 12 Jan 2024 11:16:29 -0800 Subject: [PATCH 080/274] CAMX: Snap for drop 01/10/2023 mainline 1120 LA.VENDOR.14.3.0.AU383 Change-Id: I7a3ac8d4c095b43072336cf222ecd14799d0549e Signed-off-by: Wasim Khan From 45fdf32375451ec09a8d023bb98207a7183bac8f Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 12 Jan 2024 11:16:31 -0800 Subject: [PATCH 081/274] CAMX: Snap for drop 01/11/2023 mainline 1121 LA.VENDOR.14.3.0.AU383 Change-Id: I9533c1a75e221f442d95ff656bc1ac7c4948878b Signed-off-by: Wasim Khan From 8b7623a845c766a2204f89fcf6d90c0abf46bf7a Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 12 Jan 2024 18:32:56 -0800 Subject: [PATCH 082/274] CAMX: Snap for drop 01/12/2023 mainline 1122 LA.VENDOR.14.3.0.AU383 Change-Id: Icb241f4115cc658cf052ff192e0fbb562ec357b7 Signed-off-by: Wasim Khan From 6fdb0bb346018e3a2e7267a2cd39464aff4ab001 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Wed, 17 Jan 2024 12:52:23 -0800 Subject: [PATCH 083/274] ARM: dts: msm: replace existing use of iommu-dma-addr-pool with iommu-addresses 'qcom,iommu-dma-addr-pool' describe the addresses which a device CAN use 'iommu-addresses' describes the addresses it CANNOT use. CRs-Fixed: 3697699 Change-Id: Ia0253d015073423ac50d0b4ace91278c7120f91f Signed-off-by: Soumen Ghosh --- sun-camera.dtsi | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 69a79d94..bd0431a4 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1342,14 +1342,18 @@ #address-cells = <2>; #size-cells = <2>; - msm_cam_smmu_ife { + msm_cam_smmu_ife: msm_cam_smmu_ife { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x1C00 0x00>; - qcom,iommu-dma-addr-pool = <0x0 0x100000 0xf 0xffe00000>; qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; cam-smmu-label = "ife"; multiple-client-devices; + memory-region = <&cam_smmu_ife_resv_region>; + cam_smmu_ife_resv_region: cam_smmu_ife_resv_region { + iommu-addresses = <&msm_cam_smmu_ife 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_ife 0xf 0xfff00000 0x0 0x100000>; + }; ife_iova_mem_map: iova-mem-map { /* IO region is approximately 64 GB */ iova-mem-region-io { @@ -1366,13 +1370,17 @@ }; }; - msm_cam_smmu_jpeg { + msm_cam_smmu_jpeg: msm_cam_smmu_jpeg { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x18A0 0x00>; cam-smmu-label = "jpeg"; qcom,iommu-faults = "stall-disable", "non-fatal"; - qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; dma-coherent; + memory-region = <&cam_smmu_jpeg_resv_region>; + cam_smmu_jpeg_resv_region: cam_smmu_jpeg_resv_region { + iommu-addresses = <&msm_cam_smmu_jpeg 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_jpeg 0x0 0xfff00000 0xf 0x00100000>; + }; jpeg_iova_mem_map: iova-mem-map { /* IO region is approximately 4.0 GB */ iova-mem-region-io { @@ -1389,7 +1397,7 @@ }; }; - msm_cam_smmu_icp { + msm_cam_smmu_icp: msm_cam_smmu_icp { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x1820 0x00>, <&apps_smmu 0x1800 0xC0>, @@ -1398,10 +1406,12 @@ multiple-client-devices; multiple-same-region-clients = "icp", "icp1"; qcom,iommu-faults = "stall-disable", "non-fatal"; - qcom,iommu-dma-addr-pool = <0x0 0xf1400000 0xf 0x0ec00000>; dma-coherent; + memory-region = <&cam_smmu_icp_resv_region>; + cam_smmu_icp_resv_region: cam_smmu_icp_resv_region { + iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1400000>; + }; icp_iova_mem_map: iova-mem-map { - iova-mem-region-shared1 { /* Shared region is ~900MB long */ iova-region-name = "shared"; @@ -1545,14 +1555,18 @@ }; }; - msm_cam_smmu_cdm { + msm_cam_smmu_cdm: msm_cam_smmu_cdm { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x1860 0x00>; cam-smmu-label = "rt-cdm"; qcom,iommu-faults = "stall-disable", "non-fatal"; - qcom,iommu-dma-addr-pool = <0x0 0x100000 0x0 0xffe00000>; dma-coherent; multiple-client-devices; + memory-region = <&cam_smmu_cdm_resv_region>; + cam_smmu_cdm_resv_region: cam_smmu_cdm_resv_region { + iommu-addresses = <&msm_cam_smmu_cdm 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_cdm 0x0 0xfff00000 0xf 0x00100000>; + }; rt_cdm_iova_mem_map: iova-mem-map { iova-mem-region-io { iova-region-name = "io"; From a0ca2e3d690b2b2e6e099f368d38195ed15f8bb0 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 17 Jan 2024 12:52:26 -0800 Subject: [PATCH 084/274] CAMX: Snap for drop 01/17/2023 mainline 1123 LA.VENDOR.14.3.0.AU383 56ec132 Merge 'ARM: dts: msm: replace existing use of iommu-dma-addr-pool with iommu-addresses' into camera-kernel.lnx.dev Change-Id: I8e7f2ad14aaadabde0d29b622ef1b5b9c911aedb Signed-off-by: Wasim Khan From 5b20977be3abcaf4db9b227617dcd9655b2fdff0 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Thu, 18 Jan 2024 10:59:24 -0800 Subject: [PATCH 085/274] CAMX: Snap for drop 01/17/2023 mainline 1124 LA.VENDOR.14.3.0.AU383 Change-Id: I195d6fc5af8e414daa0bb309cd1a5281ea46e5bb Signed-off-by: Wasim Khan From 500aae6a753212e52231c479cf15b31208bb056f Mon Sep 17 00:00:00 2001 From: zhuo Date: Fri, 19 Jan 2024 11:45:40 -0800 Subject: [PATCH 086/274] ARM: dts: msm: Add cci gpio resources for vmrm Due to cci is using pinctrl, but it does not define gpio info and vmrm is checking the gpios parameter to get the device use gpio info, so need to add gpio for cci. And due to cci is using pinctrl, so there is not need to define gpio-req-tbl-num for cci, so cci just has gpios without gpio-req-tbl-num. This commit add gpio_for_vmrm_purpose to identify the scene and add gpio resources. CRs-Fixed: 3685452 Change-Id: I75450c252c62899c6b563745ef3322520595a8eb Signed-off-by: zhuo --- bindings/msm-cam-cci.txt | 10 ++++++++++ pineapple-camera.dtsi | 15 +++++++++++++++ trustedvm-pineapple-camera.dtsi | 15 +++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/bindings/msm-cam-cci.txt b/bindings/msm-cam-cci.txt index 93f4eb02..7865e3fe 100644 --- a/bindings/msm-cam-cci.txt +++ b/bindings/msm-cam-cci.txt @@ -132,6 +132,16 @@ First Level Node - CCI device Definition: should specify vmrm resource id list order is mem label, mem tag, irq1 label, irq2 label. +- gpios + Usage: required when enable vmrm + Value type: + Definition: should specify the gpios to be used for the cci. + +- gpio_for_vmrm_purpose + Usage: required when enable vmrm + Value type: + Definition: A boolean flag to indicate the gpios is only for vmrm. + ========================= CCI clock settings ========================= diff --git a/pineapple-camera.dtsi b/pineapple-camera.dtsi index 6ce7c0bc..4987d266 100644 --- a/pineapple-camera.dtsi +++ b/pineapple-camera.dtsi @@ -1106,6 +1106,11 @@ pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + gpios = <&tlmm 113 0>, + <&tlmm 114 0>, + <&tlmm 115 0>, + <&tlmm 116 0>; + gpio_for_vmrm_purpose; vmrm-resource-ids = <7 7 7>; status = "ok"; @@ -1195,6 +1200,11 @@ pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + gpios = <&tlmm 12 0>, + <&tlmm 13 0>, + <&tlmm 117 0>, + <&tlmm 118 0>; + gpio_for_vmrm_purpose; vmrm-resource-ids = <8 8 8>; status = "ok"; @@ -1284,6 +1294,11 @@ pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + gpios = <&tlmm 112 0>, + <&tlmm 153 0>, + <&tlmm 119 0>, + <&tlmm 120 0>; + gpio_for_vmrm_purpose; vmrm-resource-ids = <9 9 9>; status = "ok"; diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index 0818592c..0de83a2b 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -975,6 +975,11 @@ pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + gpios = <&tlmm 113 0>, + <&tlmm 114 0>, + <&tlmm 115 0>, + <&tlmm 116 0>; + gpio_for_vmrm_purpose; vmrm-resource-ids = <7 7 7>; status = "ok"; @@ -1056,6 +1061,11 @@ pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + gpios = <&tlmm 12 0>, + <&tlmm 13 0>, + <&tlmm 117 0>, + <&tlmm 118 0>; + gpio_for_vmrm_purpose; vmrm-resource-ids = <8 8 8>; status = "ok"; @@ -1137,6 +1147,11 @@ pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + gpios = <&tlmm 112 0>, + <&tlmm 153 0>, + <&tlmm 119 0>, + <&tlmm 120 0>; + gpio_for_vmrm_purpose; vmrm-resource-ids = <9 9 9>; status = "ok"; From 416c68e20c99e7196626137034ea50e8816289d9 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 19 Jan 2024 11:45:43 -0800 Subject: [PATCH 087/274] CAMX: Snap for drop 01/19/2024 mainline 1125 LA.VENDOR.14.3.0.AU383 e5efbce Merge 'ARM: dts: msm: Add cci gpio resources for vmrm' into camera-kernel.lnx.dev Change-Id: Ie3211aaf2d4e5ff38f61ac732aac590974205c00 Signed-off-by: Wasim Khan From 6ad372930a1f364aa06cf541126ad881983d07c2 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 22 Jan 2024 23:02:46 -0800 Subject: [PATCH 088/274] CAMX: Snap for drop 01/19/2024 mainline 1126 LA.VENDOR.14.3.0.AU383 Change-Id: I535e1d7ac6490a1e7b4692bcfd358860f456e8f6 Signed-off-by: Wasim Khan From 87c11766e6aa86f73fc76fa50c358276102c0d55 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 22 Jan 2024 23:02:49 -0800 Subject: [PATCH 089/274] CAMX: Snap for drop 01/22/2024 mainline 1127 LA.VENDOR.14.3.0.AU383 Change-Id: I693534fe4b5e810f9a1ca68e85c73540c3c47484 Signed-off-by: Wasim Khan From 2e175888366b86605209a1fa91c2ee8d750999af Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 24 Jan 2024 16:22:55 -0800 Subject: [PATCH 090/274] CAMX: Snap for drop 01/23/2024 mainline 1128 LA.VENDOR.14.3.0.AU383 Change-Id: I07e304ed217598d824fe6cc7d94a4a2001603995 Signed-off-by: Wasim Khan From d3779834b748b9444e0a3f85bbfa675d34b3a228 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 26 Jan 2024 20:27:40 -0800 Subject: [PATCH 091/274] CAMX: Snap for drop 01/24/2024 mainline 1129 LA.VENDOR.14.3.0.AU383 Change-Id: Ibe305cd70853f8bab416e58b4c43b834a9111b76 Signed-off-by: Wasim Khan From 1b76bb417a92466216a1c923ad43b2370ecd261d Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 26 Jan 2024 20:27:42 -0800 Subject: [PATCH 092/274] CAMX: Snap for drop 01/26/2024 mainline 1130 LA.VENDOR.14.3.0.AU383 Change-Id: I88e153b31b2352a3e03dad30a5a973bc5754716f Signed-off-by: Wasim Khan From 51741d2256b3fbc8f651fa2a4a0231c1235b574f Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Mon, 29 Jan 2024 22:42:29 -0800 Subject: [PATCH 093/274] ARM: dts: msm: adding the 2MB iova region for LLCC To make accessible LLCC register address space by ICP FW, we need to map the 2MB. LLCC register region in SMMU context bank. CRs-Fixed: 3701263 Change-Id: I2a95b918facef5fa9c9d47a7f04151f4779995c7 Signed-off-by: Soumen Ghosh --- sun-camera.dtsi | 46 ++++++++++++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index bd0431a4..d961853c 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1409,14 +1409,14 @@ dma-coherent; memory-region = <&cam_smmu_icp_resv_region>; cam_smmu_icp_resv_region: cam_smmu_icp_resv_region { - iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1400000>; + iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1600000>; }; icp_iova_mem_map: iova-mem-map { iova-mem-region-shared1 { /* Shared region is ~900MB long */ iova-region-name = "shared"; - /* Start address: 0x80c00000 */ - iova-region-start = <0x0 0x80c00000>; + /* Start address: 0x80e00000 */ + iova-region-start = <0x0 0x80e00000>; /* Length: 0x38400000 */ iova-region-len = <0x0 0x38400000>; iova-region-id = <0x1>; @@ -1426,8 +1426,8 @@ iova-mem-region-shared2 { /* Shared region is ~900MB long */ iova-region-name = "shared"; - /* Start address: 0xb9000000 */ - iova-region-start = <0x0 0xb9000000>; + /* Start address: 0xb9200000 */ + iova-region-start = <0x0 0xb9200000>; /* Length: 0x38400000 */ iova-region-len = <0x0 0x38400000>; iova-region-id = <0x1>; @@ -1437,8 +1437,8 @@ iova-mem-region-fwuncached-region1 { /* FW uncached region is 5 MB long */ iova-region-name = "fw_uncached"; - /* Start address: 0x80200000 */ - iova-region-start = <0x0 0x80200000>; + /* Start address: 0x80400000 */ + iova-region-start = <0x0 0x80400000>; /* Length: 0x500000 */ iova-region-len = <0x0 0x500000>; iova-region-id = <0x6>; @@ -1448,7 +1448,7 @@ /* Used for HFI queues/sec heap */ iova-mem-region-generic-region { iova-region-name = "icp_hfi"; - iova-region-start = <0x0 0x80300000>; + iova-region-start = <0x0 0x80500000>; /* Length: 0x200000 */ iova-region-len = <0x0 0x200000>; iova-region-id = <0x0>; @@ -1457,7 +1457,7 @@ /* Global Sync Memory for IPC */ iova-mem-region-global-sync-region { iova-region-name = "global_sync"; - iova-region-start = <0x0 0x80200000>; + iova-region-start = <0x0 0x80400000>; /* Length: 0x100000 */ iova-region-len = <0x0 0x100000>; iova-region-id = <0x3>; @@ -1468,8 +1468,8 @@ iova-mem-region-fwuncached-region2 { /* FW uncached region is 5 MB long */ iova-region-name = "fw_uncached"; - /* Start address: 0x80700000 */ - iova-region-start = <0x0 0x80700000>; + /* Start address: 0x80900000 */ + iova-region-start = <0x0 0x80900000>; /* Length: 0x500000 */ iova-region-len = <0x0 0x500000>; iova-region-id = <0x6>; @@ -1479,7 +1479,7 @@ /* Used for HFI queues/sec heap */ iova-mem-region-generic-region { iova-region-name = "icp_hfi"; - iova-region-start = <0x0 0x80800000>; + iova-region-start = <0x0 0x80a00000>; /* Length: 0x200000 */ iova-region-len = <0x0 0x200000>; iova-region-id = <0x0>; @@ -1488,7 +1488,7 @@ /* Global Sync Memory for IPC */ iova-mem-region-global-sync-region { iova-region-name = "global_sync"; - iova-region-start = <0x0 0x80700000>; + iova-region-start = <0x0 0x80900000>; /* Length: 0x100000 */ iova-region-len = <0x0 0x100000>; iova-region-id = <0x3>; @@ -1500,7 +1500,7 @@ /* Device region is appropriate 1MB */ iova-region-name = "device"; iova-region-start = <0x0 0x80100000>; - iova-region-len = <0x0 0x100000>; + iova-region-len = <0x0 0x300000>; iova-region-id = <0x7>; subregion_support; status = "ok"; @@ -1528,15 +1528,22 @@ iova-region-id = <0x4>; phy-addr = <0xc220000>; }; + iova-mem-region-llcc-register { + iova-region-name = "llcc-register"; + iova-region-start = <0x0 0x80103000>; + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x5>; + phy-addr = <0x26C00000>; + }; }; iova-mem-region-io { /* IO region is approximately 60 GB */ iova-region-name = "io"; - /* Start address: 0xf1400000 */ - iova-region-start = <0x0 0xf1400000>; - /* Length: 0xf0ec00000 */ - iova-region-len = <0xf 0x0ec00000>; + /* Start address: 0xf1600000 */ + iova-region-start = <0x0 0xf1600000>; + /* Length: 0xf0ea00000 */ + iova-region-len = <0xf 0x0ea00000>; iova-region-id = <0x3>; status = "ok"; }; @@ -1715,6 +1722,9 @@ "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; + sys-cache-uids = <71 72 73 74 75>; + sys-cache-concur = <1 1 1 0 0>; enable-smart-qos; rt-wr-priority-min = <4>; rt-wr-priority-max = <5>; From 473eba5bb000eef6715ef86671b09d9f9f3c4730 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 29 Jan 2024 22:42:31 -0800 Subject: [PATCH 094/274] CAMX: Snap for drop 01/29/2024 mainline 1131 LA.VENDOR.14.3.0.AU383 1e54ab9 Merge 'ARM: dts: msm: adding the 2MB iova region for LLCC' into camera-kernel.lnx.dev Change-Id: I1d7f28bfbcb173ffa43dc4072c8e2af6f851056d Signed-off-by: Wasim Khan From ce67122b983700995ec40a94f51e64a448423bf3 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 30 Jan 2024 20:26:18 -0800 Subject: [PATCH 095/274] CAMX: Snap for drop 01/30/2024 mainline 1132 LA.VENDOR.15.4.0.AU225 Change-Id: I459746221e511431f386a93c52cb1877f7e6185f Signed-off-by: Wasim Khan From 429887648a1cfbc32e7f728952a3657f23c20520 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 2 Feb 2024 11:31:40 -0800 Subject: [PATCH 096/274] CAMX: Snap for drop 01/31/2024 mainline 1133 LA.VENDOR.15.4.0.AU225 Change-Id: If6769637275efa5eed82c77394a8e0e66b249327 Signed-off-by: Wasim Khan From 2895a84af50766140e0f8f2a367087320afc6a1a Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 2 Feb 2024 11:31:43 -0800 Subject: [PATCH 097/274] CAMX: Snap for drop 02/02/2024 mainline 1134 LA.VENDOR.15.4.0.AU225 Change-Id: I4c78dc9358684a55fa8f9cd3cf4fe6581e29d64f Signed-off-by: Wasim Khan From c9a1485371ee78f980fb259f44ea2d92f1f670a2 Mon Sep 17 00:00:00 2001 From: zhuo Date: Tue, 6 Feb 2024 11:15:54 -0800 Subject: [PATCH 098/274] ARM: dts: msm: Add vmrm device in camera pvm and tvm Add vmrm device in camera pvm and tvm. Default enable in tvm and disable in pvm. Also add bypass register access in tvm boot up. CRs-Fixed: 3711691 Change-Id: Iadc1b8eb669d991b7f855d7ad5decdf22b3707bb Signed-off-by: zhuo --- pineapple-camera.dtsi | 6 ++++++ trustedvm-pineapple-camera.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/pineapple-camera.dtsi b/pineapple-camera.dtsi index 4987d266..b2fc4393 100644 --- a/pineapple-camera.dtsi +++ b/pineapple-camera.dtsi @@ -877,6 +877,12 @@ status = "disabled"; }; + qcom,cam-vmrm { + compatible = "qcom,cam-vmrm"; + vmid = ; + status = "disabled"; + }; + cam_csiphy0: qcom,csiphy0@ace4000 { cell-index = <0>; compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index 0de83a2b..de791bd2 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -880,6 +880,13 @@ status = "disabled"; }; + qcom,cam-vmrm { + compatible = "qcom,cam-vmrm"; + vmid = ; + no_register_read_on_bind; + status = "ok"; + }; + cam_csiphy0: qcom,csiphy0@ace4000 { cell-index = <0>; compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; From 6d4acda8ba5f35977062e44a2ae58fc601878296 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 6 Feb 2024 11:15:56 -0800 Subject: [PATCH 099/274] CAMX: Snap for drop 02/05/2024 mainline 1135 LA.VENDOR.15.4.0.AU225 4f3fbf0 Merge 'ARM: dts: msm: Add vmrm device in camera pvm and tvm' into camera-kernel.lnx.dev Change-Id: I2140c362f4a0d14b171dee03651f3eac61c157ba Signed-off-by: Wasim Khan From fb42273515d8b5a88596f6ed4556fae6920461c1 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 7 Feb 2024 11:00:02 -0800 Subject: [PATCH 100/274] CAMX: Snap for drop 02/06/2024 mainline 1136 LA.VENDOR.15.4.0.AU231 Change-Id: I86a9bdf616eb4ea10ee5dae23a512e391f0d412e Signed-off-by: Wasim Khan From 001e79b9eb7857747c9077ed87efe6640fb0c52f Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Thu, 8 Feb 2024 16:43:57 -0800 Subject: [PATCH 101/274] CAMX: Snap for drop 02/08/2024 mainline 1137 LA.VENDOR.15.4.0.AU231 Change-Id: I99e2e09451bf98081df1761d399b265d67e889fd Signed-off-by: Wasim Khan From 7e1660cc9bf602f92c702ba754fbe5783c4e6b46 Mon Sep 17 00:00:00 2001 From: Atiya Kailany Date: Tue, 13 Feb 2024 11:45:01 -0800 Subject: [PATCH 102/274] ARM: dts: msm: Adding lowsvsd1 vote level to device tree This change adds lowsvsd1 vote level along with corresponding rates to the device tree. CRs-Fixed: 3678245 Change-Id: I99bc0cc781edfe9b31aedc1970d0d1b5ccded7d7 Signed-off-by: Atiya Kailany --- sun-camera.dtsi | 87 +++++++++++++++++++++++++++++-------------------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index d961853c..bd25bf59 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -897,8 +897,9 @@ <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI0PHYTIMER_CLK>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; clock-rates = + <266666667 0 400000000 0>, <400000000 0 400000000 0>, <480000000 0 400000000 0>; status = "ok"; @@ -930,8 +931,9 @@ <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI1PHYTIMER_CLK>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; clock-rates = + <266666667 0 400000000 0>, <400000000 0 400000000 0>, <480000000 0 400000000 0>; status = "ok"; @@ -963,8 +965,9 @@ <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI2PHYTIMER_CLK>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; clock-rates = + <266666667 0 400000000 0>, <400000000 0 400000000 0>, <480000000 0 400000000 0>; status = "ok"; @@ -996,8 +999,9 @@ <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI3PHYTIMER_CLK>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; clock-rates = + <266666667 0 400000000 0>, <400000000 0 400000000 0>, <480000000 0 400000000 0>; status = "ok"; @@ -1029,8 +1033,9 @@ <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI4PHYTIMER_CLK>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; clock-rates = + <266666667 0 400000000 0>, <400000000 0 400000000 0>, <480000000 0 400000000 0>; status = "ok"; @@ -1062,8 +1067,9 @@ <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, <&camcc CAM_CC_CSI5PHYTIMER_CLK>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; clock-rates = + <266666667 0 400000000 0>, <400000000 0 400000000 0>, <480000000 0 400000000 0>; status = "ok"; @@ -1083,8 +1089,8 @@ "cci_0_clk"; clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, <&camcc CAM_CC_CCI_0_CLK>; - clock-rates = <37500000 0>; - clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = ; pctrl-map-names = "m0", "m1"; @@ -1171,8 +1177,8 @@ "cci_1_clk"; clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, <&camcc CAM_CC_CCI_1_CLK>; - clock-rates = <37500000 0>; - clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = ; pctrl-map-names = "m0", "m1"; @@ -1259,8 +1265,8 @@ "cci_2_clk"; clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, <&camcc CAM_CC_CCI_2_CLK>; - clock-rates = <37500000 0>; - clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = ; pctrl-map-names = "m0", "m1"; @@ -1647,14 +1653,15 @@ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; clock-rates = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 56470588 0 0 0 213333333 0 200000000 0 0 0 0 0>, <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; - clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", - "nominal", "nominal_l1", "turbo"; + clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_rt_axi_clk_src"; domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; @@ -2620,13 +2627,14 @@ <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; clock-rates = + <266666667 0 0>, <400000000 0 0>, <480000000 0 0>, <480000000 0 0>, <480000000 0 0>, <480000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; @@ -2662,7 +2670,7 @@ <&camcc CAM_CC_TFE_0_BAYER_CLK>, <&camcc CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK>; clock-rates = - <0 360000000 0 0 0 0 0>, + <0 360280000 0 0 0 0 0>, <0 480000000 0 0 0 0 0>, <0 630000000 0 0 0 0 0>, <0 716000000 0 0 0 0 0>, @@ -2698,13 +2706,14 @@ <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; clock-rates = + <266666667 0 0>, <400000000 0 0>, <480000000 0 0>, <480000000 0 0>, <480000000 0 0>, <480000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; @@ -2740,7 +2749,7 @@ <&camcc CAM_CC_TFE_1_BAYER_CLK>, <&camcc CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK>; clock-rates = - <0 360000000 0 0 0 0 0>, + <0 360280000 0 0 0 0 0>, <0 480000000 0 0 0 0 0>, <0 630000000 0 0 0 0 0>, <0 716000000 0 0 0 0 0>, @@ -2776,13 +2785,14 @@ <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; clock-rates = + <266666667 0 0>, <400000000 0 0>, <480000000 0 0>, <480000000 0 0>, <480000000 0 0>, <480000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; @@ -2818,7 +2828,7 @@ <&camcc CAM_CC_TFE_2_BAYER_CLK>, <&camcc CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK>; clock-rates = - <0 360000000 0 0 0 0 0>, + <0 360280000 0 0 0 0 0>, <0 480000000 0 0 0 0 0>, <0 630000000 0 0 0 0 0>, <0 716000000 0 0 0 0 0>, @@ -2860,13 +2870,14 @@ <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; clock-rates = + <0 266666667 0 0 0 0>, <0 400000000 0 0 0 0>, <0 480000000 0 0 0 0>, <0 480000000 0 0 0 0>, <0 480000000 0 0 0 0>, <0 480000000 0 0 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; @@ -2899,13 +2910,14 @@ <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; clock-rates = + <0 0 0 266666667 0 0>, <0 0 0 400000000 0 0>, <0 0 0 480000000 0 0>, <0 0 0 480000000 0 0>, <0 0 0 480000000 0 0>, <0 0 0 480000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <19>; @@ -2939,13 +2951,14 @@ <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; clock-rates = + <0 266666667 0 0 0 0>, <0 400000000 0 0 0 0>, <0 480000000 0 0 0 0>, <0 480000000 0 0 0 0>, <0 480000000 0 0 0 0>, <0 480000000 0 0 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; @@ -2978,13 +2991,14 @@ <&camcc CAM_CC_IFE_LITE_CLK>, <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; clock-rates = + <0 0 0 266666667 0 0>, <0 0 0 400000000 0 0>, <0 0 0 480000000 0 0>, <0 0 0 480000000 0 0>, <0 0 0 480000000 0 0>, <0 0 0 480000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", - "turbo"; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <20>; @@ -3011,9 +3025,10 @@ <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; clock-rates = + <266666667 0>, <400000000 0>, <480000000 0>; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; }; @@ -3038,9 +3053,10 @@ <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; clock-rates = + <266666667 0>, <400000000 0>, <480000000 0>; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; }; @@ -3065,9 +3081,10 @@ <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; clock-rates = + <266666667 0>, <400000000 0>, <480000000 0>; - clock-cntl-level = "lowsvs", "nominal"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; }; @@ -3261,7 +3278,7 @@ <&camcc CAM_CC_OFE_HDR_CLK>, <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>; clock-rates = - <0 0 338000000 0 0 0 0 0 0 0 0>, + <0 0 338800000 0 0 0 0 0 0 0 0>, <0 0 484000000 0 0 0 0 0 0 0 0>, <0 0 586000000 0 0 0 0 0 0 0 0>, <0 0 688000000 0 0 0 0 0 0 0 0>, From 8574e854d2e3ddb1644c698396fb889656b874eb Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 13 Feb 2024 11:45:06 -0800 Subject: [PATCH 103/274] CAMX: Snap for drop 02/12/2024 mainline 1138 LA.VENDOR.15.4.0.AU231 a13cdd3 Merge 'ARM: dts: msm: Adding lowsvsd1 vote level to device tree' into camera-kernel.lnx.dev Change-Id: I377546fcbc4070f6cebe5f0b071786b2d69933d7 Signed-off-by: Wasim Khan From f53fe7d7e0058b27e9823c82e62f273147b9b516 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 14 Feb 2024 12:38:08 -0800 Subject: [PATCH 104/274] CAMX: Snap for drop 02/13/2024 mainline 1139 LA.VENDOR.15.4.0.AU240 Change-Id: Id42129a7c728e11f02da98837cacd91796f9ec6e Signed-off-by: Wasim Khan From ee79b6b788450ebc763d32fb57ac0fedc0f7a6f7 Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Fri, 16 Feb 2024 10:19:15 -0800 Subject: [PATCH 105/274] ARM: dts: msm: Add new board-id for camera sensor Add new Board id information for multiple types of RCM devices. CRs-Fixed: 3731095 Change-Id: I8576e29d754b949851636ed9e6fc5555b55a3a03 Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 8c06d501..fcd2b648 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; }; From 096530b3fd973806afe03c685f05a5cb4e7938df Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 14 Feb 2024 18:55:49 -0800 Subject: [PATCH 106/274] CAMX: Snap for drop 02/14/2024 mainline 1140 LA.VENDOR.15.4.0.AU240 Change-Id: I79d510e44ed2fcfab6069daa1996ecd38fa21625 Signed-off-by: Wasim Khan From 38ca4495b47c2ea39f52bc4b14811047bd104eba Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 16 Feb 2024 11:01:57 -0800 Subject: [PATCH 107/274] CAMX: Snap for drop 02/15/2024 mainline 1141 LA.VENDOR.15.4.0.AU240 Change-Id: I18accf07db427f8e43eda5a6b5023ab41286878a Signed-off-by: Wasim Khan From 9b30bf7e2186cb514f61ed3ffaff749321dba312 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 21 Feb 2024 11:42:58 -0800 Subject: [PATCH 108/274] CAMX: Snap for drop 02/20/2024 mainline 1142 LA.VENDOR.15.4.0.AU240 Change-Id: I2a0d8d04933efed741d0d2811d3980987e408979 Signed-off-by: Wasim Khan From fd496fbcb5b0ef28b214fc0654503e01646eaa4b Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 21 Feb 2024 22:58:06 -0800 Subject: [PATCH 109/274] CAMX: Snap for drop 02/21/2024 mainline 1143 LA.VENDOR.15.4.0.AU248 17f0dce Merge 'ARM: dts: msm: Add new board-id for camera sensor' into camera-kernel.lnx.dev Change-Id: I35cd58d3dbac34c42446b4dc8f89bd0f80300133 Signed-off-by: Wasim Khan From 117b2efb1c72d919a9f8ca10fc1b2a795c931296 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Thu, 22 Feb 2024 15:44:37 -0800 Subject: [PATCH 110/274] CAMX: Snap for drop 02/22/2024 mainline 1144 LA.VENDOR.15.4.0.AU248 Change-Id: Ia81eb7039c455be457e5971381e3dfb98332702d Signed-off-by: Wasim Khan From ff78043d9c56fed323af2beff71692f22eba3094 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 23 Feb 2024 12:18:03 -0800 Subject: [PATCH 111/274] CAMX: Snap for drop 02/23/2024 mainline 1145 LA.VENDOR.15.4.0.AU248 Change-Id: I96a92aa53723053fbc2b5530c079069fbb2592df Signed-off-by: Wasim Khan From 9a9c2befa6a0c08bd4fcd3317bd3a46d22a6713a Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Tue, 6 Feb 2024 22:37:55 -0800 Subject: [PATCH 112/274] ARM: dts: msm: Add new board-id for camera sensor Add new Board id information for multiple types of RCM devices. CRs-Fixed: 3731095 Change-Id: I8576e29d754b949851636ed9e6fc5555b55a3a03 Signed-off-by: Lokesh Kumar Aakulu Signed-off-by: Vaishali Gupta --- sun-camera-sensor-cdp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 8c06d501..fcd2b648 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; }; From 813ef2af29fabed6171b0fadf905e229f7b31783 Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Fri, 23 Feb 2024 11:12:28 -0800 Subject: [PATCH 113/274] ARM: dts: msm: Add new updated board-id for camera Add new Board id information for multiple types of CDP and MTP devices. CRs-Fixed: 3731095 Change-Id: If717a9525fd4e7c0becd72b3b4e41099be930ab7 Signed-off-by: Lokesh Kumar Aakulu Signed-off-by: Vaishali Gupta --- sun-camera-sensor-cdp.dts | 2 +- sun-camera-sensor-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index fcd2b648..6d140a32 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; }; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 5a655583..008f30e5 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>, <0x20008 0>, <0x40008 0>, <0x50008 0>; + qcom,board-id = <8 0>, <0x10108 0>, <0x20008 0>, <0x30008 0>, <0x40008 0>, <0x40108 0>, <0x50008 0>, <0x60008 0>; }; From dae3881909346118d95ed6b4c03c9257ec897c95 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 26 Feb 2024 13:30:04 -0800 Subject: [PATCH 114/274] CAMX: Snap for drop 02/26/2024 mainline 1146 LA.VENDOR.15.4.0.AU248 Change-Id: Ib2febf335d30caa2dd5e60dc516007ba24777502 Signed-off-by: Wasim Khan From 8fd98a95e8cc5ee5cde2e1af96a8fa33bc9caaf0 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 27 Feb 2024 11:20:01 -0800 Subject: [PATCH 115/274] CAMX: Snap for drop 02/27/2024 mainline 1147 LA.VENDOR.15.4.0.AU248 Change-Id: I06370ccff5990e394cd8bf896f7dd6c9fa4ccd99 Signed-off-by: Wasim Khan From 96bc031355a04e05684a58762675ea8180d0330e Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Wed, 28 Feb 2024 14:48:18 -0800 Subject: [PATCH 116/274] ARM: dts: msm: Add icp dt nodes in tvm camera device tree Add ICP, BPS, IPE related device tree nodes in tvm camera device tree for pineapple. CRs-Fixed: 3706497 Change-Id: I55c1c0fde26af6b841620bbd3d31ceaa87713934 Signed-off-by: Ashish Bhimanpalliwar --- trustedvm-pineapple-camera.dtsi | 133 ++++++++++++++++++++++---------- 1 file changed, 94 insertions(+), 39 deletions(-) diff --git a/trustedvm-pineapple-camera.dtsi b/trustedvm-pineapple-camera.dtsi index de791bd2..8d571974 100644 --- a/trustedvm-pineapple-camera.dtsi +++ b/trustedvm-pineapple-camera.dtsi @@ -1258,23 +1258,25 @@ msm_cam_smmu_icp { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x1820 0x00>, - <&apps_smmu 0x18C0 0x00>, - <&apps_smmu 0x1800 0x00>, - <&apps_smmu 0x1840 0x00>, - <&apps_smmu 0x1880 0x00>; + iommus = <&apps_smmu 0x18C2 0x00>, + <&apps_smmu 0x1841 0x00>, + <&apps_smmu 0x1881 0x00>, + <&apps_smmu 0x1808 0x20>; cam-smmu-label = "icp"; qcom,iommu-faults = "stall-disable", "non-fatal"; - qcom,iommu-dma-addr-pool = <0x0 0xf9500000 0xf 0x06a00000>; + /* dma-addr-pool is iova address range for io region */ + /* here size of dma-addr-pool is appoximately 2.5GB */ + qcom,iommu-dma-addr-pool = <0x0 0x1FF00000 0x0 0xC0000000>; dma-coherent; + /* TVM iova address range can be between 48MB to 3GB */ icp_iova_mem_map: iova-mem-map { iova-mem-region-shared { - /* Shared region is ~900MB long */ + /* Shared region is ~423MB long */ iova-region-name = "shared"; - /* Start address: 0xc0700000 */ - iova-region-start = <0x0 0xc0700000>; - /* Length: 0x38e00000 */ - iova-region-len = <0x0 0x38e00000>; + /* Start address: 0x5800000 */ + iova-region-start = <0x0 0x5800000>; + /* Length: 0x1a700000 */ + iova-region-len = <0x0 0x1a700000>; iova-region-id = <0x1>; status = "ok"; }; @@ -1282,8 +1284,8 @@ iova-mem-region-fwuncached-region { /* FW uncached region is 5 MB long */ iova-region-name = "fw_uncached"; - /* Start address: 0xc0200000 */ - iova-region-start = <0x0 0xc0200000>; + /* Start address: 0x5300000 */ + iova-region-start = <0x0 0x5300000>; /* Length: 0x500000 */ iova-region-len = <0x0 0x500000>; iova-region-id = <0x6>; @@ -1293,48 +1295,35 @@ /* Used for HFI queues/sec heap */ iova-mem-region-generic-region { iova-region-name = "icp_hfi"; - iova-region-start = <0x0 0xc0300000>; + /* Start address: 0x5300000 */ + iova-region-start = <0x0 0x5300000>; /* Length: 0x200000 */ iova-region-len = <0x0 0x200000>; iova-region-id = <0x0>; }; - /* Global Sync Memory for IPC */ - iova-mem-region-global-sync-region { - iova-region-name = "global_sync"; - iova-region-start = <0x0 0xc0200000>; - /* Length: 0x100000 */ - iova-region-len = <0x0 0x100000>; - iova-region-id = <0x2>; - phy-addr = <0x82600000>; - }; }; iova-mem-device-region { /* Device region is appropriate 1MB */ iova-region-name = "device"; - iova-region-start = <0x0 0xc0100000>; + /* Start address: 0x5200000 */ + iova-region-start = <0x0 0x5200000>; + /* Length: 0x100000 */ iova-region-len = <0x0 0x100000>; iova-region-id = <0x7>; subregion_support; status = "ok"; - iova-mem-region-synx-hwmutex { - iova-region-name = "synx_hwmutex"; - iova-region-start = <0x0 0xc0100000>; - iova-region-len = <0x0 0x1000>; - iova-region-id = <0x1>; - phy-addr = <0x1f4a000>; - }; }; iova-mem-region-io { - /* IO region is approximately 60 GB */ + /* IO region is approximately 2.5 GB */ iova-region-name = "io"; - /* Start address: 0xf9500000 */ - iova-region-start = <0x0 0xf9500000>; - /* Length: 0xf06a00000 */ - iova-region-len = <0xf 0x06a00000>; + /* Start address: 0x1FF00000 */ + iova-region-start = <0x0 0x1FF00000>; + /* Length: 0xC0000000 */ + iova-region-len = <0x0 0xC0000000>; iova-region-id = <0x3>; status = "ok"; }; @@ -1342,8 +1331,8 @@ iova-mem-qdss-region { /* QDSS region is appropriate 1MB */ iova-region-name = "qdss"; - /* Start address: 0xc0000000 */ - iova-region-start = <0x0 0xc0000000>; + /* Start address: 0x5100000 */ + iova-region-start = <0x0 0x5100000>; /* Length: 0x100000 */ iova-region-len = <0x0 0x100000>; iova-region-id = <0x5>; @@ -2646,5 +2635,71 @@ interrupts = ; status = "ok"; }; -}; + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,icp", + "qcom,ipe0", + "qcom,bps"; + num-icp = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_use_pil; + icp_pc_en; + }; + cam_icp: qcom,icp@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0xac02000 0x1000>, + <0x0ac04000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x2000 0x4000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + qos-val = <0x808>; + cam_hw_pid = <11>; + vmrm-resource-ids = <29 29 29>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0xac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 13 31>; + vmrm-resource-ids = <30 30 30>; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps680"; + reg = <0xac2c000 0xb000>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "bps-vdd"; + nrt-device; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <6 30>; + vmrm-resource-ids = <31 31 31>; + status = "ok"; + }; +}; From 6cc5ff9cb98ef8657d46ef94ca1dcfd6dce69e78 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 28 Feb 2024 14:48:20 -0800 Subject: [PATCH 117/274] CAMX: Snap for drop 02/28/2024 mainline 1148 LA.VENDOR.15.4.0.AU254 58af205 Merge 'ARM: dts: msm: Add icp dt nodes in tvm camera device tree' into camera-kernel.lnx.dev Change-Id: Ibf503ec738dbd5f19cbe199f56c16555864c68cf Signed-off-by: Wasim Khan From 9ad9a6704f25fe56476b23cf1d3cc302bbcf0cf0 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Thu, 29 Feb 2024 15:36:20 -0800 Subject: [PATCH 118/274] CAMX: Snap for drop 02/29/2024 mainline 1149 LA.VENDOR.15.4.0.AU254 Change-Id: Ia713511e45f606886c7f510d64f7b5fad842cd4c Signed-off-by: Wasim Khan From 6abbd1b7837de6235ef6124fa44734b6e830f72d Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Fri, 1 Mar 2024 10:47:05 -0800 Subject: [PATCH 119/274] ARM: dts: msm: Add new updated board-id for camera Add new Board id information for multiple types of CDP and MTP devices. CRs-Fixed: 3731095 Change-Id: If717a9525fd4e7c0becd72b3b4e41099be930ab7 Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dts | 2 +- sun-camera-sensor-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index fcd2b648..6d140a32 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; }; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 5a655583..008f30e5 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>, <0x20008 0>, <0x40008 0>, <0x50008 0>; + qcom,board-id = <8 0>, <0x10108 0>, <0x20008 0>, <0x30008 0>, <0x40008 0>, <0x40108 0>, <0x50008 0>, <0x60008 0>; }; From 9c800374780789dc6a5107b25872d1d4692140dc Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 1 Mar 2024 10:47:07 -0800 Subject: [PATCH 120/274] CAMX: Snap for drop 03/01/2024 mainline 1150 LA.VENDOR.15.4.0.AU254 07032d8 Merge 'ARM: dts: msm: Add new updated board-id for camera' into camera-kernel.lnx.dev Change-Id: I043d3e2672c867570d71fdb0a4f452f9b825d02f Signed-off-by: Wasim Khan From 3b03f053ffc07013c802e0454a6e685da0d8d50c Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 5 Mar 2024 07:18:53 -0800 Subject: [PATCH 121/274] CAMX: Snap for drop 03/04/2024 mainline 1151 LA.VENDOR.15.4.0.AU254 Change-Id: I6cc4a106690a02c241f333580973ea73966926ad Signed-off-by: Wasim Khan From ee60b4d4e21e94d682883788b5e4fe520ebe3cce Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Thu, 7 Mar 2024 11:31:42 -0800 Subject: [PATCH 122/274] CAMX: Snap for drop 03/05/2024 mainline 1152 LA.VENDOR.15.4.0.AU262 Change-Id: I845ca8fe84adb410a331d821debf95b71f9f3135 Signed-off-by: Wasim Khan From e17b23f8003d63080763fb9b7f452a0c138f1787 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Thu, 7 Mar 2024 11:31:45 -0800 Subject: [PATCH 123/274] ARM: dts: msm: enabling cesta and ddr drv This change will help to enable CLK and DDR drv feature. CRs-Fixed: 3736393 Change-Id: I6b9b76818f2d23d72936390fcfa8a961a894665b Signed-off-by: Soumen Ghosh --- sun-camera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index bd25bf59..8430eb36 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1733,6 +1733,7 @@ sys-cache-uids = <71 72 73 74 75>; sys-cache-concur = <1 1 1 0 0>; enable-smart-qos; + enable-cam-drv = <(CAM_DDR_DRV | CAM_CLK_DRV)>; rt-wr-priority-min = <4>; rt-wr-priority-max = <5>; rt-wr-priority-clamp = <6>; From 05479d7c929c0f994467ab5c10bdfa05213d7df6 Mon Sep 17 00:00:00 2001 From: hchintal Date: Thu, 7 Mar 2024 11:31:47 -0800 Subject: [PATCH 124/274] CAMX: Snap for drop 03/06/2024 mainline 1153 LA.VENDOR.15.4.0.AU262 4353642 Merge 'ARM: dts: msm: enabling cesta and ddr drv' into camera-kernel.lnx.dev Change-Id: I5ced8e10a0ba6880335feb7664e7c29be0bc2e0c Signed-off-by: hchintal From 37bbd09dcd101c2edbd26432e240baa4d8bacee8 Mon Sep 17 00:00:00 2001 From: hchintal Date: Fri, 8 Mar 2024 11:33:38 -0800 Subject: [PATCH 125/274] CAMX: Snap for drop 03/07/2024 mainline 1154 LA.VENDOR.15.4.0.AU262 Change-Id: I74adb7e05cc23a90175dbb8193dc33fd7d48eda2 Signed-off-by: hchintal From b08f259547368fed939de7483aedc1c93ea48927 Mon Sep 17 00:00:00 2001 From: hchintal Date: Fri, 8 Mar 2024 11:33:40 -0800 Subject: [PATCH 126/274] CAMX: Snap for drop 03/08/2024 mainline 1155 LA.VENDOR.15.4.0.AU262 Change-Id: I510346a10fb494f91f220d433b74960d4bc1c2fd Signed-off-by: hchintal From 526f867aea233e364084bf7e286b7877180aa3ca Mon Sep 17 00:00:00 2001 From: hchintal Date: Tue, 12 Mar 2024 10:26:24 -0700 Subject: [PATCH 127/274] CAMX: Snap for drop 03/11/2024 mainline 1156 LA.VENDOR.15.4.0.AU262 Change-Id: I6f84d2641f23b9ce489b8468f6656894593c497f Signed-off-by: hchintal From 85202b39b41122758930b383557d84b8dfa4c36b Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 12 Mar 2024 15:58:57 -0700 Subject: [PATCH 128/274] CAMX: Snap for drop 03/12/2024 mainline 1157 LA.VENDOR.15.4.0.AU270 Change-Id: I6fcc7e691df6ac8237e1250557e5838bd8161ee9 Signed-off-by: Haritha Chintalapati From 3002a1df891a5f39a44965dfe4c1118bebd3c936 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 13 Mar 2024 13:17:02 -0700 Subject: [PATCH 129/274] CAMX: Snap for drop 03/13/2024 mainline 1158 LA.VENDOR.15.4.0.AU270 Change-Id: Ifd0029e28f0cc52af55ff45f9e093506a4825e02 Signed-off-by: Haritha Chintalapati From 2f7f7e6bf087c2d76896a85ff33c09f9e8b99b39 Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 16:56:40 -0700 Subject: [PATCH 130/274] Revert "ARM: dts: msm: Add new updated board-id for camera" This reverts commit 813ef2af29fabed6171b0fadf905e229f7b31783. Signed-off-by: Vaishali Gupta Change-Id: I1133599aef3b2504e08489bc9918e70c8389e7e0 --- sun-camera-sensor-cdp.dts | 2 +- sun-camera-sensor-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 6d140a32..fcd2b648 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; }; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 008f30e5..5a655583 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>, <0x10108 0>, <0x20008 0>, <0x30008 0>, <0x40008 0>, <0x40108 0>, <0x50008 0>, <0x60008 0>; + qcom,board-id = <8 0>, <0x20008 0>, <0x40008 0>, <0x50008 0>; }; From 048cbd872859740c708cc8c62ec1c4dd63ff83aa Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 16:56:45 -0700 Subject: [PATCH 131/274] Revert "ARM: dts: msm: Add new board-id for camera sensor" This reverts commit 9a9c2befa6a0c08bd4fcd3317bd3a46d22a6713a. Signed-off-by: Vaishali Gupta Change-Id: Ia0c6091299d87658c8c3f315efc8e81843381507 --- sun-camera-sensor-cdp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index fcd2b648..8c06d501 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; + qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x50001 0>, <0x60001 0>; }; From c14e65e2436dad2f0e13a0a6ea572bb7291cbac1 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 19 Mar 2024 13:36:07 -0700 Subject: [PATCH 132/274] CAMX: Snap for drop 03/14/2024 mainline 1159 LA.VENDOR.15.4.0.AU270 Change-Id: Iea923823962d68ec3044b3448d4636fa343066da Signed-off-by: Haritha Chintalapati From 174a550831de51e1f38b487f7a88bb5434cbe7be Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 19 Mar 2024 13:36:19 -0700 Subject: [PATCH 133/274] CAMX: Snap for drop 03/18/2024 mainline 1160 LA.VENDOR.15.4.0.AU270 Change-Id: I3c5e72b386e1b9ebc665dc648ee0ede56e6e8fb3 Signed-off-by: Haritha Chintalapati From 858bcf1f1fffefc9e0be674551d5c9951c6559e4 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 20 Mar 2024 11:09:28 -0700 Subject: [PATCH 134/274] CAMX: Snap for drop 03/20/2024 mainline 1161 LA.VENDOR.15.4.0.AU278 Change-Id: I929c0e015d64d0ee90da37830954eb92eadd435a Signed-off-by: Haritha Chintalapati From c976d6a547517a2dd1dae0350ad809ab0f351f1c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 21 Mar 2024 17:35:56 -0700 Subject: [PATCH 135/274] CAMX: Snap for drop 03/20/2024 mainline 1162 LA.VENDOR.15.4.0.AU278 Change-Id: I27667c98fa80ec641ef06e10e6fe9de903893a1c Signed-off-by: Haritha Chintalapati From 33735e43018504219b403485c335a87c497e5057 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 21 Mar 2024 17:35:59 -0700 Subject: [PATCH 136/274] CAMX: Snap for drop 03/21/2024 mainline 1163 LA.VENDOR.15.4.0.AU278 Change-Id: If0dde0cb9404505340b99d8055588025194e1310 Signed-off-by: Haritha Chintalapati From 59fc199d70b5782f634fa378053f83a9f9a69355 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Sat, 23 Mar 2024 15:26:01 -0700 Subject: [PATCH 137/274] CAMX: Snap for drop 03/22/2024 mainline 1164 LA.VENDOR.15.4.0.AU278 Change-Id: If20c22f64bc7e5a9aaa139a57682b1828ab61d8d Signed-off-by: Haritha Chintalapati From 86b274f07278d606db900c5463892b48588cb73f Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 25 Mar 2024 20:51:55 -0700 Subject: [PATCH 138/274] CAMX: Snap for drop 03/25/2024 mainline 1165 LA.VENDOR.15.4.0.AU278 Change-Id: I4071a7ec0f3985266af84211b14e4866f2f49345 Signed-off-by: Haritha Chintalapati From 2964bdf933c0bb97e2f64f0980b81faa2302aa73 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 28 Mar 2024 18:00:18 -0700 Subject: [PATCH 139/274] CAMX: Snap for drop 03/27/2024 mainline 1166 LA.VENDOR.15.4.0.AU284 Change-Id: I4ca75dd630ae668800d4ad06b006b920cb63a28e Signed-off-by: Haritha Chintalapati From dfb7c5948a758c06c22f5da378c381798239025e Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Thu, 28 Mar 2024 18:00:21 -0700 Subject: [PATCH 140/274] ARM: dts: msm: Fix reg cam base for camera nodes in sun Currently, the register base addresses in the reg cam base property of camera nodes are incorrect. Update the values to reflect the correct difference with camera base. Also, update the reg base addresses in all the camera nodes for uniformity. CRs-Fixed: 3762492 Change-Id: Idfa710a05b4e1f45ea6739b04ba739160b8b9f03 Signed-off-by: Mukund Madhusudan Atre --- sun-camera.dtsi | 120 ++++++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 8430eb36..816f8fcc 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -876,7 +876,7 @@ compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; reg = <0x0ada9000 0x2000>; reg-names = "csiphy"; - reg-cam-base = <0xa9000>; + reg-cam-base = <0x1a9000>; interrupt-names = "CSIPHY0"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; @@ -908,9 +908,9 @@ cam_csiphy1: qcom,csiphy1@adab000 { cell-index = <1>; compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; - reg = <0xadab000 0x2000>; + reg = <0x0adab000 0x2000>; reg-names = "csiphy"; - reg-cam-base = <0xab000>; + reg-cam-base = <0x1ab000>; interrupt-names = "CSIPHY1"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; @@ -942,9 +942,9 @@ cam_csiphy2: qcom,csiphy2@adad000 { cell-index = <2>; compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; - reg = <0xadad000 0x2000>; + reg = <0x0adad000 0x2000>; reg-names = "csiphy"; - reg-cam-base = <0xad000>; + reg-cam-base = <0x1ad000>; interrupt-names = "CSIPHY2"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; @@ -976,9 +976,9 @@ cam_csiphy3: qcom,csiphy3@adaf000 { cell-index = <3>; compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; - reg = <0xadaf000 0x2000>; + reg = <0x0adaf000 0x2000>; reg-names = "csiphy"; - reg-cam-base = <0xaf000>; + reg-cam-base = <0x1af000>; interrupt-names = "CSIPHY3"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; @@ -1010,9 +1010,9 @@ cam_csiphy4: qcom,csiphy4@adb1000 { cell-index = <4>; compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; - reg = <0xadb1000 0x2000>; + reg = <0x0adb1000 0x2000>; reg-names = "csiphy"; - reg-cam-base = <0xb1000>; + reg-cam-base = <0x1b1000>; interrupt-names = "CSIPHY4"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; @@ -1044,9 +1044,9 @@ cam_csiphy5: qcom,csiphy5@adb3000 { cell-index = <5>; compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; - reg = <0xadb3000 0x2000>; + reg = <0x0adb3000 0x2000>; reg-names = "csiphy"; - reg-cam-base = <0xb3000>; + reg-cam-base = <0x1b3000>; interrupt-names = "CSIPHY5"; interrupts = ; regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; @@ -1078,7 +1078,7 @@ cam_cci0: qcom,cci0@ac7b000 { cell-index = <0>; compatible = "qcom,cci", "simple-bus"; - reg = <0xac7b000 0x1000>; + reg = <0x0ac7b000 0x1000>; reg-names = "cci"; reg-cam-base = <0x7b000>; interrupt-names = "CCI0"; @@ -1166,7 +1166,7 @@ cam_cci1: qcom,cci1@ac7c000 { cell-index = <1>; compatible = "qcom,cci", "simple-bus"; - reg = <0xac7c000 0x1000>; + reg = <0x0ac7c000 0x1000>; reg-names = "cci"; reg-cam-base = <0x7c000>; interrupt-names = "CCI1"; @@ -1254,7 +1254,7 @@ cam_cci2: qcom,cci2@ac7d000 { cell-index = <2>; compatible = "qcom,cci", "simple-bus"; - reg = <0xac7d000 0x1000>; + reg = <0x0ac7d000 0x1000>; reg-names = "cci"; reg-cam-base = <0x7d000>; interrupt-names = "CCI2"; @@ -1607,12 +1607,12 @@ label = "cpas"; arch-compat = "cpas_top"; reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh", "cam_cesta"; - reg = <0xac04000 0x1000>, + reg = <0x0ac04000 0x1000>, <0x0ac62000 0x9200>, <0x0ad90000 0x9000>, - <0xbbf0000 0x1f00>, - <0xadcb000 0x5000>; - reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000 0xadcb000>; + <0x0bbf0000 0x1f00>, + <0x0adcb000 0x5000>; + reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000 0x0adcb000>; interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt"; interrupts = , ; @@ -2480,7 +2480,7 @@ cell-index = <0>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; - reg = <0xac7f000 0x580>; + reg = <0x0ac7f000 0x580>; reg-names = "rt-cdm0"; reg-cam-base = <0x7f000>; interrupt-names = "rt-cdm0"; @@ -2505,7 +2505,7 @@ cell-index = <1>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; - reg = <0xac80000 0x580>; + reg = <0x0ac80000 0x580>; reg-names = "rt-cdm1"; reg-cam-base = <0x80000>; interrupt-names = "rt-cdm1"; @@ -2530,7 +2530,7 @@ cell-index = <2>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; - reg = <0xac81000 0x580>; + reg = <0x0ac81000 0x580>; reg-names = "rt-cdm2"; reg-cam-base = <0x81000>; interrupt-names = "rt-cdm2"; @@ -2555,7 +2555,7 @@ cell-index = <3>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; - reg = <0xac82000 0x580>; + reg = <0x0ac82000 0x580>; reg-names = "rt-cdm3"; reg-cam-base = <0x82000>; interrupt-names = "rt-cdm3"; @@ -2580,7 +2580,7 @@ cell-index = <4>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; - reg = <0xac83000 0x580>; + reg = <0x0ac83000 0x580>; reg-names = "rt-cdm4"; reg-cam-base = <0x83000>; interrupt-names = "rt-cdm4"; @@ -2611,8 +2611,8 @@ cell-index = <0>; compatible = "qcom,csid980"; reg-names = "csid"; - reg = <0xad27000 0x2b00>; - reg-cam-base = <0x27000>; + reg = <0x0ad27000 0x2b00>; + reg-cam-base = <0x127000>; rt-wrapper-base = <0x86000>; interrupt-names = "csid0"; interrupts = ; @@ -2645,7 +2645,7 @@ cell-index = <0>; compatible = "qcom,mc_tfe980"; reg-names = "ife", "cam_camnoc_rt"; - reg = <0xac86000 0x10000>, + reg = <0x0ac86000 0x10000>, <0x0ad90000 0x9000>; reg-cam-base = <0x86000 0x19000>; rt-wrapper-base = <0x86000>; @@ -2690,8 +2690,8 @@ cell-index = <1>; compatible = "qcom,csid980"; reg-names = "csid"; - reg = <0xad2a000 0x2b00>; - reg-cam-base = <0x2a000>; + reg = <0x0ad2a000 0x2b00>; + reg-cam-base = <0x12a000>; rt-wrapper-base = <0x86000>; interrupt-names = "csid1"; interrupts = ; @@ -2724,7 +2724,7 @@ cell-index = <1>; compatible = "qcom,mc_tfe980"; reg-names = "ife", "cam_camnoc_rt"; - reg = <0xac96000 0x10000>, + reg = <0x0ac96000 0x10000>, <0x0ad90000 0x9000>; reg-cam-base = <0x96000 0x19000>; rt-wrapper-base = <0x86000>; @@ -2769,8 +2769,8 @@ cell-index = <2>; compatible = "qcom,csid980"; reg-names = "csid"; - reg = <0xad2d000 0x2b00>; - reg-cam-base = <0x2d000>; + reg = <0x0ad2d000 0x2b00>; + reg-cam-base = <0x12d000>; rt-wrapper-base = <0x86000>; interrupt-names = "csid2"; interrupts = ; @@ -2803,7 +2803,7 @@ cell-index = <2>; compatible = "qcom,mc_tfe980"; reg-names = "ife", "cam_camnoc_rt"; - reg = <0xaca6000 0x10000>, + reg = <0x0aca6000 0x10000>, <0x0ad90000 0x9000>; reg-cam-base = <0xa6000 0x19000>; rt-wrapper-base = <0x86000>; @@ -2848,9 +2848,9 @@ cell-index = <3>; compatible = "qcom,csid-lite980"; reg-names = "csid-lite"; - reg = <0xad6d000 0xa00>; - reg-cam-base = <0x6d000>; - rt-wrapper-base = <0x6c000>; + reg = <0x0ad6d000 0xa00>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; interrupt-names = "csid-lite0"; interrupts = ; regulator-names = "gdsc"; @@ -2888,9 +2888,9 @@ cell-index = <3>; compatible = "qcom,vfe-lite980"; reg-names = "ife-lite"; - reg = <0xad6d000 0x2800>; - reg-cam-base = <0x6d000>; - rt-wrapper-base = <0x6c000>; + reg = <0x0ad6d000 0x2800>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; interrupt-names = "ife-lite0"; interrupts = ; regulator-names = "gdsc"; @@ -2929,9 +2929,9 @@ cell-index = <4>; compatible = "qcom,csid-lite980"; reg-names = "csid-lite"; - reg = <0xad72000 0xa00>; - reg-cam-base = <0x72000>; - rt-wrapper-base = <0x6c000>; + reg = <0x0ad72000 0xa00>; + reg-cam-base = <0x172000>; + rt-wrapper-base = <0x16c000>; interrupt-names = "csid-lite1"; interrupts = ; regulator-names = "gdsc"; @@ -2969,9 +2969,9 @@ cell-index = <4>; compatible = "qcom,vfe-lite980"; reg-names = "ife-lite"; - reg = <0xad72000 0x2800>; - reg-cam-base = <0x72000>; - rt-wrapper-base = <0x6c000>; + reg = <0x0ad72000 0x2800>; + reg-cam-base = <0x172000>; + rt-wrapper-base = <0x16c000>; interrupt-names = "ife-lite1"; interrupts = ; regulator-names = "gdsc"; @@ -3011,9 +3011,9 @@ phy-id = <0>; compatible = "qcom,cam-tpg104"; reg-names = "tpg0", "cam_cpas_top"; - reg = <0xad8b000 0x400>, - <0xac04000 0x1000>; - reg-cam-base = <0x8b000 0x04000>; + reg = <0x0ad8b000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18b000 0x04000>; regulator-names = "gdsc"; gdsc-supply = <&cam_cc_titan_top_gdsc>; interrupt-names = "tpg0"; @@ -3039,9 +3039,9 @@ phy-id = <1>; compatible = "qcom,cam-tpg104"; reg-names = "tpg1", "cam_cpas_top"; - reg = <0xad8c000 0x400>, - <0xac04000 0x1000>; - reg-cam-base = <0x8c000 0x04000>; + reg = <0x0ad8c000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18c000 0x04000>; regulator-names = "gdsc"; gdsc-supply = <&cam_cc_titan_top_gdsc>; interrupt-names = "tpg1"; @@ -3067,9 +3067,9 @@ phy-id = <2>; compatible = "qcom,cam-tpg104"; reg-names = "tpg2", "cam_cpas_top"; - reg = <0xad8d000 0x400>, - <0xac04000 0x1000>; - reg-cam-base = <0x8d000 0x04000>; + reg = <0x0ad8d000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18d000 0x04000>; regulator-names = "gdsc"; gdsc-supply = <&cam_cc_titan_top_gdsc>; interrupt-names = "tpg2"; @@ -3122,7 +3122,7 @@ cell-index = <0>; compatible = "qcom,cam-icp_v2_1"; icp-version = <0x0201>; - reg = <0xac06000 0x1000>, + reg = <0x0ac06000 0x1000>, <0x0ac09000 0x1000>; reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x6000 0x9000>; @@ -3166,8 +3166,8 @@ cell-index = <1>; compatible = "qcom,cam-icp_v2_1"; icp-version = <0x0201>; - reg = <0xac16000 0x1000>, - <0xac19000 0x1000>; + reg = <0x0ac16000 0x1000>, + <0x0ac19000 0x1000>; reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x16000 0x19000>; interrupt-names = "icp1"; @@ -3209,7 +3209,7 @@ cam_ipe0: qcom,ipe0@ac42000 { cell-index = <0>; compatible = "qcom,cam-ipe680"; - reg = <0xac42000 0x18000>; + reg = <0x0ac42000 0x18000>; reg-names = "ipe0_top"; reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; @@ -3249,7 +3249,7 @@ cam_ofe: qcom,ofe@ac2a000 { cell-index = <0>; compatible = "qcom,cam-ofe"; - reg = <0xac2a000 0x18000>; + reg = <0x0ac2a000 0x18000>; reg-names = "ofe0_top"; reg-cam-base = <0x2a000>; regulator-names = "ofe0-vdd"; @@ -3307,7 +3307,7 @@ cell-index = <0>; compatible = "qcom,cam_jpeg_enc_780"; reg-names = "jpegenc_hw", "cam_camnoc_nrt"; - reg = <0xac25000 0x1000>, + reg = <0x0ac25000 0x1000>, <0x0ac62000 0x9200>; reg-cam-base = <0x25000 0x62000>; interrupt-names = "jpeg_enc0"; @@ -3337,7 +3337,7 @@ cell-index = <0>; compatible = "qcom,cam_jpeg_dma_780"; reg-names = "jpegdma_hw", "cam_camnoc_nrt"; - reg = <0xac26000 0x1000>, + reg = <0x0ac26000 0x1000>, <0x0ac62000 0x9200>; reg-cam-base = <0x26000 0x62000>; interrupt-names = "jpeg_dma0"; From 6f160d4e1582c3ebc2deba351bfb8366cfb2a584 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 28 Mar 2024 18:00:23 -0700 Subject: [PATCH 141/274] CAMX: Snap for drop 03/28/2024 mainline 1167 LA.VENDOR.15.4.0.AU284 15e58ac Merge 'ARM: dts: msm: Fix reg cam base for camera nodes in sun' into camera-kernel.lnx.dev Change-Id: I9b9a401d680abae09cfc6562e0b433b19e4c3034 Signed-off-by: Haritha Chintalapati From cb62ae1e8151544a358d55cb08ea43335d12f6d3 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 29 Mar 2024 17:49:53 -0700 Subject: [PATCH 142/274] CAMX: Snap for drop 03/29/2024 mainline 1168 LA.VENDOR.15.4.0.AU284 Change-Id: Iaa3e1eef26b7fa8f914a27b8448500628f71d6e8 Signed-off-by: Haritha Chintalapati From 5787eb38ad5cb55813ea9b59ba6166da239db078 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 1 Apr 2024 21:44:55 -0700 Subject: [PATCH 143/274] CAMX: Snap for drop 04/01/2024 mainline 1168_1 LA.VENDOR.15.4.0.AU284 Change-Id: Ide2c22cc972c9795908ffc7bd4a519e4fcc15289 Signed-off-by: Haritha Chintalapati From 71d5f566a8f768adfbe82e2fdc3cdeaefb5a2463 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 2 Apr 2024 22:35:38 -0700 Subject: [PATCH 144/274] CAMX: Snap for drop 04/01/2024 mainline 1169 LA.VENDOR.15.4.0.AU284 Change-Id: I48b878f11b5d5343d0848446f0046125ba6addc5 Signed-off-by: Haritha Chintalapati From f758a7e10d8e53a8dc6949d1e77d17d5bfda9d76 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 3 Apr 2024 17:09:00 -0700 Subject: [PATCH 145/274] CAMX: Snap for drop 04/03/2024 mainline 1170 LA.VENDOR.15.4.0.AU291 Change-Id: If936342fa062310e0d7d0c026355b4b4cf2f60dc Signed-off-by: Haritha Chintalapati From 4c1a0231dcfcffcc627efe9193988e844450a789 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 4 Apr 2024 16:28:18 -0700 Subject: [PATCH 146/274] CAMX: Snap for drop 04/04/2024 mainline 1171 LA.VENDOR.15.4.0.AU291 Change-Id: Iedc47c859de8e5ca445d162662986e55c77d4947 Signed-off-by: Haritha Chintalapati From dda8a49a213c72a543b1462540bf179536d6cce3 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 5 Apr 2024 13:59:18 -0700 Subject: [PATCH 147/274] CAMX: Snap for drop 04/05/2024 mainline 1172 LA.VENDOR.15.4.0.AU291 Change-Id: Id7064d7e182bc0fd47d03f42eaec982842f5b6ea Signed-off-by: Haritha Chintalapati From a0db2cc2d314edc44487228334216967a154b74e Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 8 Apr 2024 23:42:11 -0700 Subject: [PATCH 148/274] CAMX: Snap for drop 04/08/2024 mainline 1173 LA.VENDOR.15.4.0.AU291 Change-Id: I6d0443b8065f09fd0cdfff32fc04a0c1cebab154 Signed-off-by: Haritha Chintalapati From 2487d232cfc63aba4f148aff43d08d77560fe5df Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 9 Apr 2024 19:28:03 -0700 Subject: [PATCH 149/274] CAMX: Snap for drop 04/09/2024 mainline 1174 LA.VENDOR.15.4.0.AU297 Change-Id: I5c87d7e7a82f45b089905ba25618c91ec1341579 Signed-off-by: Haritha Chintalapati From d97bf4e71c2a967f97e6658d9202e951258d60c2 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 10 Apr 2024 19:25:54 -0700 Subject: [PATCH 150/274] CAMX: Snap for drop 04/10/2024 mainline 1175 LA.VENDOR.15.4.0.AU297 Change-Id: I748d5ca78ff29a8bcd434c796e542029cbf18210 Signed-off-by: Haritha Chintalapati From 3ee0e60707d753d0466aeda412876b7e037e40b9 Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Fri, 12 Apr 2024 01:49:21 -0700 Subject: [PATCH 151/274] ARM: dts: msm: Add new updated msm-id for camera Updated new msm-id for new variant devices under camera. And also updated change in board-id for selecting correct power grid. CRs-Fixed: 3773324 Change-Id: I3ca9e2b6879f414b88e367035aeb3887d466045a Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dts | 4 +++- sun-camera-sensor-mtp.dts | 6 ++++-- sun-camera-sensor-qrd.dts | 4 +++- sun-camera-sensor-rumi.dts | 4 +++- sun-camera.dts | 4 +++- 5 files changed, 16 insertions(+), 6 deletions(-) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 6d140a32..83f1e76b 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -12,6 +12,8 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP/RCM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp", "qcom,rcm", "qcom,sun-rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <1 0>, <21 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>, <0x50001 0>, <0x60001 0>, <0x30015 0>, <0x40015 0>, <0x20015 0>; }; diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 008f30e5..54da5b60 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -12,6 +12,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>, <0x10108 0>, <0x20008 0>, <0x30008 0>, <0x40008 0>, <0x40108 0>, <0x50008 0>, <0x60008 0>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <8 0>, <0x108 0>, <0x20008 0>, <0x30008 0>, <0x40008 0>, <0x40108 0>, <0x50008 0>, <0x60008 0>; }; diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 95472e51..6222d3f3 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -12,6 +12,8 @@ / { model = "Qualcomm Technologies, Inc. Sun QRD"; compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; }; diff --git a/sun-camera-sensor-rumi.dts b/sun-camera-sensor-rumi.dts index e0190d72..fa7b4141 100644 --- a/sun-camera-sensor-rumi.dts +++ b/sun-camera-sensor-rumi.dts @@ -12,6 +12,8 @@ / { model = "Qualcomm Technologies, Inc. Sun RUMI"; compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <15 0>; }; diff --git a/sun-camera.dts b/sun-camera.dts index 80cb1c7f..8e77a5d3 100644 --- a/sun-camera.dts +++ b/sun-camera.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0 0>; }; From f114740afe27b31edfbb0bb68fc6548b536441fc Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Fri, 12 Apr 2024 01:49:25 -0700 Subject: [PATCH 152/274] ARM: dts: msm: Add new board id on sun qrd target Add new board id to support sensor, eeprom, flash Actuator node. CRs-Fixed: 3752824 Change-Id: Iccecbf205ae5c99621c3a83d35492c78975cd0d8 Signed-off-by: Pengfei Liu --- sun-camera-sensor-qrd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 6222d3f3..5ee419f5 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -15,5 +15,5 @@ qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>, <0x100027f 0x10000>, <0x100027f 0x20000>; - qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; + qcom,board-id = <0x1000B 0>, <0x1001F 0>, <0x2000B 0>, <0x3000B 0>; }; From eeb10a7756dd299144259889fb85a82544dc87e4 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 12 Apr 2024 09:50:56 -0700 Subject: [PATCH 153/274] CAMX: Snap for drop 04/12/2024 mainline 1176 LA.VENDOR.15.4.0.AU297 86f8846 Merge 'ARM: dts: msm: Add new board id on sun qrd target' into camera-kernel.lnx.dev 59fe955 Merge 'ARM: dts: msm: Add new updated msm-id for camera' into camera-kernel.lnx.dev Change-Id: Ib6a224e40cec4c6e8b40ed13aed31af96372ee78 Signed-off-by: Haritha Chintalapati From bd97ff84aea2487cda1244889a9c534171d67f04 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 15 Apr 2024 12:59:48 -0700 Subject: [PATCH 154/274] CAMX: Snap for drop 04/13/2024 mainline 1177 LA.VENDOR.15.4.0.AU297 Change-Id: I12f4964e151921b5b93f013cb9098bb4e5c8aaf7 Signed-off-by: Haritha Chintalapati From e6224445f3c72eadf1b71ac6483668b9b8775bde Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 16 Apr 2024 17:51:20 -0700 Subject: [PATCH 155/274] CAMX: Snap for drop 04/16/2024 mainline 1178 LA.VENDOR.15.4.0.AU305 Change-Id: I9de56fe37e51aa4e1e978167a4b616faa6b2c878 Signed-off-by: Haritha Chintalapati From 47f815a847ca6fc8c48322a28075d0223461a346 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 17 Apr 2024 17:23:26 -0700 Subject: [PATCH 156/274] CAMX: Snap for drop 04/17/2024 mainline 1179 LA.VENDOR.15.4.0.AU305 Change-Id: I651fe3a71aa656babdb22b2ab3611a380b386e93 Signed-off-by: Haritha Chintalapati From b4e810d7c7b2d2a2ddac21e2bc58898e7e1dcb72 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 18 Apr 2024 18:57:50 -0700 Subject: [PATCH 157/274] CAMX: Snap for drop 04/18/2024 mainline 1180 LA.VENDOR.15.4.0.AU305 Change-Id: I2ac77956e3e722ae976bc4b94e0c29a3bf8a548a Signed-off-by: Haritha Chintalapati From 7771eb521d1738a49f02de3df55b9b720fbe4b5d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 22 Apr 2024 11:45:33 -0700 Subject: [PATCH 158/274] CAMX: Snap for drop 04/19/2024 mainline 1181 LA.VENDOR.15.4.0.AU305 Change-Id: I5413704821a59aa1d468da260bb2ccd16abf0253 Signed-off-by: Haritha Chintalapati From f69895c3f8968de2d7ab4507e5fca6de695444a1 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 22 Apr 2024 15:46:46 -0700 Subject: [PATCH 159/274] CAMX: Snap for drop 04/22/2024 mainline 1182 LA.VENDOR.15.4.0.AU305 Change-Id: Ie437bc3f09a9514b2dd31b862d303c9716834566 Signed-off-by: Haritha Chintalapati From 8e7e5d4c5c8ed43cba073f7c2c0306106b2a408c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 25 Apr 2024 12:07:55 -0700 Subject: [PATCH 160/274] CAMX: Snap for drop 04/23/2024 mainline 1183 LA.VENDOR.15.4.0.AU305 Change-Id: If39b3f71018b27ec2ee806e89f6b243d34054769 Signed-off-by: Haritha Chintalapati From 583c5fdde2a25591f014ccf0f39f1a93f9cb3a62 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 25 Apr 2024 12:07:59 -0700 Subject: [PATCH 161/274] CAMX: Snap for drop 04/24/2024 mainline 1184 LA.VENDOR.15.4.0.AU305 Change-Id: I9570b06ae3a4a963e74c9a7128be794ca492615a Signed-off-by: Haritha Chintalapati From 552746765d43fe93a982f121092f5aeb7ccbabfb Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 25 Apr 2024 16:02:15 -0700 Subject: [PATCH 162/274] CAMX: Snap for drop 04/25/2024 mainline 1185 LA.VENDOR.15.4.0.AU305 Change-Id: I502a494536453dbae77124d20059f780f1aaa921 Signed-off-by: Haritha Chintalapati From dc71f9086a7ec7bee0a55fbb86e5b04c17df92be Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 26 Apr 2024 16:08:23 -0700 Subject: [PATCH 163/274] CAMX: Snap for drop 04/26/2024 mainline 1186 LA.VENDOR.15.4.0.AU305 Change-Id: I99c849ef1b3aa87497ffb5cf5a55b23e14d4796b Signed-off-by: Haritha Chintalapati From c0342904bcfdd6a05f8f9a84ac4a0e91979666e6 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 29 Apr 2024 18:52:27 -0700 Subject: [PATCH 164/274] CAMX: Snap for drop 04/29/2024 mainline 1187 LA.VENDOR.15.4.0.AU313 Change-Id: I756cb8b40c37667a905f6e621ca189ad91799cfd Signed-off-by: Haritha Chintalapati From 03bdbe1192a0d66d1c3b443fa29e3d012fd9e362 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 30 Apr 2024 16:07:53 -0700 Subject: [PATCH 165/274] CAMX: Snap for drop 04/30/2024 mainline 1188 LA.VENDOR.15.4.0.AU313 Change-Id: Ieab668c5ffd697cb0c9b0671315ff5fa111467d7 Signed-off-by: Haritha Chintalapati From d0422b9d714b1f61891813921e3a1696c273bb4c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 2 May 2024 17:09:22 -0700 Subject: [PATCH 166/274] CAMX: Snap for drop 05/02/2024 mainline 1189 LA.VENDOR.15.4.0.AU313 Change-Id: Ie1065b44daa34264a40e813f7a1320b4b8ca09ba Signed-off-by: Haritha Chintalapati From 16c0f0f59dcfefc14f5c5e47d8cd500a0d916f2c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 2 May 2024 23:04:05 -0700 Subject: [PATCH 167/274] CAMX: Snap for drop 05/02/2024 mainline 1190 LA.VENDOR.15.4.0.AU313 Change-Id: I129b08c59f9502421d23c6e91b0e0f954da3ce56 Signed-off-by: Haritha Chintalapati From cc0099d0219dfe6ff6d8f73f51e6400cbef8b25e Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Mon, 6 May 2024 18:24:15 -0700 Subject: [PATCH 168/274] ARM: dts: msm: Add property to max limit RT axi bw votes Add cam-max-rt-axi-bw property to provide a max limiting value for RT axi bw votes. CRs-Fixed: 3780345 Change-Id: I14e330e02a0d2a9e978470b2c40ea4fe0e747749 Signed-off-by: Mukund Madhusudan Atre --- bindings/msm-cam-cpas.txt | 5 +++++ sun-camera.dtsi | 1 + 2 files changed, 6 insertions(+) diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index fa5d7c0d..b46f9a41 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -97,6 +97,11 @@ First Level Node - CAM CPAS device Value type: Definition: Min camnoc axi bw for the given target. +- cam-max-rt-axi-bw + Usage: optional + Value type: + Definition: Max RT axi bw allowed to be voted for the given target. + - regulator-names Usage: required Value type: diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 816f8fcc..674f3308 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1617,6 +1617,7 @@ interrupts = , ; camnoc-axi-min-ib-bw = <3000000000>; + cam-max-rt-axi-bw = <0x3 0x60447100>; regulator-names = "top-gdsc"; top-gdsc-supply = <&cam_cc_titan_top_gdsc>; clock-names = From dd139e6334cf06f28d9f11a9932715088132a183 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 6 May 2024 18:24:18 -0700 Subject: [PATCH 169/274] CAMX: Snap for drop 05/06/2024 mainline 1191 LA.VENDOR.15.4.0.AU313 facc4a4 Merge 'ARM: dts: msm: Add property to max limit RT axi bw votes' into camera-kernel.lnx.dev Change-Id: Ia333cf01cefa6e6cd9288ce8a774283de44513e2 Signed-off-by: Haritha Chintalapati From 919cc9b363c3e8ef064e9116819e627202ea1556 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 8 May 2024 14:19:17 -0700 Subject: [PATCH 170/274] CAMX: Snap for drop 05/07/2024 mainline 1192 LA.VENDOR.15.4.0.AU330 Change-Id: I65e120ff5128c886fa4b06a3b59c503e3cc7b399 Signed-off-by: Haritha Chintalapati From 29d047c74e72a4f799212d4c963ab2e6877dc8f4 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 10 May 2024 00:59:16 -0700 Subject: [PATCH 171/274] CAMX: Snap for drop 05/09/2024 mainline 1193 LA.VENDOR.15.4.0.AU330 Change-Id: Ia2669f57c672ed5b6659d9e1c39de0de6825b8e7 Signed-off-by: Haritha Chintalapati From e10ea09db69d9f0cf0277befe00b66ba38c77204 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 10 May 2024 00:59:19 -0700 Subject: [PATCH 172/274] CAMX: Snap for drop 05/10/2024 mainline 1194 LA.VENDOR.15.4.0.AU330 Change-Id: Ibf5ca74d223e89847c14bffd38811dc0890356e5 Signed-off-by: Haritha Chintalapati From 2844cc45e44cd3435693b92ba7e2f0bc18f4310c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Sun, 12 May 2024 21:50:51 -0700 Subject: [PATCH 173/274] CAMX: Snap for drop 05/10/2024 mainline 1195 LA.VENDOR.15.4.0.AU330 Change-Id: Ia4ecf02fa5d859377ca89ba2eff263e026ab0c86 Signed-off-by: Haritha Chintalapati From f29ccb12229af2c846ffc18411106837797dee78 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Wed, 15 May 2024 22:28:16 -0700 Subject: [PATCH 174/274] ARM: dts: msm: correcting cci pinctrl information cci1 pinctrl-2 and pinctrl-3 information was not correct, added the correct information. CRs-Fixed: 3809949 Change-Id: I38e06237d144ef324a0f8d4a756cb77630f8bf86 Signed-off-by: Soumen Ghosh --- sun-camera.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 674f3308..2d7b61c9 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1186,8 +1186,8 @@ "m1_active", "m1_suspend"; pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; - pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_scl3_active>; - pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_scl3_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; status = "ok"; i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { From 51b983b198a96314ef5c4140ceeaccad7673f6cb Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 15 May 2024 22:28:22 -0700 Subject: [PATCH 175/274] CAMX: Snap for drop 05/14/2024 mainline 1196 LA.VENDOR.15.4.0.AU330 6cf625d Merge 'ARM: dts: msm: correcting cci pinctrl information' into camera-kernel.lnx.dev Change-Id: I4f0700e845963bbc0eeb57610f1da17976ca237e Signed-off-by: Haritha Chintalapati From e3cab89f4d612ac8a0b0ecee71aa38764611fb7d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 15 May 2024 22:28:28 -0700 Subject: [PATCH 176/274] CAMX: Snap for drop 05/15/2024 mainline 1197 LA.VENDOR.15.4.0.AU334 Change-Id: I483a1c80995a0e4db11cd0ba94ec0385ad9cb2c4 Signed-off-by: Haritha Chintalapati From 127c72fa34174dbd3c2bb2324369a04f05373117 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 17 May 2024 12:22:52 -0700 Subject: [PATCH 177/274] CAMX: Snap for drop 05/17/2024 mainline 1198 LA.VENDOR.15.4.0.AU334 Change-Id: If1dfdd9e03a19c5b52ebbe9f95a4ce3a94de0745 Signed-off-by: Haritha Chintalapati From e7560cdc867163ca37b95539ea3162e4b19124e7 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 21 May 2024 12:25:50 -0700 Subject: [PATCH 178/274] CAMX: Snap for drop 05/20/2024 mainline 1199 LA.VENDOR.15.4.0.AU334 Change-Id: Ia414575eb7986294bff80440a6322fdfadf7bcc9 Signed-off-by: Haritha Chintalapati From 30755928b54028b6d176eb436c210229e7a4676b Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 21 May 2024 22:45:04 -0700 Subject: [PATCH 179/274] CAMX: Snap for drop 05/21/2024 mainline 1200 LA.VENDOR.15.4.0.AU345 Change-Id: I54fbe2b3333e0c442a083bec4fd2d877c23bd123 Signed-off-by: Haritha Chintalapati From 9b361f64a484051346cd053cdb46e447f028d76b Mon Sep 17 00:00:00 2001 From: Atiya Kailany Date: Wed, 22 May 2024 17:14:29 -0700 Subject: [PATCH 180/274] ARM: dts: msm: Add flag indicating crmb api support This flag is added in cpas node to indicate that the src clk in this node supports crmb api passthrough when voting. CRs-Fixed: 3799575 Change-Id: Ic11d376e2d04b49dad3185ef32ae863f60f1d759 Signed-off-by: Atiya Kailany --- bindings/msm-cam-cpas.txt | 7 +++++++ sun-camera.dtsi | 1 + 2 files changed, 8 insertions(+) diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index b46f9a41..39a6c62d 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -150,6 +150,12 @@ First Level Node - CAM CPAS device Definition: Bool property specifying whether to control camnoc axi clock from cpas driver. +- cam-crmb-clk + Usage: required + Value type: + Definition: Flag indicating whether the src clk in this node is + a crmb clk or not + - camnoc-bus-width Usage: required if control-camnoc-axi-clk is enabled Value type: @@ -509,6 +515,7 @@ Example: clock-cntl-level = "turbo"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; control-camnoc-axi-clk; + cam-crmb-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <10>; qcom,msm-bus,name = "cam_ahb"; diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 2d7b61c9..efa53d5b 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1676,6 +1676,7 @@ <0>, <0>, <0>, <0>; shared-clks-option = <0 0 0 1 0>; control-camnoc-axi-clk; + cam-crmb-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; domain-id = , From f88d988a4690b0837493cebab8bed7bf9489bb89 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 22 May 2024 17:14:33 -0700 Subject: [PATCH 181/274] CAMX: Snap for drop 05/22/2024 mainline 1201 LA.VENDOR.15.4.0.AU345 f8b64ae Merge 'ARM: dts: msm: Add flag indicating crmb api support' into camera-kernel.lnx.dev Change-Id: I2d6dc8ca602e20ea38668491b98134b2bfd69b0a Signed-off-by: Haritha Chintalapati From 67a9b916b681326460715b85b5a2bb42aa3b6120 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 23 May 2024 16:09:53 -0700 Subject: [PATCH 182/274] CAMX: Snap for drop 05/23/2024 mainline 1202 LA.VENDOR.15.4.0.AU345 Change-Id: I8bd6721a77149134b8d49b689ac92d6640a442d1 Signed-off-by: Haritha Chintalapati From 02d5af25356092ef89252a8b822ebd9f8be591b2 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 27 May 2024 23:13:32 -0700 Subject: [PATCH 183/274] CAMX: Snap for drop 05/24/2024 mainline 1203 LA.VENDOR.15.4.0.AU345 Change-Id: Id8368538cee689df83b19d282514ba91db901225 Signed-off-by: Haritha Chintalapati From 06d90a0a9b0e206edf7c8ee5e83ca5fae33094de Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 29 May 2024 14:24:27 -0700 Subject: [PATCH 184/274] CAMX: Snap for drop 05/28/2024 mainline 1204 LA.VENDOR.15.4.0.AU345 Change-Id: I3ac82a366042c109740d0405723b5245bd731e9a Signed-off-by: Haritha Chintalapati From 0de991422c6eedb40a45a7980730826bb9569a53 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 29 May 2024 17:32:04 -0700 Subject: [PATCH 185/274] CAMX: Snap for drop 05/29/2024 mainline 1205 LA.VENDOR.15.4.0.AU354 Change-Id: I44cd2e2f6981ba591dd5965e9391ef454ff38256 Signed-off-by: Haritha Chintalapati From 10fabceff35cca072144bb9e3efb2e66dacf378a Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 3 Jun 2024 10:50:45 -0700 Subject: [PATCH 186/274] CAMX: Snap for drop 05/30/2024 mainline 1206 LA.VENDOR.15.4.0.AU354 Change-Id: Iacff39bf835c862dc07e5bd3aea97db96184df90 Signed-off-by: Haritha Chintalapati From 0f3ad263b024298cd9e9900eefe5a980dec791d7 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 3 Jun 2024 10:50:49 -0700 Subject: [PATCH 187/274] CAMX: Snap for drop 05/31/2024 mainline 1207 LA.VENDOR.15.4.0.AU354 Change-Id: I19bd659e33fa98d64da8e8abfb387106ba757f90 Signed-off-by: Haritha Chintalapati From bcddbce1bbbd9fb2c3513dd0932d5d4601d42d90 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 3 Jun 2024 15:45:01 -0700 Subject: [PATCH 188/274] CAMX: Snap for drop 06/03/2024 mainline 1208 LA.VENDOR.15.4.0.AU354 Change-Id: I753f7ffc7d9b6f49639f44d0155ab98f814232ce Signed-off-by: Haritha Chintalapati From 271b8fc07fc883dd6151923eb024a48b411008cf Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 5 Jun 2024 12:41:54 -0700 Subject: [PATCH 189/274] CAMX: Snap for drop 06/04/2024 mainline 1209 LA.VENDOR.15.4.0.AU363 Change-Id: I34455e3c3da077f4fe336e9c86257fba2d09232f Signed-off-by: Haritha Chintalapati From 2a6c81ad4c2bdef8ed8e2438475e23f6a697d8a8 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 5 Jun 2024 12:41:58 -0700 Subject: [PATCH 190/274] CAMX: Snap for drop 06/05/2024 mainline 1210 LA.VENDOR.15.4.0.AU363 Change-Id: Iab7e692467fbd6f89ec427bce8542e9efc199ce7 Signed-off-by: Haritha Chintalapati From 9899a066d3f41b6678052aa146e45d47f4e7ca3d Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Sun, 9 Jun 2024 23:14:17 -0700 Subject: [PATCH 191/274] ARM: dts: msm: Update OFE write ubwc config for Pakala This change updates the UBWC write config for OFE on Pakala. CRs-Fixed: 3833870 Change-Id: I21138604bdd7927f56c4ed6409537c0344ae1132 Signed-off-by: Karthik Anantha Ram --- sun-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index efa53d5b..726439eb 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -3201,7 +3201,7 @@ clock-control-debugfs = "true"; fw_name = "CAMERA_ICP_1"; ubwc-ofe-fetch-cfg = <0x3f083 0x3f083>; - ubwc-ofe-write-cfg = <0x16209 0x16209>; + ubwc-ofe-write-cfg = <0x1620F 0x1620F>; qos-val = <0x808>; fw-pas-id = <50>; cam_hw_pid = <10>; From ef1adb46651d2dc24187b05ee296cf6517d5ac4d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 6 Jun 2024 16:09:52 -0700 Subject: [PATCH 192/274] CAMX: Snap for drop 06/06/2024 mainline 1211 LA.VENDOR.15.4.0.AU363 Change-Id: I31f884b927d5700842c610dc0a9a2c1588ad7ac4 Signed-off-by: Haritha Chintalapati From 28b5baa021312fe21b63e8d4a5b03a8da22fdda9 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Sun, 9 Jun 2024 23:14:13 -0700 Subject: [PATCH 193/274] CAMX: Snap for drop 06/07/2024 mainline 1212 LA.VENDOR.15.4.0.AU363 Change-Id: I986be1fa76033f71aaac7cb55885272591ad6e78 Signed-off-by: Haritha Chintalapati From b87c3a36f6586db02eeefb78bea5e7edb67a8802 Mon Sep 17 00:00:00 2001 From: liji Date: Mon, 10 Jun 2024 23:46:49 -0700 Subject: [PATCH 194/274] ARM: dts: msm: Add IMX766 LPAI OIS module configuration Add IMX766 LPAI OIS sensor module configuration in Pakala MTP dtsi CRs-Fixed: 3797440 Change-Id: I58bd23e04483701401524d47fd886dc298c41884 Signed-off-by: liji --- sun-camera-sensor-mtp.dtsi | 58 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index 94ddcf35..1e993b1b 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -94,6 +94,20 @@ status = "ok"; }; + lpai_ois: qcom,ois1 { + cell-index = <9>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L1I>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio","cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 2960000>; + rgltr-max-voltage = <1200000 2960000>; + rgltr-load-current = <3000 220000>; + status = "ok"; + }; + eeprom_tof1: qcom,eeprom7 { cell-index = <7>; compatible = "qcom,eeprom"; @@ -330,6 +344,50 @@ status = "ok"; }; + qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&lpai_ois>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + }; &cam_cci1 { From 43bfffc59f552a3ab1a164af5dffb3c4bc3733b1 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 10 Jun 2024 23:46:53 -0700 Subject: [PATCH 195/274] CAMX: Snap for drop 06/10/2024 mainline 1213 LA.VENDOR.15.4.0.AU363 a47636f Merge 'ARM: dts: msm: Add IMX766 LPAI OIS module configuration' into camera-kernel.lnx.dev 2be5024 Merge 'ARM: dts: msm: Update OFE write ubwc config for Pakala' into camera-kernel.lnx.dev Change-Id: I2ddc97df76f1762e72ca084d1f510982ded87db8 Signed-off-by: Haritha Chintalapati From b8f306393d0944b5a72885eb8574f90d582f07ad Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 11 Jun 2024 18:03:30 -0700 Subject: [PATCH 196/274] CAMX: Snap for drop 06/11/2024 mainline 1214 LA.VENDOR.15.4.0.AU369 Change-Id: If2896ecc41bb89661401046764136b0fee9acd14 Signed-off-by: Haritha Chintalapati From 2638faa245551188047936fde58ba2a96f5e1451 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 13 Jun 2024 01:40:32 -0700 Subject: [PATCH 197/274] CAMX: Snap for drop 06/12/2024 mainline 1215 LA.VENDOR.15.4.0.AU369 Change-Id: I60b350539fa94748c3211225b8b74c91b69da779 Signed-off-by: Haritha Chintalapati From 700b16c67af9adfcb263b51929786a0e1adf1a55 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 17 Jun 2024 00:09:27 -0700 Subject: [PATCH 198/274] CAMX: Snap for drop 06/13/2024 mainline 1216 LA.VENDOR.15.4.0.AU369 Change-Id: I74d80ca3658ad48a262cc3eee89f31c2fc196d61 Signed-off-by: Haritha Chintalapati From 60393f1fb8988ab9fa2a1c662e39a432415ae591 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 17 Jun 2024 12:30:24 -0700 Subject: [PATCH 199/274] CAMX: Snap for drop 06/17/2024 mainline 1217 LA.VENDOR.15.4.0.AU369 Change-Id: I497950efdd3f056c4a10c81dfc8ed4c0c5de7d01 Signed-off-by: Haritha Chintalapati From 3e057bb21615e70534c2001b99af0cd2a035a816 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 18 Jun 2024 11:36:37 -0700 Subject: [PATCH 200/274] CAMX: Snap for drop 06/18/2024 mainline 1218 LA.VENDOR.15.4.0.AU375 Change-Id: I8e5733d05cd014d16081df5da5476242feb9444d Signed-off-by: Haritha Chintalapati From 682dc239a5a04f330c1d510a77e5a425add33828 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 19 Jun 2024 18:22:17 -0700 Subject: [PATCH 201/274] CAMX: Snap for drop 06/19/2024 mainline 1219 LA.VENDOR.15.4.0.AU375 Change-Id: I9f1a23175df89a070ad2559633c0c3ad85fd2332 Signed-off-by: Haritha Chintalapati From 1ecfa07361953e5babd0a962ec3bd512ce7d5a8e Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 20 Jun 2024 10:12:18 -0700 Subject: [PATCH 202/274] CAMX: Snap for drop 06/20/2024 mainline 1220 LA.VENDOR.15.4.0.AU375 Change-Id: Ifc34c9995f7503b36e242c46629e0178820c2d14 Signed-off-by: Haritha Chintalapati From 8c7ca3f8adb2aec5ad3ff768d2c0931434a63d82 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 24 Jun 2024 12:00:16 -0700 Subject: [PATCH 203/274] CAMX: Snap for drop 06/21/2024 mainline 1221 LA.VENDOR.15.4.0.AU375 Change-Id: Idf8bde2745faf431ec16fa638ee7272f8f2fb43e Signed-off-by: Haritha Chintalapati From cbd2eed2332a739360916fe303fc561e98068234 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 24 Jun 2024 12:00:20 -0700 Subject: [PATCH 204/274] CAMX: Snap for drop 06/24/2024 mainline 1222 LA.VENDOR.15.4.0.AU375 Change-Id: I134690de09b690729e074e1e7e71fc9efac55cbf Signed-off-by: Haritha Chintalapati From 66e0eaf0232371292650e4c68f9f25192f87bc76 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 25 Jun 2024 12:05:24 -0700 Subject: [PATCH 205/274] CAMX: Snap for drop 06/25/2024 mainline 1223 LA.VENDOR.15.4.0.AU383 Change-Id: Ifd0fef6744f2515058bf54b6a74e0360a528e81d Signed-off-by: Haritha Chintalapati From 11e6e68cde68a369634ab075437200b916955238 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 26 Jun 2024 14:21:50 -0700 Subject: [PATCH 206/274] CAMX: Snap for drop 06/26/2024 mainline 1224 LA.VENDOR.15.4.0.AU383 Change-Id: Ia95915131955980994924e9d963205bef39dac28 Signed-off-by: Haritha Chintalapati From cfa9e0beec9aeb8c468050a04b8d2e074bca488c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 27 Jun 2024 23:42:19 -0700 Subject: [PATCH 207/274] CAMX: Snap for drop 06/27/2024 mainline 1225 LA.VENDOR.15.4.0.AU383 Change-Id: I4e9ae1289592100f5a303710a62a67fe59d6062f Signed-off-by: Haritha Chintalapati From d07f033157e4a4bc1763f0789b68df7747d00643 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 1 Jul 2024 19:09:27 -0700 Subject: [PATCH 208/274] CAMX: Snap for drop 06/28/2024 mainline 1226 LA.VENDOR.15.4.0.AU383 Change-Id: I6453ea8fbdb8ea40885530abe227144822480eb6 Signed-off-by: Haritha Chintalapati From 0aee48892aee7a61f89bde3b762fb8f8238b7411 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 1 Jul 2024 19:09:30 -0700 Subject: [PATCH 209/274] CAMX: Snap for drop 07/01/2024 mainline 1227 LA.VENDOR.15.4.0.AU383 Change-Id: I3d8727d7f1308500547f7920c6a4ec66d45f10a0 Signed-off-by: Haritha Chintalapati From 766308f81fbb3a95c4c6e9446da858b429b1a5f5 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 5 Jul 2024 13:56:23 -0700 Subject: [PATCH 210/274] CAMX: Snap for drop 07/02/2024 mainline 1228 LA.VENDOR.15.4.0.AU383 Change-Id: I87fb0d618bd9e5cde58711fbbe78a6b67f987cb4 Signed-off-by: Haritha Chintalapati From 3096fc486aec7f907d7200ee46a61e7f8f4c8295 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 5 Jul 2024 13:56:25 -0700 Subject: [PATCH 211/274] CAMX: Snap for drop 07/05/2024 mainline 1230 LA.VENDOR.15.4.0.AU393 Change-Id: I67168b53d5028db58ee7792a54c1cb6beb18ca70 Signed-off-by: Haritha Chintalapati From d40e68e229b0b324ba8e28a2191b7b5ce895839a Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 8 Jul 2024 18:59:27 -0700 Subject: [PATCH 212/274] CAMX: Snap for drop 07/08/2024 mainline 1231 LA.VENDOR.15.4.0.AU393 Change-Id: I013658b5464133518f82255c0a993954edd5e176 Signed-off-by: Haritha Chintalapati From b3a62805ef49bf8aadac39d6b92279826756677d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 9 Jul 2024 17:15:31 -0700 Subject: [PATCH 213/274] CAMX: Snap for drop 07/09/2024 mainline 1232 LA.VENDOR.15.4.0.AU396 Change-Id: I0ddae473cfb3f3a7959bf1e248800070fd19d4bb Signed-off-by: Haritha Chintalapati From 19dc65609e5352041cf6ff38d40fe8be7b02aa26 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 10 Jul 2024 17:37:47 -0700 Subject: [PATCH 214/274] CAMX: Snap for drop 07/10/2024 mainline 1233 LA.VENDOR.15.4.0.AU396 Change-Id: I5a1bdb07668ed9f633932b886689b1309bca5dc1 Signed-off-by: Haritha Chintalapati From 9dc35054cd2fa96faf206e657eec76549d87b327 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 11 Jul 2024 11:07:15 -0700 Subject: [PATCH 215/274] CAMX: Snap for drop 07/11/2024 mainline 1234 LA.VENDOR.15.4.0.AU396 Change-Id: I3cfb07dcd17ac9fec6777f8364c1d9834f4fb7c4 Signed-off-by: Haritha Chintalapati From 909581ba7c0c3201a06c2e960a4e05d81501940b Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 12 Jul 2024 10:07:38 -0700 Subject: [PATCH 216/274] CAMX: Snap for drop 07/12/2024 mainline 1235 LA.VENDOR.15.4.0.AU396 Change-Id: Ifa0b62f785093f9c2e10827bc6ded98cdb19651e Signed-off-by: Haritha Chintalapati From ce7eabcfaaeb923d5c1fbaaa2103294056bacf13 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 15 Jul 2024 13:07:09 -0700 Subject: [PATCH 217/274] CAMX: Snap for drop 07/15/2024 mainline 1236 LA.VENDOR.15.4.0.AU396 Change-Id: I0b943eb07a28ee480c4d7e2175efc85fe525aac5 Signed-off-by: Haritha Chintalapati From 53c2a39734fc7cef05e96fafed33bd24878cd428 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 16 Jul 2024 17:37:10 -0700 Subject: [PATCH 218/274] CAMX: Snap for drop 07/16/2024 mainline 1237 LA.VENDOR.15.4.0.AU402 Change-Id: I8c38e21a4ef72b7133c0172ebcedf481fa3b8a3a Signed-off-by: Haritha Chintalapati From d156c92d31ea979ffc347605ae8221fc0c6c639f Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 17 Jul 2024 08:37:06 -0700 Subject: [PATCH 219/274] CAMX: Snap for drop 07/17/2024 mainline 1238 LA.VENDOR.15.4.0.AU402 Change-Id: Ia84a0cde6ab1aa7e3f0dfa6b8ebb54884c53ede2 Signed-off-by: Haritha Chintalapati From 29e9e7351f81cd37928f86cf2a675d4bf113b7a0 Mon Sep 17 00:00:00 2001 From: Lokesh Kumar Aakulu Date: Thu, 18 Jul 2024 09:37:08 -0700 Subject: [PATCH 220/274] ARM: dts: msm: Reduce SE8 CLK to operate in lowSVS To handle power regression at SE8 end reduce SCL clock, which makes the QUP clock domain to run in LowSVS instead of SVS. And the theoritical latency calculated for this change is minimal, around 0.3 msec for 200 xfers. CRs-Fixed: 3859750 Change-Id: I256e745a6edbdb356b297cf4d8909ca214840120 Signed-off-by: Lokesh Kumar Aakulu --- sun-camera-sensor-cdp.dtsi | 4 ++-- sun-camera-sensor-mtp.dtsi | 4 ++-- sun-camera-sensor-qrd.dtsi | 4 ++-- sun-camera-sensor-rumi.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi index 94ddcf35..ec137d95 100644 --- a/sun-camera-sensor-cdp.dtsi +++ b/sun-camera-sensor-cdp.dtsi @@ -585,8 +585,8 @@ }; &i3c3 { - se-clock-frequency = <100000000>; - i3c-scl-hz = <12500000>; + se-clock-frequency = <64000000>; + i3c-scl-hz = <8300000>; dfs-index = <0>; i2c-scl-hz = <1000000>; qcom,pm-ctrl-client; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index 1e993b1b..7287c5ca 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -643,8 +643,8 @@ }; &i3c3 { - se-clock-frequency = <100000000>; - i3c-scl-hz = <12500000>; + se-clock-frequency = <64000000>; + i3c-scl-hz = <8300000>; dfs-index = <0>; i2c-scl-hz = <1000000>; qcom,pm-ctrl-client; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi index 94ddcf35..ec137d95 100644 --- a/sun-camera-sensor-qrd.dtsi +++ b/sun-camera-sensor-qrd.dtsi @@ -585,8 +585,8 @@ }; &i3c3 { - se-clock-frequency = <100000000>; - i3c-scl-hz = <12500000>; + se-clock-frequency = <64000000>; + i3c-scl-hz = <8300000>; dfs-index = <0>; i2c-scl-hz = <1000000>; qcom,pm-ctrl-client; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi index 94ddcf35..ec137d95 100644 --- a/sun-camera-sensor-rumi.dtsi +++ b/sun-camera-sensor-rumi.dtsi @@ -585,8 +585,8 @@ }; &i3c3 { - se-clock-frequency = <100000000>; - i3c-scl-hz = <12500000>; + se-clock-frequency = <64000000>; + i3c-scl-hz = <8300000>; dfs-index = <0>; i2c-scl-hz = <1000000>; qcom,pm-ctrl-client; From e49456806929b25ad10f36aa8817e142235fa66d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 18 Jul 2024 11:07:08 -0700 Subject: [PATCH 221/274] CAMX: Snap for drop 07/18/2024 mainline 1239 LA.VENDOR.15.4.0.AU402 b75c777 Merge 'ARM: dts: msm: Reduce SE8 CLK to operate in lowSVS' into camera-kernel.lnx.dev Change-Id: Icf44d50928d69342a372f5ef6ac3f53e109f3436 Signed-off-by: Haritha Chintalapati From 17ec1968e6e1795ebae9ddb921eccdcdb5fc0ba1 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 19 Jul 2024 11:07:09 -0700 Subject: [PATCH 222/274] CAMX: Snap for drop 07/19/2024 mainline 1240 LA.VENDOR.15.4.0.AU402 Change-Id: Ia9a388f253925d540d5be2eb10b6b90e753a2314 Signed-off-by: Haritha Chintalapati From dd542900b0cfd184955e0872e36f98476fbd64ad Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 22 Jul 2024 14:37:07 -0700 Subject: [PATCH 223/274] CAMX: Snap for drop 07/22/2024 mainline 1241 LA.VENDOR.15.4.0.AU402 Change-Id: I98be57e7502cf96bb2a2c0ee099e51bf6e0a6e92 Signed-off-by: Haritha Chintalapati From 1ef82244859dc93811ff254420adcfc1673a333a Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 24 Jul 2024 12:37:10 -0700 Subject: [PATCH 224/274] CAMX: Snap for drop 07/23/2024 mainline 1242 LA.VENDOR.15.4.0.AU402 Change-Id: I21b38ceaeff5479443103daecd68004ffa4d3bfd Signed-off-by: Haritha Chintalapati From 901af30bcce5ebc5fbe07e7f457efff54860b7ba Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 24 Jul 2024 12:37:12 -0700 Subject: [PATCH 225/274] CAMX: Snap for drop 07/24/2024 mainline 1243 LA.VENDOR.15.4.0.AU402 Change-Id: I9efaaef71c6b595d7999b8eaa4e30a3a064bebb1 Signed-off-by: Haritha Chintalapati From f660d0ac9fec5805a78c173ad44d705f5be95866 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 25 Jul 2024 17:07:38 -0700 Subject: [PATCH 226/274] CAMX: Snap for drop 07/25/2024 mainline 1244 LA.VENDOR.15.4.0.AU417 Change-Id: I754353a8a148439a1dc5626695a61ca733f1c212 Signed-off-by: Haritha Chintalapati From 342e94f61fea9881f1117519f7b8b6965e61bf35 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 29 Jul 2024 16:38:09 -0700 Subject: [PATCH 227/274] CAMX: Snap for drop 07/29/2024 mainline 1245 LA.VENDOR.15.4.0.AU417 Change-Id: I6ea06d40b08484bd79b6ec23e4fe9f457c69b515 Signed-off-by: Haritha Chintalapati From e900b84a6c1bae12f04a49d921f14a7b7ffe2b37 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 29 Jul 2024 22:20:08 -0700 Subject: [PATCH 228/274] CAMX: Snap for drop 07/29/2024 mainline 1246 LA.VENDOR.15.4.0.AU417 Change-Id: If893daa2a40275a7e4b08d77c8f6c09b0f9a7ed2 Signed-off-by: Haritha Chintalapati From 800a670e4e2bcb10f628cf9fe6f21b027f1e1f8c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 30 Jul 2024 22:38:08 -0700 Subject: [PATCH 229/274] CAMX: Snap for drop 07/30/2024 mainline 1247 LA.VENDOR.15.4.0.AU418 Change-Id: I4433f1789c22883af652fcf68ee64215b8e5e7ca Signed-off-by: Haritha Chintalapati From f919ae8d3f94f06102c3e00cd5b9a4ebbc607e7c Mon Sep 17 00:00:00 2001 From: Haochen Yang Date: Wed, 31 Jul 2024 15:38:08 -0700 Subject: [PATCH 230/274] ARM: dts: msm: Add support to update camera qos This change adds support to update static and smart camera qos. enable-secure-qos-update property specifies whether secure camera Qos update feature is enabled. CRs-Fixed: 3857947 Change-Id: I4c70f1be49a1e3bcda1ea2e4a73fbce3c130b6ab Signed-off-by: Haochen Yang --- bindings/msm-cam-cpas.txt | 5 +++++ sun-camera.dtsi | 1 + 2 files changed, 6 insertions(+) diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index 39a6c62d..c872a2cf 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -229,6 +229,11 @@ First Level Node - CAM CPAS device Definition: Client ID for camera caches. ID is used to differentiate the property of the cache like being Forget, Dealloc. +- enable-secure-qos-update + Usage: optional + Value type: + Definition: Bool property specifying whether secure camera Qos update feature is enabled. + - enable-smart-qos Usage: optional Value type: diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 726439eb..71300adc 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1734,6 +1734,7 @@ sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; sys-cache-uids = <71 72 73 74 75>; sys-cache-concur = <1 1 1 0 0>; + enable-secure-qos-update; enable-smart-qos; enable-cam-drv = <(CAM_DDR_DRV | CAM_CLK_DRV)>; rt-wr-priority-min = <4>; From 79dee7f64396cfb7a88fc64213611e601c9cc14c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 31 Jul 2024 18:08:08 -0700 Subject: [PATCH 231/274] CAMX: Snap for drop 07/31/2024 mainline 1248 LA.VENDOR.15.4.0.AU418 60658a5 Merge 'ARM: dts: msm: Add support to update camera qos' into camera-kernel.lnx.dev Change-Id: I382ad9696200ec6520ea13fc01c7742d85588bdd Signed-off-by: Haritha Chintalapati From 554527efcc03425129481fe25be80f60a03a8188 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 1 Aug 2024 15:08:07 -0700 Subject: [PATCH 232/274] CAMX: Snap for drop 08/01/2024 mainline 1249 LA.VENDOR.15.4.0.AU418 Change-Id: I7b734a22bf32fc8253adb6f05d70eac821172723 Signed-off-by: Haritha Chintalapati From 5b3153fe49563d76643103de87ae939c12a10121 Mon Sep 17 00:00:00 2001 From: Li Sha Lim Date: Mon, 5 Aug 2024 13:08:08 -0700 Subject: [PATCH 233/274] ARM: dts: msm: Remove camnoc reg from TFE In the past, TFE driver needed camnoc reg access in event of bus overflow. Now, there's no need for it with usage of CPAS APIs, so the reg entries for cam_camnoc_rt in TFE is removed. CRs-Fixed: 3865318 Change-Id: Iccb6619d82b9b8b34e937d32a3c628b151745c54 Signed-off-by: Li Sha Lim --- sun-camera.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 71300adc..074a2160 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -2647,10 +2647,9 @@ cam_vfe0: qcom,ife0@ac86000{ cell-index = <0>; compatible = "qcom,mc_tfe980"; - reg-names = "ife", "cam_camnoc_rt"; - reg = <0x0ac86000 0x10000>, - <0x0ad90000 0x9000>; - reg-cam-base = <0x86000 0x19000>; + reg-names = "ife"; + reg = <0x0ac86000 0x10000>; + reg-cam-base = <0x86000>; rt-wrapper-base = <0x86000>; interrupt-names = "tfe0"; interrupts = ; @@ -2726,10 +2725,9 @@ cam_vfe1: qcom,ife1@ac96000 { cell-index = <1>; compatible = "qcom,mc_tfe980"; - reg-names = "ife", "cam_camnoc_rt"; - reg = <0x0ac96000 0x10000>, - <0x0ad90000 0x9000>; - reg-cam-base = <0x96000 0x19000>; + reg-names = "ife"; + reg = <0x0ac96000 0x10000>; + reg-cam-base = <0x96000>; rt-wrapper-base = <0x86000>; interrupt-names = "tfe1"; interrupts = ; @@ -2805,10 +2803,9 @@ cam_vfe2: qcom,ife2@aca6000 { cell-index = <2>; compatible = "qcom,mc_tfe980"; - reg-names = "ife", "cam_camnoc_rt"; - reg = <0x0aca6000 0x10000>, - <0x0ad90000 0x9000>; - reg-cam-base = <0xa6000 0x19000>; + reg-names = "ife"; + reg = <0x0aca6000 0x10000>; + reg-cam-base = <0xa6000>; rt-wrapper-base = <0x86000>; interrupt-names = "tfe2"; interrupts = ; From 8491d7878d12b54d2f64be79428449378882c99c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 5 Aug 2024 13:08:22 -0700 Subject: [PATCH 234/274] CAMX: Snap for drop 08/05/2024 mainline 1250 LA.VENDOR.15.4.0.AU418 ac7a0e2 Merge 'ARM: dts: msm: Remove camnoc reg from TFE' into camera-kernel.lnx.dev Change-Id: Icc545568d3327ffd49230f90f0f7cdeea84da318 Signed-off-by: Haritha Chintalapati From f0ef78f8ade473e7031b2197a2222d79fa357a24 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 7 Aug 2024 00:38:07 -0700 Subject: [PATCH 235/274] CAMX: Snap for drop 08/06/2024 mainline 1251 LA.VENDOR.15.4.0.AU427 Change-Id: Ifc34e1aa94c3038c6087be6a274ab501c9c5c641 Signed-off-by: Haritha Chintalapati From 4e35d12d947653ea7a80752b5ffce1b8755b414c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 7 Aug 2024 15:08:05 -0700 Subject: [PATCH 236/274] CAMX: Snap for drop 08/07/2024 mainline 1252 LA.VENDOR.15.4.0.AU427 Change-Id: I96a636f3efb7b0d2e687a88a1ac07fdea96ce491 Signed-off-by: Haritha Chintalapati From 4c9044def2d9ad4e83972ff847d259066addf72a Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 8 Aug 2024 16:08:08 -0700 Subject: [PATCH 237/274] CAMX: Snap for drop 08/08/2024 mainline 1253 LA.VENDOR.15.4.0.AU427 Change-Id: I23a9ba558156220bbc77879d397e17b6bacc7337 Signed-off-by: Haritha Chintalapati From 4964693ec762f073589e2900a889dfb963b494a4 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 9 Aug 2024 17:07:08 -0700 Subject: [PATCH 238/274] CAMX: Snap for drop 08/09/2024 mainline 1254 LA.VENDOR.15.4.0.AU427 Change-Id: I51ab9765a2a1b583587ea0aaae9a74c7c1033729 Signed-off-by: Haritha Chintalapati From 162ce796b622702259103b36d73dc2972915785d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Tue, 13 Aug 2024 23:21:09 -0700 Subject: [PATCH 239/274] CAMX: Snap for drop 08/12/2024 mainline 1255 LA.VENDOR.15.4.0.AU427 Change-Id: If9b06bce894cc780b5da4166e958effc161e0ab9 Signed-off-by: Haritha Chintalapati From 3e3199acc7dc8f7e47ea4cb37a9b2f0409d2c17b Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 14 Aug 2024 17:07:36 -0700 Subject: [PATCH 240/274] CAMX: Snap for drop 08/14/2024 mainline 1256 LA.VENDOR.15.4.0.AU436 Change-Id: I6bc22f7744e0f1d4f2724d865d6cc4476dbf0644 Signed-off-by: Haritha Chintalapati From 689d8a01bab47cbf4e2e5b746f4fb32e50a5ae4c Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Wed, 14 Aug 2024 20:37:07 -0700 Subject: [PATCH 241/274] CAMX: Snap for drop 08/14/2024 mainline 1257 LA.VENDOR.15.4.0.AU436 Change-Id: I2bf95e1827ec3537ba90b1b1b8599c986c68faea Signed-off-by: Haritha Chintalapati From e352667b311a98af97da68aaf0d1f651d632e0e0 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Thu, 15 Aug 2024 22:37:09 -0700 Subject: [PATCH 242/274] ARM: dts: msm: adding canoe dtsi files This change will add new dtsi file for kaanapali. This is base change for smmu, cpas, jpeg, csid, ife, tpg. CRs-Fixed: 3818816 Change-Id: I00a39693f10c50663dc3c08539dfd736f3666813 Signed-off-by: Soumen Ghosh --- canoe-camera.dts | 21 + canoe-camera.dtsi | 3242 +++++++++++++++++++++++++++++++++++++++++++++ config/canoe.mk | 1 + 3 files changed, 3264 insertions(+) create mode 100644 canoe-camera.dts create mode 100644 canoe-camera.dtsi create mode 100644 config/canoe.mk diff --git a/canoe-camera.dts b/canoe-camera.dts new file mode 100644 index 00000000..1cee107b --- /dev/null +++ b/canoe-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "canoe-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. canoe SoC"; + compatible = "qcom,canoe"; + qcom,msm-id = <660 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/canoe-camera.dtsi b/canoe-camera.dtsi new file mode 100644 index 00000000..8d91f2ba --- /dev/null +++ b/canoe-camera.dtsi @@ -0,0 +1,3242 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio113"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio115"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio116"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio117"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio118"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci_i2c_scl3_active { + mux { + pins = "gpio164"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio164"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { + mux { + pins = "gpio111"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci_i2c_sda3_active { + mux { + pins = "gpio111"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio111"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { + mux { + pins = "gpio164"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio164"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda4_active: cci_i2c_sda4_active { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda4_suspend: cci_i2c_sda4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112"; + function = "cci_i2c_sda4"; + }; + + config { + pins = "gpio112"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl4_active: cci_i2c_scl4_active { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl4_suspend: cci_i2c_scl4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio153"; + function = "cci_i2c_scl4"; + }; + + config { + pins = "gpio153"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda5_active: cci_i2c_sda5_active { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda5_suspend: cci_i2c_sda5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio119"; + function = "cci_i2c_sda5"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl5_active: cci_i2c_scl5_active { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl5_suspend: cci_i2c_scl5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio120"; + function = "cci_i2c_scl5"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio89"; + function = "cam_mclk"; + }; + + config { + pins = "gpio89"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio89"; + function = "cam_mclk"; + }; + + config { + pins = "gpio89"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio90"; + function = "cam_mclk"; + }; + + config { + pins = "gpio90"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio90"; + function = "cam_mclk"; + }; + + config { + pins = "gpio90"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio91"; + function = "cam_asc_mclk2"; + }; + + config { + pins = "gpio91"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio91"; + function = "cam_asc_mclk2"; + }; + + config { + pins = "gpio91"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio92"; + function = "cam_mclk"; + }; + + config { + pins = "gpio92"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio92"; + function = "cam_mclk"; + }; + + config { + pins = "gpio92"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio93"; + function = "cam_asc_mclk4"; + }; + + config { + pins = "gpio93"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio93"; + function = "cam_asc_mclk4"; + }; + + config { + pins = "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio94"; + function = "cam_mclk"; + }; + + config { + pins = "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio94"; + function = "cam_mclk"; + }; + + config { + pins = "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + + config { + pins = "gpio96"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + + config { + pins = "gpio96"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_active: cam_sensor_mclk7_active { + /* MCLK7 */ + mux { + pins = "gpio95"; + function = "cam_mclk"; + }; + + config { + pins = "gpio95"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk7_suspend: cam_sensor_mclk7_suspend { + /* MCLK7 */ + mux { + pins = "gpio95"; + function = "cam_mclk"; + }; + + config { + pins = "gpio95"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst7: cam_sensor_active_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst7: cam_sensor_suspend_rst7 { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_i3cSelect_active: cam_sensor_i3cSelect_active { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_i3cSelect_suspend: cam_sensor_i3cSelect_suspend { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_ponv_rear_active: cam_sensor_ponv_rear_active { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_ponv_rear_suspend: cam_sensor_ponv_rear_suspend { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam-i3c-id-table { + i3c-sensor-id-table = <0x1B0 0x0858>; + i3c-eeprom-id-table = <>; + i3c-actuator-id-table = <>; + i3c-ois-id-table = <>; + status = "disabled"; + }; + + cam_csiphy0: qcom,csiphy0@ada9000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0ada9000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1a9000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@adab000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0adab000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1ab000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@adad000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0adad000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1ad000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L3I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1256000 912000>; + rgltr-load-current = <0 6200 88200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@adaf000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0adaf000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1af000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@adb1000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0adb1000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1b1000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L3I>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1256000 912000>; + rgltr-load-current = <0 6200 88200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@adb3000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0adb3000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1b3000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L3G>; + csi-vdd-0p9-supply = <&L1F>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1256000 920000>; + rgltr-load-current = <0 6200 88200>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac7b000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7b000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac7c000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7c000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7c000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci2: qcom,cci2@ac7d000 { + cell-index = <2>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7d000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7d000>; + interrupt-names = "CCI2"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_2_clk_src", + "cci_2_clk"; + clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; + src-clock-name = "cci_2_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>; + pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>; + pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>; + pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci2: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci2: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci2: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci2: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife: msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1C00 0x00>; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + cam-smmu-label = "ife"; + multiple-client-devices; + memory-region = <&cam_smmu_ife_resv_region>; + cam_smmu_ife_resv_region: cam_smmu_ife_resv_region { + iommu-addresses = <&msm_cam_smmu_ife 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_ife 0xf 0xfff00000 0x0 0x100000>; + }; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg: msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x00>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + memory-region = <&cam_smmu_jpeg_resv_region>; + cam_smmu_jpeg_resv_region: cam_smmu_jpeg_resv_region { + iommu-addresses = <&msm_cam_smmu_jpeg 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_jpeg 0x0 0xfff00000 0xf 0x00100000>; + }; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp: msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1800 0xC0>, + <&apps_smmu 0x1980 0x00>; + cam-smmu-label = "icp", "icp1"; + multiple-client-devices; + multiple-same-region-clients = "icp", "icp1"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + memory-region = <&cam_smmu_icp_resv_region>; + cam_smmu_icp_resv_region: cam_smmu_icp_resv_region { + iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1600000>; + }; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared1 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0x80e00000 */ + iova-region-start = <0x0 0x80e00000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-shared2 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xb9200000 */ + iova-region-start = <0x0 0xb9200000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region1 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80400000 */ + iova-region-start = <0x0 0x80400000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80500000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80400000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-region-fwuncached-region2 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80900000 */ + iova-region-start = <0x0 0x80900000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80a00000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80900000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x300000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + + iova-mem-region-ipc-hwmutex { + iova-region-name = "ipc_hwmutex"; + iova-region-start = <0x0 0x80101000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x2>; + phy-addr = <0x1f4b000>; + }; + + iova-mem-region-global_cntr { + iova-region-name = "global_cntr"; + iova-region-start = <0x0 0x80102000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x4>; + phy-addr = <0xc220000>; + }; + iova-mem-region-llcc-register { + iova-region-name = "llcc-register"; + iova-region-start = <0x0 0x80103000>; + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x5>; + phy-addr = <0x34C00000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf1600000 */ + iova-region-start = <0x0 0xf1600000>; + /* Length: 0xf0ea00000 */ + iova-region-len = <0xf 0x0ea00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0x80000000 */ + iova-region-start = <0x0 0x80000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x37790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm: msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + multiple-client-devices; + memory-region = <&cam_smmu_cdm_resv_region>; + cam_smmu_cdm_resv_region: cam_smmu_cdm_resv_region { + iommu-addresses = <&msm_cam_smmu_cdm 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_cdm 0x0 0xfff00000 0xf 0x00100000>; + }; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + qti,smmu-proxy-cb-id = ; + }; + }; + + qcom,cam-cpas@900B000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh", "cam_cesta"; + reg = <0x0 0x0900B000 0x0 0x1000>, + <0x0 0x09117000 0x0 0x10000>, + <0x0 0x09405000 0x0 0x10000>, + <0x0 0x0bbf0000 0x0 0x1f00>, + <0x0 0x09548000 0x0 0x1E00>; + reg-cam-base = <0xB000 0x117000 0x405000 0x0bbf0000 0x09548000>; + interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt"; + interrupts = , + ; + camnoc-axi-min-ib-bw = <3000000000>; + cam-max-rt-axi-bw = <0x3 0x60447100>; + regulator-names = "top-gdsc"; + top-gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_top_fast_ahb_clk", + "camnoc_rt_axi_clk_src", + "camnoc_rt_axi_clk", + "camnoc_nrt_axi_clk", + "cam_cc_drv_xo_clk", + "cam_cc_pll0", + "cam_cc_qdss_debug_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>, + <&camcc CAM_CC_PLL0>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 56470588 0 0 0 213333333 0 200000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 480000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 480000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 480000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 480000000 0 0 0 0 0>; + clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_rt_axi_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = , + ; + cam-icc-path-names = "cam_ahb"; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv", + "cam_sf_0", + "cam_sf_icp"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>, + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF + &mc_virt SLAVE_EBI1>; + rpmh-bcm-info = <13 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", + "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", + "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; + sys-cache-uids = <71 72 73 74 75>; + sys-cache-concur = <1 1 1 0 0>; + enable-smart-qos; + enable-cam-drv = <(CAM_DDR_DRV | CAM_CLK_DRV)>; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv"; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = + "cam_sf_icp"; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x4830>; + priority-lut-high-offset = <0x4834>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x4A30>; + priority-lut-high-offset = <0x4A34>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_rt4_rd: level1-rt4-rd { + cell-index = <11>; + node-name = "level1-rt4-cdm-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <12>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_wr: level1-nrt6-wr { + cell-index = <13>; + node-name = "level1-nrt6-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_rd: level1-nrt6-rd { + cell-index = <14>; + node-name = "level1-nrt6-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt5_rd: level1-nrt5-rd { + cell-index = <15>; + node-name = "level1-nrt5-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt4_rd: level1-nrt4-rd { + cell-index = <16>; + node-name = "level1-nrt4-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + }; + + level0-nodes { + level-index = <0>; + ife0_full_rdi_raw_pdaf1_wr: ife0-full-rdi-raw-pdaf1-wr { + cell-index = <17>; + node-name = "ife0-full-rdi-raw-pdaf1-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_full_rdi_raw_pdaf1_wr: ife1-full-rdi-raw-pdaf1-wr { + cell-index = <18>; + node-name = "ife1-full-rdi-raw-pdaf1-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_full_rdi_raw_pdaf1_wr: ife2-full-rdi-raw-pdaf1-wr { + cell-index = <19>; + node-name = "ife2-full-rdi-raw-pdaf1-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pdaf_fd_linear_wr: ife0-pdaf-fd-linear-wr { + cell-index = <20>; + node-name = "ife0-pdaf-fd-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_pdaf_fd_linear_wr: ife1-pdaf-fd-linear-wr { + cell-index = <21>; + node-name = "ife1-pdaf-fd-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_pdaf_fd_linear_wr: ife2-pdaf-fd-linear-wr { + cell-index = <22>; + node-name = "ife2-pdaf-fd-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife3_rdi_stats_wr: ife3-rdi-stats-wr { + cell-index = <23>; + node-name = "ife3-rdi-stats-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife4_rdi_stats_wr: ife4-rdi-stats-wr { + cell-index = <24>; + node-name = "ife4-rdi-stats-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife0_pdaf_stats_wr: ife0-pdaf-stats-wr { + cell-index = <25>; + node-name = "ife0-pdaf-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_stats_wr: ife1-pdaf-stats-wr { + cell-index = <26>; + node-name = "ife1-pdaf-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_stats_wr: ife2-pdaf-stats-wr { + cell-index = <27>; + node-name = "ife2-pdaf-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <28>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <29>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <30>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <31>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_rd>; + }; + + rt_cdm4_all_rd: rt-cdm4-all-rd { + cell-index = <32>; + node-name = "rt-cdm4-all-rd"; + client-name = "rt-cdm4"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt4_rd>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <33>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <34>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <35>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <36>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <37>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <38>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <39>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <40>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + icp1_all_rd: icp1-all-rd { + cell-index = <41>; + node-name = "icp1-all-rd"; + client-name = "icp1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + ofe0_linear_wr: ofe0-linear-wr { + cell-index = <42>; + node-name = "ofe0-linear-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt2_wr>; + }; + + ofe0_in_rd: ofe0-in-rd { + cell-index = <43>; + node-name = "ofe0-in-rd"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt4_rd>; + }; + + ofe0_ubwc_wr: ofe0-ubwc-wr { + cell-index = <44>; + node-name = "ofe0-ubwc-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <45>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <46>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt5_rd>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@9147000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0 0x09147000 0x0 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x147000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <9>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@9148000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0 0x09148000 0x0 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x148000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <10>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@9149000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0 0x09149000 0x0 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x149000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <11>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@914A000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0 0x0914A000 0x0 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x14A000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <8>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm4@914B000 { + cell-index = <4>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0 0x0914B000 0x0 0x580>; + reg-names = "rt-cdm4"; + reg-cam-base = <0x14B000>; + interrupt-names = "rt-cdm4"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife4"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <12>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "mc_tfe"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@9253000 { + cell-index = <0>; + compatible = "qcom,csid1080"; + reg-names = "csid"; + reg = <0x0 0x09253000 0x0 0x5e80>; + reg-cam-base = <0x253000>; + rt-wrapper-base = <0x151000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0 0>, + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@9151000 { + cell-index = <0>; + compatible = "qcom,mc_tfe1080"; + reg-names = "ife"; + reg = <0x0 0x09151000 0x0 0x20000>; + reg-cam-base = <0x151000>; + rt-wrapper-base = <0x151000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "gdsc", "tfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe0-supply = <&cam_cc_tfe_0_gdsc>; + clock-names = + "tfe_0_main_fast_ahb", + "tfe_0_clk_src", + "tfe_0_main_clk", + "cam_cc_camnoc_rt_tfe_0_main_clk", + "tfe_0_bayer_fast_ahb", + "tfe_0_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_CLK>; + clock-rates = + <0 360280000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 630000000 0 0 0 0>, + <0 716000000 0 0 0 0>, + <0 833000000 0 0 0 0>, + <0 833000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_0_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <0 16 4>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@9263000 { + cell-index = <1>; + compatible = "qcom,csid1080"; + reg-names = "csid"; + reg = <0x0 0x09263000 0x0 0x5e80>; + reg-cam-base = <0x263000>; + rt-wrapper-base = <0x151000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0 0>, + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@9171000 { + cell-index = <1>; + compatible = "qcom,mc_tfe1080"; + reg-names = "ife"; + reg = <0x0 0x09171000 0x0 0x20000>; + reg-cam-base = <0x171000>; + rt-wrapper-base = <0x151000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "gdsc", "tfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe1-supply = <&cam_cc_tfe_1_gdsc>; + clock-names = + "tfe_1_main_fast_ahb", + "tfe_1_clk_src", + "tfe_1_main_clk", + "cam_cc_camnoc_rt_tfe_1_main_clk", + "tfe_1_bayer_fast_ahb", + "tfe_1_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_CLK>; + clock-rates = + <0 360280000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 630000000 0 0 0 0>, + <0 716000000 0 0 0 0>, + <0 833000000 0 0 0 0>, + <0 833000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_1_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <1 17 5>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@9273000 { + cell-index = <2>; + compatible = "qcom,csid1080"; + reg-names = "csid"; + reg = <0x0 0x09273000 0x0 0x5e80>; + reg-cam-base = <0x273000>; + rt-wrapper-base = <0x151000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0 0>, + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@9191000 { + cell-index = <2>; + compatible = "qcom,mc_tfe1080"; + reg-names = "ife"; + reg = <0x0 0x09191000 0x0 0x20000>; + reg-cam-base = <0x191000>; + rt-wrapper-base = <0x151000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "gdsc", "tfe2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe2-supply = <&cam_cc_tfe_2_gdsc>; + clock-names = + "tfe_2_main_fast_ahb", + "tfe_2_clk_src", + "tfe_2_main_clk", + "cam_cc_camnoc_rt_tfe_2_main_clk", + "tfe_2_bayer_fast_ahb", + "tfe_2_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_CLK>; + clock-rates = + <0 360280000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 630000000 0 0 0 0>, + <0 716000000 0 0 0 0>, + <0 833000000 0 0 0 0>, + <0 833000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_2_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <2 18 6>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@92d3000 { + cell-index = <3>; + compatible = "qcom,csid-lite1080"; + reg-names = "csid-lite"; + reg = <0x0 0x092d3000 0x0 0x3880>; + reg-cam-base = <0x2d3000>; + rt-wrapper-base = <0x2d1000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@92dc000 { + cell-index = <3>; + compatible = "qcom,vfe-lite1080"; + reg-names = "ife-lite"; + reg = <0x0 0x092dc000 0x0 0x7000>; + reg-cam-base = <0x2dc000>; + rt-wrapper-base = <0x2d1000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <19>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@92e7000 { + cell-index = <4>; + compatible = "qcom,csid-lite1080"; + reg-names = "csid-lite"; + reg = <0x0 0x092e7000 0x0 0x3880>; + reg-cam-base = <0x2e7000>; + rt-wrapper-base = <0x2d1000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@92f0000 { + cell-index = <4>; + compatible = "qcom,vfe-lite1080"; + reg-names = "ife-lite"; + reg = <0x0 0x092f0000 0x0 0x7000>; + reg-cam-base = <0x2f0000>; + rt-wrapper-base = <0x2d1000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <20>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@93fd000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0x0 0x093fd000 0x0 0x400>, + <0x0 0x0900b000 0x0 0x1000>; + reg-cam-base = <0x3fd000 0x0b000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@93fe000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0x0 0x093fe000 0x0 0x400>, + <0x0 0x0900b000 0x0 0x1000>; + reg-cam-base = <0x3fe000 0x0b000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@93ff000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0x0 0x093ff000 0x0 0x400>, + <0x0 0x0900b000 0x0 0x1000>; + reg-cam-base = <0x3ff000 0xb000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp0 { + compatible = "qcom,cam-icp0"; + cell-index = <0>; + compat-hw-name = "qcom,icp0", + "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + qcom,cam-icp1 { + compatible = "qcom,cam-icp1"; + cell-index = <1>; + compat-hw-name = "qcom,icp1", + "qcom,ofe"; + num-icp = <1>; + num-ofe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp0: qcom,icp0@900d000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0 0x0900e000 0x0 0x1000>, + <0x0 0x09011000 0x0 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0xe000 0x11000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_0_AHB_CLK>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 500000000 0 0>, + <0 600000000 0 0>, + <0 740000000 0 0>, + <0 875000000 0 0>, + <0 1000000000 0 0>, + <0 1000000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x3f083 0x3f083>; + ubwc-ipe-write-cfg = <0x1620F 0x1620F>; + qos-val = <0x808>; + fw-pas-id = <33>; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_icp1: qcom,icp1@902d000 { + cell-index = <1>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0 0x0902e000 0x0 0x1000>, + <0x0 0x09031000 0x0 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x2E000 0x31000>; + interrupt-names = "icp1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_2_mem>; + clock-names = + "icp_1_ahb_clk", + "icp_1_clk_src", + "icp_1_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_1_AHB_CLK>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 500000000 0 0>, + <0 600000000 0 0>, + <0 740000000 0 0>, + <0 875000000 0 0>, + <0 1000000000 0 0>, + <0 1000000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_1_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_1"; + ubwc-ofe-fetch-cfg = <0x3f083 0x3f083>; + ubwc-ofe-write-cfg = <0x1620F 0x1620F>; + qos-val = <0x808>; + fw-pas-id = <50>; + cam_hw_pid = <10>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@90d7000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0x0 0x090d7000 0x0 0x20000>; + reg-names = "ipe0_top"; + reg-cam-base = <0xd7000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_camnoc_nrt_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>; + clock-rates = + <0 0 0 332500000 0 0 0>, + <0 0 0 475000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 26 27>; + status = "ok"; + }; + + cam_ofe: qcom,ofe@9057000 { + cell-index = <0>; + compatible = "qcom,cam-ofe"; + reg = <0x0 0x09057000 0x0 0x40000>; + reg-names = "ofe0_top"; + reg-cam-base = <0x57000>; + regulator-names = "ofe0-vdd"; + ofe0-vdd-supply = <&cam_cc_ofe_gdsc>; + clock-names = + "camnoc_nrt_ofe_anchor", + "camnoc_nrt_ofe_hdr", + "ofe_clk_src", + "ofe_main_clk", + "camnoc_nrt_ofe_main_clk", + "ofe_ahb_clk", + "ofe_anchor_clk", + "ofe_anchor_fast_ahb", + "ofe_hdr_fast_ahb", + "ofe_hdr_clk", + "ofe_main_fast_ahb"; + clocks = + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_OFE_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>, + <&camcc CAM_CC_OFE_AHB_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>; + clock-rates = + <338800000 0 0 0 0 0 0 0 0>, + <484000000 0 0 0 0 0 0 0 0>, + <586000000 0 0 0 0 0 0 0 0>, + <688000000 0 0 0 0 0 0 0 0>, + <841000000 0 0 0 0 0 0 0 0>, + <841000000 0 0 0 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ofe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <13 28 6>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@904d000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc_nrt"; + reg = <0x0 0x904d000 0x0 0x1000>, + <0x0 0x09117000 0x0 0x10000>; + reg-cam-base = <0x4d000 0x117000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@904e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc_nrt"; + reg = <0x0 0x0904e000 0x0 0x1000>, + <0x0 0x09117000 0x0 0x10000>; + reg-cam-base = <0x4e000 0x117000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +}; diff --git a/config/canoe.mk b/config/canoe.mk new file mode 100644 index 00000000..24674e78 --- /dev/null +++ b/config/canoe.mk @@ -0,0 +1 @@ +dtbo-$(CONFIG_ARCH_CANOE) := canoe-camera.dtbo From 7db117e64b446b150d9bde15bb119c4671403f12 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Thu, 15 Aug 2024 23:37:40 -0700 Subject: [PATCH 243/274] CAMX: Snap for drop 08/15/2024 mainline 1258 LA.VENDOR.15.4.0.AU436 e1a7cf4 Merge 'ARM: dts: msm: adding canoe dtsi files' into camera-kernel.lnx.dev Change-Id: I273d8000d455dd23b9fa28a74f8472a75a84cb83 Signed-off-by: Haritha Chintalapati From 4997203e4f69b909b5b107dc03e62f90edb5795d Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Fri, 16 Aug 2024 18:07:08 -0700 Subject: [PATCH 244/274] CAMX: Snap for drop 08/16/2024 mainline 1259 LA.VENDOR.15.4.0.AU436 Change-Id: I4064e410167a247d26f767205e47a68d0a71bdde Signed-off-by: Haritha Chintalapati From 52f001f5e925b51863ac391b36eb5f12e0f25491 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Mon, 19 Aug 2024 11:37:37 -0700 Subject: [PATCH 245/274] ARM: dts: msm: Remove synx support for ICP1 on sun Remove synx support for ICP1 core on sun. Synx on ICP1 is not completely supported yet leading to warning log spew. CRs-Fixed: 3889739 Change-Id: I3023652b36e862b214bf6d2d6d53e4797f5c77a5 Signed-off-by: Karthik Anantha Ram --- sun-camera.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 074a2160..77c1391f 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -3115,7 +3115,6 @@ icp_pc_en; icp_use_pil; ipe_bps_pc_en; - synx_signaling_en; }; cam_icp0: qcom,icp0@ac05000 { From 13903d5eeac1d7830a5180a9bb11de3bb41614b1 Mon Sep 17 00:00:00 2001 From: Haritha Chintalapati Date: Mon, 19 Aug 2024 11:37:40 -0700 Subject: [PATCH 246/274] CAMX: Snap for drop 08/19/2024 mainline 1260 LA.VENDOR.15.4.0.AU436 58c7290 Merge 'ARM: dts: msm: Remove synx support for ICP1 on sun' into camera-kernel.lnx.dev Change-Id: I552cfea11b60b301cac47d94ab3830ac4916f1b4 Signed-off-by: Haritha Chintalapati From 78ff4ce784f67a04f2d720c6c36600b86df718bf Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Mon, 20 May 2024 16:56:28 -0700 Subject: [PATCH 247/274] ARM: dts: msm: adding license information There was missing license information adding this to all files. Licence information required for these files. CRs-Fixed: 3818810 Change-Id: I743432f8cb1ee997422dfab6287f07739e6464d4 Signed-off-by: Soumen Ghosh (cherry picked from commit 3317f10320b719d76128e13e77eb691dc6cd18e7) --- sun-camera-sensor-cdp.dts | 5 +++++ sun-camera-sensor-cdp.dtsi | 5 +++++ sun-camera-sensor-mtp.dts | 5 +++++ sun-camera-sensor-mtp.dtsi | 5 +++++ sun-camera-sensor-qrd.dts | 5 +++++ sun-camera-sensor-qrd.dtsi | 5 +++++ sun-camera-sensor-rumi.dts | 5 +++++ sun-camera-sensor-rumi.dtsi | 5 +++++ sun-camera.dts | 5 +++++ sun-camera.dtsi | 5 +++++ 10 files changed, 50 insertions(+) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 83f1e76b..f37362f3 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi index ec137d95..d617d9c8 100644 --- a/sun-camera-sensor-cdp.dtsi +++ b/sun-camera-sensor-cdp.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 54da5b60..4432743b 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index 7287c5ca..ba531f25 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 5ee419f5..7a25dd6f 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi index ec137d95..d617d9c8 100644 --- a/sun-camera-sensor-qrd.dtsi +++ b/sun-camera-sensor-qrd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera-sensor-rumi.dts b/sun-camera-sensor-rumi.dts index fa7b4141..46a70d37 100644 --- a/sun-camera-sensor-rumi.dts +++ b/sun-camera-sensor-rumi.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi index ec137d95..d617d9c8 100644 --- a/sun-camera-sensor-rumi.dtsi +++ b/sun-camera-sensor-rumi.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera.dts b/sun-camera.dts index 8e77a5d3..b7b0e6ae 100644 --- a/sun-camera.dts +++ b/sun-camera.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 77c1391f..7adef2b5 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include #include From 51d9de9232af2b8851ba02e5796f3545f0710b91 Mon Sep 17 00:00:00 2001 From: Soumen Ghosh Date: Mon, 20 May 2024 16:56:28 -0700 Subject: [PATCH 248/274] ARM: dts: msm: adding license information There was missing license information adding this to all files. Licence information required for these files. CRs-Fixed: 3818810 Change-Id: I743432f8cb1ee998722dfab6287f07739e6464d4 Signed-off-by: Soumen Ghosh (cherry picked from commit 3317f10320b719d76128e13e77eb691dc6cd18e7) --- sun-camera-sensor-cdp.dts | 5 +++++ sun-camera-sensor-cdp.dtsi | 5 +++++ sun-camera-sensor-mtp.dts | 5 +++++ sun-camera-sensor-mtp.dtsi | 5 +++++ sun-camera-sensor-qrd.dts | 5 +++++ sun-camera-sensor-qrd.dtsi | 5 +++++ sun-camera-sensor-rumi.dts | 5 +++++ sun-camera-sensor-rumi.dtsi | 5 +++++ sun-camera.dts | 5 +++++ sun-camera.dtsi | 5 +++++ 10 files changed, 50 insertions(+) diff --git a/sun-camera-sensor-cdp.dts b/sun-camera-sensor-cdp.dts index 83f1e76b..f37362f3 100644 --- a/sun-camera-sensor-cdp.dts +++ b/sun-camera-sensor-cdp.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-cdp.dtsi b/sun-camera-sensor-cdp.dtsi index ec137d95..d617d9c8 100644 --- a/sun-camera-sensor-cdp.dtsi +++ b/sun-camera-sensor-cdp.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera-sensor-mtp.dts b/sun-camera-sensor-mtp.dts index 54da5b60..4432743b 100644 --- a/sun-camera-sensor-mtp.dts +++ b/sun-camera-sensor-mtp.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-mtp.dtsi b/sun-camera-sensor-mtp.dtsi index 7287c5ca..ba531f25 100644 --- a/sun-camera-sensor-mtp.dtsi +++ b/sun-camera-sensor-mtp.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 5ee419f5..7a25dd6f 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-qrd.dtsi b/sun-camera-sensor-qrd.dtsi index ec137d95..d617d9c8 100644 --- a/sun-camera-sensor-qrd.dtsi +++ b/sun-camera-sensor-qrd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera-sensor-rumi.dts b/sun-camera-sensor-rumi.dts index fa7b4141..46a70d37 100644 --- a/sun-camera-sensor-rumi.dts +++ b/sun-camera-sensor-rumi.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera-sensor-rumi.dtsi b/sun-camera-sensor-rumi.dtsi index ec137d95..d617d9c8 100644 --- a/sun-camera-sensor-rumi.dtsi +++ b/sun-camera-sensor-rumi.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include &soc { led_flash_triple_rear_wide: qcom,camera-flash1 { diff --git a/sun-camera.dts b/sun-camera.dts index 8e77a5d3..b7b0e6ae 100644 --- a/sun-camera.dts +++ b/sun-camera.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + /dts-v1/; /plugin/; diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 77c1391f..7adef2b5 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include #include From 7c44e2a721626059380d2942421dae61a960c0e9 Mon Sep 17 00:00:00 2001 From: Yash Upadhyay Date: Thu, 12 Sep 2024 12:48:16 +0530 Subject: [PATCH 249/274] ARM: dts: msm: Base device tree changes for Tuna This change adds support for Tuna in device tree. Change includes support for both Tuna and Ramos soc boards. CRs-Fixed: 3933582 Change-Id: I696ed4ab182508f399fd2102626248ad10df112d --- config/sun.mk | 2 + tuna-camera.dts | 21 + tuna-camera.dtsi | 2003 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2026 insertions(+) create mode 100644 tuna-camera.dts create mode 100644 tuna-camera.dtsi diff --git a/config/sun.mk b/config/sun.mk index 020533b5..197a891e 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -3,3 +3,5 @@ dtbo-$(CONFIG_ARCH_SUN) += sun-camera-sensor-mtp.dtbo \ sun-camera-sensor-rumi.dtbo \ sun-camera-sensor-cdp.dtbo \ sun-camera-sensor-qrd.dtbo + +dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo diff --git a/tuna-camera.dts b/tuna-camera.dts new file mode 100644 index 00000000..87507407 --- /dev/null +++ b/tuna-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "tuna-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna-camera.dtsi b/tuna-camera.dtsi new file mode 100644 index 00000000..6c96b31c --- /dev/null +++ b/tuna-camera.dtsi @@ -0,0 +1,2003 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife: msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1C00 0x00>; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + cam-smmu-label = "ife"; + multiple-client-devices; + memory-region = <&cam_smmu_ife_resv_region>; + cam_smmu_ife_resv_region: cam_smmu_ife_resv_region { + iommu-addresses = <&msm_cam_smmu_ife 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_ife 0xf 0xfff00000 0x0 0x100000>; + }; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg: msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x00>; + cam-smmu-label = "jpeg"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + memory-region = <&cam_smmu_jpeg_resv_region>; + cam_smmu_jpeg_resv_region: cam_smmu_jpeg_resv_region { + iommu-addresses = <&msm_cam_smmu_jpeg 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_jpeg 0x0 0xfff00000 0xf 0x00100000>; + }; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp: msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1800 0xC0>, + <&apps_smmu 0x1980 0x00>; + cam-smmu-label = "icp", "icp1"; + multiple-client-devices; + multiple-same-region-clients = "icp", "icp1"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + memory-region = <&cam_smmu_icp_resv_region>; + cam_smmu_icp_resv_region: cam_smmu_icp_resv_region { + iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1600000>; + }; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared1 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0x80e00000 */ + iova-region-start = <0x0 0x80e00000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-shared2 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xb9200000 */ + iova-region-start = <0x0 0xb9200000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region1 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80400000 */ + iova-region-start = <0x0 0x80400000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80500000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80400000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-region-fwuncached-region2 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80900000 */ + iova-region-start = <0x0 0x80900000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80a00000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80900000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x300000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + + iova-mem-region-ipc-hwmutex { + iova-region-name = "ipc_hwmutex"; + iova-region-start = <0x0 0x80101000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x2>; + phy-addr = <0x1f4b000>; + }; + + iova-mem-region-global_cntr { + iova-region-name = "global_cntr"; + iova-region-start = <0x0 0x80102000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x4>; + phy-addr = <0xc220000>; + }; + iova-mem-region-llcc-register { + iova-region-name = "llcc-register"; + iova-region-start = <0x0 0x80103000>; + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x5>; + phy-addr = <0x26C00000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf1600000 */ + iova-region-start = <0x0 0xf1600000>; + /* Length: 0xf0ea00000 */ + iova-region-len = <0xf 0x0ea00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0x80000000 */ + iova-region-start = <0x0 0x80000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x37790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm: msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + qcom,iommu-faults = "stall-disable", "non-fatal"; + dma-coherent; + multiple-client-devices; + memory-region = <&cam_smmu_cdm_resv_region>; + cam_smmu_cdm_resv_region: cam_smmu_cdm_resv_region { + iommu-addresses = <&msm_cam_smmu_cdm 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_cdm 0x0 0xfff00000 0xf 0x00100000>; + }; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + qti,smmu-proxy-cb-id = ; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh", "cam_cesta"; + reg = <0x0ac04000 0x1000>, + <0x0ac62000 0xA000>, + <0x0ad90000 0x9000>, + <0x0bbf0000 0x1f00>, + <0x0adcb000 0x4E00>; + reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000 0x0adcb000>; + interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt"; + interrupts = , + ; + camnoc-axi-min-ib-bw = <3000000000>; + cam-max-rt-axi-bw = <0x3 0x60447100>; + regulator-names = "top-gdsc"; + top-gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_top_fast_ahb_clk", + "camnoc_rt_axi_clk_src", + "camnoc_rt_axi_clk", + "camnoc_nrt_axi_clk", + "cam_cc_drv_xo_clk", + "cam_cc_pll0", + "cam_cc_qdss_debug_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>, + <&camcc CAM_CC_PLL0>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 56470588 0 0 0 200000000 0 200000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_rt_axi_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + cam-crmb-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = , + ; + cam-icc-path-names = "cam_ahb"; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv", + "cam_sf_0", + "cam_sf_icp"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0 + &mc_virt SLAVE_EBI1_CAM_IFE_0>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1 + &mc_virt SLAVE_EBI1_CAM_IFE_1>, + <&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2 + &mc_virt SLAVE_EBI1_CAM_IFE_2>, + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF + &mc_virt SLAVE_EBI1>; + rpmh-bcm-info = <13 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", + "cci0", "cci1", "csid0", "csid1", "csid2", "csid3", "csid4", + "ife0", "ife1", "ife2", "ife3", "ife4", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", + "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", + "jpeg-dma0", "jpeg-enc0", + "tpg13", "tpg14", "tpg15"; + sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; + sys-cache-uids = <71 72 73 74 75>; + sys-cache-concur = <1 1 1 0 0>; + enable-smart-qos; + enable-cam-drv = <(CAM_DDR_DRV | CAM_CLK_DRV)>; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0", + "cam_ife_0_drv", + "cam_ife_1_drv", + "cam_ife_2_drv"; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = + "cam_sf_icp"; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x4830>; + priority-lut-high-offset = <0x4834>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x4A30>; + priority-lut-high-offset = <0x4A34>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <11>; + node-name = "level1-rt4-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x5230>; + priority-lut-high-offset = <0x5234>; + }; + + level1_rt3_rd: level1-rt3-rd { + cell-index = <12>; + node-name = "level1-rt3-cdm-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_wr: level1-nrt6-wr { + cell-index = <14>; + node-name = "level1-nrt6-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_rd: level1-nrt6-rd { + cell-index = <15>; + node-name = "level1-nrt6-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <16>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt5_rd: level1-nrt5-rd { + cell-index = <17>; + node-name = "level1-nrt5-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt4_rd: level1-nrt4-rd { + cell-index = <18>; + node-name = "level1-nrt4-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt3_wr: level1-nrt3-wr { + cell-index = <19>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt9_rd: level1-nrt9-rd { + cell-index = <20>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <21>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <22>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <23>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <24>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pdaf_linear_wr: ife0-pdaf-linear-wr { + cell-index = <27>; + node-name = "ife0-pdaf-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_linear_wr: ife1-pdaf-linear-wr { + cell-index = <28>; + node-name = "ife1-pdaf-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_linear_wr: ife2-pdaf-linear-wr { + cell-index = <29>; + node-name = "ife2-pdaf-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + drv-voting-index = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <30>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <31>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <32>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <33>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <34>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + drv-voting-index = + ; + parent-node = <&level1_rt2_wr>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <35>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <36>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <37>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <38>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <39>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt5_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <40>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <41>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <42>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <43>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <44>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <45>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <46>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <47>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm4_all_rd: rt-cdm4-all-rd { + cell-index = <48>; + node-name = "rt-cdm4-all-rd"; + client-name = "rt-cdm4"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <49>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + icp1_all_rd: icp1-all-rd { + cell-index = <50>; + node-name = "icp1-all-rd"; + client-name = "icp1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + ofe0_linear_wr: ofe0-linear-wr { + cell-index = <51>; + node-name = "ofe0-linear-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt2_wr>; + }; + + ofe0_in_rd: ofe0-in-rd { + cell-index = <52>; + node-name = "ofe0-in-rd"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt4_rd>; + }; + + ofe0_ubwc_wr: ofe0-ubwc-wr { + cell-index = <53>; + node-name = "ofe0-ubwc-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt3_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac7f000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac7f000 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x7f000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac80000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac80000 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x80000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac81000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac81000 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x81000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac82000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac82000 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x82000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm4@ac83000 { + cell-index = <4>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac83000 0x580>; + reg-names = "rt-cdm4"; + reg-cam-base = <0x83000>; + interrupt-names = "rt-cdm4"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife4"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <28>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "mc_tfe"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@ad26000 { + cell-index = <0>; + compatible = "qcom,csid975"; + reg-names = "csid"; + reg = <0x0ad27000 0x2b00>; + reg-cam-base = <0x127000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0 0>, + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac86000{ + cell-index = <0>; + compatible = "qcom,mc_tfe975"; + reg-names = "ife"; + reg = <0x0ac86000 0x10000>; + reg-cam-base = <0x86000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "gdsc", "tfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe0-supply = <&cam_cc_tfe_0_gdsc>; + clock-names = + "tfe_0_main_fast_ahb", + "tfe_0_clk_src", + "tfe_0_main_clk", + "cam_cc_camnoc_rt_tfe_0_main_clk", + "tfe_0_bayer_fast_ahb", + "tfe_0_bayer_clk", + "cam_cc_camnoc_rt_tfe_0_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK>; + clock-rates = + <0 289000000 0 0 0 0 0>, + <0 400000000 0 0 0 0 0>, + <0 525000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 750000000 0 0 0 0 0>, + <0 750000000 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_0_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <8 13 16 4>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@ad29000 { + cell-index = <1>; + compatible = "qcom,csid975"; + reg-names = "csid"; + reg = <0x0ad2a000 0x2b00>; + reg-cam-base = <0x12a000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0 0>, + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac96000 { + cell-index = <1>; + compatible = "qcom,mc_tfe975"; + reg-names = "ife"; + reg = <0x0ac96000 0x10000>; + reg-cam-base = <0x96000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "gdsc", "tfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe1-supply = <&cam_cc_tfe_1_gdsc>; + clock-names = + "tfe_1_main_fast_ahb", + "tfe_1_clk_src", + "tfe_1_main_clk", + "cam_cc_camnoc_rt_tfe_1_main_clk", + "tfe_1_bayer_fast_ahb", + "tfe_1_bayer_clk", + "cam_cc_camnoc_rt_tfe_1_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK>; + clock-rates = + <0 289000000 0 0 0 0 0>, + <0 400000000 0 0 0 0 0>, + <0 525000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 750000000 0 0 0 0 0>, + <0 750000000 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_1_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <9 14 17 5>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@ad2c000 { + cell-index = <2>; + compatible = "qcom,csid975"; + reg-names = "csid"; + reg = <0x0ad2d000 0x2b00>; + reg-cam-base = <0x12d000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0 0>, + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@aca6000 { + cell-index = <2>; + compatible = "qcom,mc_tfe975"; + reg-names = "ife"; + reg = <0x0aca6000 0x10000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "gdsc", "tfe2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe2-supply = <&cam_cc_tfe_2_gdsc>; + clock-names = + "tfe_2_main_fast_ahb", + "tfe_2_clk_src", + "tfe_2_main_clk", + "cam_cc_camnoc_rt_tfe_2_main_clk", + "tfe_2_bayer_fast_ahb", + "tfe_2_bayer_clk", + "cam_cc_camnoc_rt_tfe_2_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK>; + clock-rates = + <0 289000000 0 0 0 0 0>, + <0 400000000 0 0 0 0 0>, + <0 525000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 750000000 0 0 0 0 0>, + <0 750000000 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_2_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <10 12 18 6>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,csid-lite975"; + reg-names = "csid-lite"; + reg = <0x0ad6d000 0xa00>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,vfe-lite975"; + reg-names = "ife-lite"; + reg = <0x0ad6d000 0x2800>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <19>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@ad71000 { + cell-index = <4>; + compatible = "qcom,csid-lite975"; + reg-names = "csid-lite"; + reg = <0x0ad72000 0xa00>; + reg-cam-base = <0x172000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "csid-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 266666667 0 0 0 0>, + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@ad71000 { + cell-index = <4>; + compatible = "qcom,vfe-lite975"; + reg-names = "ife-lite"; + reg = <0x0ad72000 0x2800>; + reg-cam-base = <0x172000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "ife-lite1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 266666667 0 0>, + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <20>; + status = "ok"; + }; + + cam_csiphy_tpg13: qcom,tpg13@ad8b000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0x0ad8b000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18b000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@ad8c000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0x0ad8c000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18c000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg15: qcom,tpg15@ad8d000 { + cell-index = <15>; + phy-id = <2>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0x0ad8d000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18d000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <266666667 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp0 { + compatible = "qcom,cam-icp0"; + cell-index = <0>; + compat-hw-name = "qcom,icp0", + "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + qcom,cam-icp1 { + compatible = "qcom,cam-icp1"; + cell-index = <1>; + compat-hw-name = "qcom,icp1", + "qcom,ofe"; + num-icp = <1>; + num-ofe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp0: qcom,icp0@ac05000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0ac06000 0x1000>, + <0x0ac09000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x6000 0x9000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_0_AHB_CLK>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 300000000 0 0>, + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP"; + ubwc-ipe-fetch-cfg = <0x3f083 0x3f083>; + ubwc-ipe-write-cfg = <0x1620F 0x1620F>; + qos-val = <0x808>; + fw-pas-id = <33>; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_icp1: qcom,icp1@ac150000 { + cell-index = <1>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0ac16000 0x1000>, + <0x0ac19000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x16000 0x19000>; + interrupt-names = "icp1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_2_mem>; + clock-names = + "icp_1_ahb_clk", + "icp_1_clk_src", + "icp_1_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_1_AHB_CLK>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 300000000 0 0>, + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "icp_1_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_1"; + ubwc-ofe-fetch-cfg = <0x3f083 0x3f083>; + ubwc-ofe-write-cfg = <0x1620F 0x1620F>; + qos-val = <0x808>; + fw-pas-id = <50>; + cam_hw_pid = <10>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0x0ac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_camnoc_nrt_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>; + clock-rates = + <0 0 0 309000000 0 0 0>, + <0 0 0 450000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 26 27>; + status = "ok"; + }; + + cam_ofe: qcom,ofe@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam-ofe"; + reg = <0x0ac2a000 0x18000>; + reg-names = "ofe0_top"; + reg-cam-base = <0x2a000>; + regulator-names = "ofe0-vdd"; + ofe0-vdd-supply = <&cam_cc_ofe_gdsc>; + clock-names = + "camnoc_nrt_ofe_anchor", + "camnoc_nrt_ofe_hdr", + "ofe_clk_src", + "ofe_main_clk", + "camnoc_nrt_ofe_main_clk", + "ofe_ahb_clk", + "ofe_anchor_clk", + "ofe_anchor_fast_ahb", + "ofe_hdr_fast_ahb", + "ofe_hdr_clk", + "ofe_main_fast_ahb"; + clocks = + <&camcc CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_OFE_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>, + <&camcc CAM_CC_OFE_AHB_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>; + clock-rates = + <0 0 283000000 0 0 0 0 0 0 0 0>, + <0 0 436000000 0 0 0 0 0 0 0 0>, + <0 0 570000000 0 0 0 0 0 0 0 0>, + <0 0 675000000 0 0 0 0 0 0 0 0>, + <0 0 757000000 0 0 0 0 0 0 0 0>, + <0 0 757000000 0 0 0 0 0 0 0 0>; + clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + nrt-device; + src-clock-name = "ofe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <13 28 6>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc_nrt"; + reg = <0x0ac25000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x25000 0x62000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_0_clk", + "jpegenc_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@ac26000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc_nrt"; + reg = <0x0ac26000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x26000 0x62000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_0_clk", + "jpegdma_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +}; From faca95135f1e41b999f324357a24e317db4c651f Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Fri, 27 Sep 2024 23:16:11 +0530 Subject: [PATCH 250/274] ARM: dts: msm: Initial camera sensor dtsi files for Tuna Initial sensor dtsi files for Tuna MTP/CDP/RCM with: - Peripherals: CCI0/CCI1, - CSIPHY instances: 0 to 4, - Sensors: IMX766/IMX858/JN1 nodes, - ASC sensor: OV32C node, - TPG instances: 1 to 3, - MCLK/RESET GPIO pin controls CRs-Fixed: 3940535. Change-Id: Ie2536cbf26380c152300ce122865d71e86c40a66 Signed-off-by: Shadul Shaikh --- config/sun.mk | 3 + tuna-camera-sensor-cdp.dts | 22 + tuna-camera-sensor-mtp.dts | 22 + tuna-camera-sensor-mtp.dtsi | 414 ++++++++++++++++++ tuna-camera.dtsi | 826 ++++++++++++++++++++++++++++++++++++ 5 files changed, 1287 insertions(+) create mode 100644 tuna-camera-sensor-cdp.dts create mode 100644 tuna-camera-sensor-mtp.dts create mode 100644 tuna-camera-sensor-mtp.dtsi diff --git a/config/sun.mk b/config/sun.mk index 197a891e..5efc0a84 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -5,3 +5,6 @@ dtbo-$(CONFIG_ARCH_SUN) += sun-camera-sensor-mtp.dtbo \ sun-camera-sensor-qrd.dtbo dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo + +dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera-sensor-mtp.dtbo \ + tuna-camera-sensor-cdp.dtbo diff --git a/tuna-camera-sensor-cdp.dts b/tuna-camera-sensor-cdp.dts new file mode 100644 index 00000000..70f3e1c0 --- /dev/null +++ b/tuna-camera-sensor-cdp.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "tuna-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna CDP/RCM"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,cdp", "qcom,rcm", "qcom,tuna-rcm"; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,board-id = <1 0>, <21 0>, <21 1>; +}; diff --git a/tuna-camera-sensor-mtp.dts b/tuna-camera-sensor-mtp.dts new file mode 100644 index 00000000..922c3b5b --- /dev/null +++ b/tuna-camera-sensor-mtp.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "tuna-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,mtp"; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,board-id = <8 0>, <8 1>, <8 2>; +}; diff --git a/tuna-camera-sensor-mtp.dtsi b/tuna-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..3e2ff6fd --- /dev/null +++ b/tuna-camera-sensor-mtp.dtsi @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pmxr2230_flash0 &pmxr2230_flash1>; + torch-source = <&pmxr2230_torch0 &pmxr2230_torch1>; + switch-source = <&pmxr2230_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pmxr2230_flash0 &pmxr2230_flash1>; + torch-source = <&pmxr2230_torch0 &pmxr2230_torch1>; + switch-source = <&pmxr2230_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pmxr2230_flash0 &pmxr2230_flash1>; + torch-source = <&pmxr2230_torch0 &pmxr2230_torch1>; + switch-source = <&pmxr2230_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + actuator_triple_uw: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103360>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 0>; + rgltr-max-voltage = <1980000 3000000 0>; + rgltr-load-current = <3500 214290 0>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; + rgltr-load-current = <3500 913200 0 91430 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 64 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; + rgltr-load-current = <4060 523640 0 107500 103360>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 65 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* IMX766 + OIS (Wide) */ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; + rgltr-load-current = <3500 913200 0 91430 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 64 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* IMX858 (UWide) */ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; + rgltr-load-current = <4060 523640 0 107500 103360>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 65 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103040>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; + rgltr-load-current = <4500 266330 0 69000 103040>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 67 0>, + <&tlmm 180 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET2"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* JN1 (Tele) */ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; + rgltr-load-current = <4500 266330 0 69000 103040>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 67 0>, + <&tlmm 180 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET2"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&qupv3_se8_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000>; + rgltr-load-current = <3560 283910 0 50360>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 68 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET3"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* OV32C4C + ASC (Front) */ + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000>; + rgltr-load-current = <3560 283910 0 50360>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 68 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET3"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/tuna-camera.dtsi b/tuna-camera.dtsi index 6c96b31c..bc066f1e 100644 --- a/tuna-camera.dtsi +++ b/tuna-camera.dtsi @@ -6,6 +6,486 @@ #include #include +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio70"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio70"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio70"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio70"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio71"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio71"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio71"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio71"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio72"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio72"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio72"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio72"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio73"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio73"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio73"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio73"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio74"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio74"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio74"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio75"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio75"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio75"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci_i2c_sda3_active { + mux { + pins = "gpio20"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { + mux { + pins = "gpio20"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci_i2c_scl3_active { + mux { + pins = "gpio21"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio21"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { + mux { + pins = "gpio21"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio64"; + function = "cam_mclk"; + }; + + config { + pins = "gpio64"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_asc_mclk4"; + }; + + config { + pins = "gpio68"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio68"; + function = "cam_asc_mclk4"; + }; + + config { + pins = "gpio68"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio180"; + function = "gpio"; + }; + + config { + pins = "gpio180"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio180"; + function = "gpio"; + }; + + config { + pins = "gpio180"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -21,6 +501,352 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy0@ada9000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0ada9000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1a9000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 950000>; + rgltr-load-current = <0 7810 81600>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@adab000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0adab000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1ab000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 950000>; + rgltr-load-current = <0 7810 81600>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@adad000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0adad000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1ad000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 950000>; + rgltr-load-current = <0 7810 81600>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@adaf000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0adaf000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1af000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 950000>; + rgltr-load-current = <0 7810 81600>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@adb1000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0adb1000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1b1000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1200000 950000>; + rgltr-load-current = <0 7810 81600>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvsd1", "lowsvs", "nominal"; + clock-rates = + <266666667 0 400000000 0>, + <400000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac7b000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7b000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac7c000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7c000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7c000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvsd1", "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; From 51c0ab783c4d80c0a980a85411af5b07487af288 Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Tue, 22 Oct 2024 10:54:27 +0530 Subject: [PATCH 251/274] ARM: dts: msm: Add platform subtype support for Tuna MTP Add platform subtypes Harmonium and NFC support for Tuna MTP. CRs-Fixed: 3955488. Change-Id: I45e62f144da579638cc16da2be05853935a8e305 Signed-off-by: Shadul Shaikh --- tuna-camera-sensor-mtp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tuna-camera-sensor-mtp.dts b/tuna-camera-sensor-mtp.dts index 922c3b5b..1f6d39a1 100644 --- a/tuna-camera-sensor-mtp.dts +++ b/tuna-camera-sensor-mtp.dts @@ -16,7 +16,7 @@ #include "tuna-camera-sensor-mtp.dtsi" / { model = "Qualcomm Technologies, Inc. Tuna MTP"; - compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,mtp"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; - qcom,board-id = <8 0>, <8 1>, <8 2>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 3>, <8 4>; }; From 40fb0392b96dc0b58b44515b4d40ea6fc4a53cd5 Mon Sep 17 00:00:00 2001 From: zhaocao Date: Thu, 17 Oct 2024 17:57:52 +0800 Subject: [PATCH 252/274] ARM: dts: msm: Add camera dtsi change for tuna Add tuna qrd camera dtsi support. CRs-Fixed: 3951945 Signed-off-by: zhaocao Change-Id: Ice6aea53510a5a08c1d739a2d29366570e08e102 --- config/sun.mk | 3 ++- tuna-camera-sensor-qrd.dts | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 tuna-camera-sensor-qrd.dts diff --git a/config/sun.mk b/config/sun.mk index 5efc0a84..5ff2a2f5 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -7,4 +7,5 @@ dtbo-$(CONFIG_ARCH_SUN) += sun-camera-sensor-mtp.dtbo \ dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera-sensor-mtp.dtbo \ - tuna-camera-sensor-cdp.dtbo + tuna-camera-sensor-cdp.dtbo \ + tuna-camera-sensor-qrd.dtbo diff --git a/tuna-camera-sensor-qrd.dts b/tuna-camera-sensor-qrd.dts new file mode 100644 index 00000000..14a5e9c7 --- /dev/null +++ b/tuna-camera-sensor-qrd.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "tuna-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Tuna QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,qrd"; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,board-id = <11 0>; +}; From a54dd41744de864df648769a961a69f986ffb9c7 Mon Sep 17 00:00:00 2001 From: Yash Upadhyay Date: Tue, 29 Oct 2024 10:25:29 +0530 Subject: [PATCH 253/274] ARM: dts: msm: Adding support for Tuna APQ This change adds support for Tuna APQ soc. CRs-Fixed: 3933582 Change-Id: Ib098bb7f28101a281d6342c033f5f239c0e64049 --- tuna-camera.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tuna-camera.dts b/tuna-camera.dts index 87507407..a1e16fc9 100644 --- a/tuna-camera.dts +++ b/tuna-camera.dts @@ -16,6 +16,7 @@ / { model = "Qualcomm Technologies, Inc. Tuna SoC"; compatible = "qcom,tuna"; - qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>, + <694 0x10000>, <694 0x20000>; qcom,board-id = <0 0>; }; From c30a9ec681d0a6e26ff35a277db63382f5336d67 Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Tue, 29 Oct 2024 12:50:27 +0530 Subject: [PATCH 254/274] ARM: dts: msm: Add new soc id support for Tuna Add APQ SOC ID support for Tuna MTP/CDP. CRs-Fixed: 3961927. Change-Id: I4da667b1646e3351117de000cd3013cc4d4d3430 Signed-off-by: Shadul Shaikh --- tuna-camera-sensor-cdp.dts | 2 +- tuna-camera-sensor-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tuna-camera-sensor-cdp.dts b/tuna-camera-sensor-cdp.dts index 70f3e1c0..b9631c5e 100644 --- a/tuna-camera-sensor-cdp.dts +++ b/tuna-camera-sensor-cdp.dts @@ -17,6 +17,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna CDP/RCM"; compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,cdp", "qcom,rcm", "qcom,tuna-rcm"; - qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>, <694 0x10000>, <694 0x20000>; qcom,board-id = <1 0>, <21 0>, <21 1>; }; diff --git a/tuna-camera-sensor-mtp.dts b/tuna-camera-sensor-mtp.dts index 1f6d39a1..1b06b857 100644 --- a/tuna-camera-sensor-mtp.dts +++ b/tuna-camera-sensor-mtp.dts @@ -17,6 +17,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>, <694 0x10000>, <694 0x20000>; qcom,board-id = <8 0>, <8 1>, <8 2>, <8 3>, <8 4>; }; From 9ac2eb76b1dc19f334423d5aa6583782c9148903 Mon Sep 17 00:00:00 2001 From: zhaocao Date: Wed, 30 Oct 2024 13:46:51 +0530 Subject: [PATCH 255/274] ARM: dts: msm: Add new soc id support for Tuna Add APQ SOC ID support for Tuna QRD CRs-Fixed: 3963176. Change-Id: I46b54ad4b5dd466e746a7d865145729452c0085b Signed-off-by: zhaocao --- tuna-camera-sensor-qrd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tuna-camera-sensor-qrd.dts b/tuna-camera-sensor-qrd.dts index 14a5e9c7..11874e2c 100644 --- a/tuna-camera-sensor-qrd.dts +++ b/tuna-camera-sensor-qrd.dts @@ -16,7 +16,7 @@ #include "tuna-camera-sensor-mtp.dtsi" / { model = "Qualcomm Technologies, Inc. Tuna QRD"; - compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,qrd"; - qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,qrd", "qcom,rcm", "qcom,tuna-rcm"; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>, <694 0x10000>, <694 0x20000>; qcom,board-id = <11 0>; }; From 3f9b9479137b6519491e61cd55450a07c596f62f Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Wed, 30 Oct 2024 17:21:15 +0530 Subject: [PATCH 256/274] ARM: dts: msm: Update sensors load current for Tuna Update VAF load current(uA) of IMX766/JN1 sensors and its sub devices. CRs-Fixed: 3963500. Change-Id: I5ee5a6e41dd5e83908e5545547be8531f98bae32 Signed-off-by: Shadul Shaikh --- tuna-camera-sensor-mtp.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tuna-camera-sensor-mtp.dtsi b/tuna-camera-sensor-mtp.dtsi index 3e2ff6fd..7d5bd2a7 100644 --- a/tuna-camera-sensor-mtp.dtsi +++ b/tuna-camera-sensor-mtp.dtsi @@ -48,7 +48,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103000>; + rgltr-load-current = <118930>; status = "ok"; }; @@ -76,7 +76,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 2800000 0>; rgltr-max-voltage = <1980000 3000000 0>; - rgltr-load-current = <3500 214290 0>; + rgltr-load-current = <3500 220000 0>; status = "ok"; }; @@ -94,7 +94,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -174,7 +174,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -250,7 +250,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103040>; + rgltr-load-current = <130040>; status = "ok"; }; @@ -267,7 +267,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4500 266330 0 69000 103040>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active @@ -310,7 +310,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4500 266330 0 69000 103040>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active From b50d126b7cb903aa8f1d618c95b28f4aedaa78e4 Mon Sep 17 00:00:00 2001 From: Dharmender Sharma Date: Fri, 27 Sep 2024 02:17:36 +0530 Subject: [PATCH 257/274] ARM: dts: msm: Base device tree changes for Kera This change adds support for Kera in device tree. CRs-Fixed: 3947490 Change-Id: I3c292e37bb48a7758217191607c24c72b04e9d62 Signed-off-by: Dharmender Sharma Signed-off-by: Abhilash Kumar --- config/sun.mk | 2 + kera-camera.dts | 21 + kera-camera.dtsi | 1730 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1753 insertions(+) create mode 100644 kera-camera.dts create mode 100644 kera-camera.dtsi diff --git a/config/sun.mk b/config/sun.mk index 5ff2a2f5..7c40229e 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -9,3 +9,5 @@ dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera-sensor-mtp.dtbo \ tuna-camera-sensor-cdp.dtbo \ tuna-camera-sensor-qrd.dtbo + +dtbo-$(CONFIG_ARCH_KERA) += kera-camera.dtbo diff --git a/kera-camera.dts b/kera-camera.dts new file mode 100644 index 00000000..81127fc1 --- /dev/null +++ b/kera-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kera-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/kera-camera.dtsi b/kera-camera.dtsi new file mode 100644 index 00000000..4d0e9a88 --- /dev/null +++ b/kera-camera.dtsi @@ -0,0 +1,1730 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife: msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1C00 0x00>; + dma-coherent; + cam-smmu-label = "ife"; + multiple-client-devices; + memory-region = <&cam_smmu_ife_resv_region>; + cam_smmu_ife_resv_region: cam_smmu_ife_resv_region { + iommu-addresses = <&msm_cam_smmu_ife 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_ife 0xf 0xfff00000 0x0 0x100000>; + }; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg: msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x00>; + cam-smmu-label = "jpeg"; + dma-coherent; + memory-region = <&cam_smmu_jpeg_resv_region>; + cam_smmu_jpeg_resv_region: cam_smmu_jpeg_resv_region { + iommu-addresses = <&msm_cam_smmu_jpeg 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_jpeg 0x0 0xfff00000 0xf 0x00100000>; + }; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp: msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1800 0xC0>, + <&apps_smmu 0x1980 0x00>; + cam-smmu-label = "icp", "icp1"; + multiple-client-devices; + multiple-same-region-clients = "icp", "icp1"; + dma-coherent; + memory-region = <&cam_smmu_icp_resv_region>; + cam_smmu_icp_resv_region: cam_smmu_icp_resv_region { + iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1600000>; + }; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared1 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0x80e00000 */ + iova-region-start = <0x0 0x80e00000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-shared2 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xb9200000 */ + iova-region-start = <0x0 0xb9200000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region1 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80400000 */ + iova-region-start = <0x0 0x80400000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80500000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80400000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-region-fwuncached-region2 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80900000 */ + iova-region-start = <0x0 0x80900000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80a00000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80900000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x300000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + + iova-mem-region-ipc-hwmutex { + iova-region-name = "ipc_hwmutex"; + iova-region-start = <0x0 0x80101000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x2>; + phy-addr = <0x1f4b000>; + }; + + iova-mem-region-global_cntr { + iova-region-name = "global_cntr"; + iova-region-start = <0x0 0x80102000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x4>; + phy-addr = <0xc220000>; + }; + iova-mem-region-llcc-register { + iova-region-name = "llcc-register"; + iova-region-start = <0x0 0x80103000>; + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x5>; + phy-addr = <0x26C00000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf1600000 */ + iova-region-start = <0x0 0xf1600000>; + /* Length: 0xf0ea00000 */ + iova-region-len = <0xf 0x0ea00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0x80000000 */ + iova-region-start = <0x0 0x80000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x37790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm: msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + memory-region = <&cam_smmu_cdm_resv_region>; + cam_smmu_cdm_resv_region: cam_smmu_cdm_resv_region { + iommu-addresses = <&msm_cam_smmu_cdm 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_cdm 0x0 0xfff00000 0xf 0x00100000>; + }; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + qti,smmu-proxy-cb-id = ; + }; + }; + + qcom,cam-cpas@ac04000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh"; + reg = <0x0ac04000 0x1000>, + <0x0ac62000 0x9200>, + <0x0ad90000 0x9000>, + <0x0bbf0000 0x1f00>; + reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000>; + interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt"; + interrupts = , + ; + camnoc-axi-min-ib-bw = <3000000000>; + cam-max-rt-axi-bw = <0x3 0x60447100>; + regulator-names = "top-gdsc"; + top-gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_top_fast_ahb_clk", + "camnoc_rt_axi_clk_src", + "camnoc_rt_axi_clk", + "camnoc_nrt_axi_clk", + "cam_cc_drv_xo_clk", + "cam_cc_pll0", + "cam_cc_qdss_debug_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>, + <&camcc CAM_CC_PLL0>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "camnoc_rt_axi_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + cam-crmb-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = , + ; + cam-icc-path-names = "cam_ahb"; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_sf_0", + "cam_sf_icp"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF + &mc_virt SLAVE_EBI1>; + rpmh-bcm-info = <13 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", + "ife0", "ife1", "ife2", "ife3", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", + "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", + "jpeg-dma0", "jpeg-enc0"; + sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; + sys-cache-uids = <71 72 73 74 75>; + sys-cache-concur = <1 1 1 0 0>; + enable-smart-qos; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = + "cam_sf_icp"; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x4830>; + priority-lut-high-offset = <0x4834>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x4A30>; + priority-lut-high-offset = <0x4A34>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <11>; + node-name = "level1-rt4-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x5230>; + priority-lut-high-offset = <0x5234>; + }; + + level1_rt3_rd: level1-rt3-rd { + cell-index = <12>; + node-name = "level1-rt3-cdm-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_wr: level1-nrt6-wr { + cell-index = <14>; + node-name = "level1-nrt6-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_rd: level1-nrt6-rd { + cell-index = <15>; + node-name = "level1-nrt6-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt7_rd: level1-nrt7-rd { + cell-index = <16>; + node-name = "level1-nrt7-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <17>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt5_rd: level1-nrt5-rd { + cell-index = <18>; + node-name = "level1-nrt5-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt4_rd: level1-nrt4-rd { + cell-index = <19>; + node-name = "level1-nrt4-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt3_wr: level1-nrt3-wr { + cell-index = <20>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt9_rd: level1-nrt9-rd { + cell-index = <21>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <22>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <23>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <24>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <27>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pdaf_linear_wr: ife0-pdaf-linear-wr { + cell-index = <28>; + node-name = "ife0-pdaf-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_linear_wr: ife1-pdaf-linear-wr { + cell-index = <29>; + node-name = "ife1-pdaf-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_linear_wr: ife2-pdaf-linear-wr { + cell-index = <30>; + node-name = "ife2-pdaf-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <31>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <32>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <33>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <34>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt2_wr>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <35>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <36>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <37>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <38>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <39>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt5_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <40>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <41>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <42>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt7_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <43>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt7_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <44>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <45>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <46>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <47>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <48>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + icp1_all_rd: icp1-all-rd { + cell-index = <49>; + node-name = "icp1-all-rd"; + client-name = "icp1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + ofe0_linear_wr: ofe0-linear-wr { + cell-index = <50>; + node-name = "ofe0-linear-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt2_wr>; + }; + + ofe0_in_rd: ofe0-in-rd { + cell-index = <51>; + node-name = "ofe0-in-rd"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt4_rd>; + }; + + ofe0_ubwc_wr: ofe0-ubwc-wr { + cell-index = <52>; + node-name = "ofe0-ubwc-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt3_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac7f000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac7f000 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x7f000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac80000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac80000 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x80000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac81000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac81000 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x81000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac82000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac82000 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x82000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "mc_tfe"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@ad26000 { + cell-index = <0>; + compatible = "qcom,csid970"; + reg-names = "csid"; + reg = <0x0ad27000 0x2b00>; + reg-cam-base = <0x127000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac86000{ + cell-index = <0>; + compatible = "qcom,mc_tfe970"; + reg-names = "ife"; + reg = <0x0ac86000 0x10000>; + reg-cam-base = <0x86000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "gdsc", "tfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe0-supply = <&cam_cc_tfe_0_gdsc>; + clock-names = + "tfe_0_main_fast_ahb", + "tfe_0_clk_src", + "tfe_0_main_clk", + "cam_cc_camnoc_rt_tfe_0_main_clk", + "tfe_0_bayer_fast_ahb", + "tfe_0_bayer_clk", + "cam_cc_camnoc_rt_tfe_0_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK>; + clock-rates = + <0 445000000 0 0 0 0 0>, + <0 567000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe_0_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1026>; + cam_hw_pid = <0 9 16 4>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@ad29000 { + cell-index = <1>; + compatible = "qcom,csid970"; + reg-names = "csid"; + reg = <0x0ad2a000 0x2b00>; + reg-cam-base = <0x12a000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac96000 { + cell-index = <1>; + compatible = "qcom,mc_tfe970"; + reg-names = "ife"; + reg = <0x0ac96000 0x10000>; + reg-cam-base = <0x96000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "gdsc", "tfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe1-supply = <&cam_cc_tfe_1_gdsc>; + clock-names = + "tfe_1_main_fast_ahb", + "tfe_1_clk_src", + "tfe_1_main_clk", + "cam_cc_camnoc_rt_tfe_1_main_clk", + "tfe_1_bayer_fast_ahb", + "tfe_1_bayer_clk", + "cam_cc_camnoc_rt_tfe_1_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK>; + clock-rates = + <0 445000000 0 0 0 0 0>, + <0 567000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_1_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1026>; + cam_hw_pid = <1 10 17 5>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@ad2c000 { + cell-index = <2>; + compatible = "qcom,csid970"; + reg-names = "csid"; + reg = <0x0ad2d000 0x2b00>; + reg-cam-base = <0x12d000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@aca6000 { + cell-index = <2>; + compatible = "qcom,mc_tfe970"; + reg-names = "ife"; + reg = <0x0aca6000 0x10000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "gdsc", "tfe2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe2-supply = <&cam_cc_tfe_2_gdsc>; + clock-names = + "tfe_2_main_fast_ahb", + "tfe_2_clk_src", + "tfe_2_main_clk", + "cam_cc_camnoc_rt_tfe_2_main_clk", + "tfe_2_bayer_fast_ahb", + "tfe_2_bayer_clk", + "cam_cc_camnoc_rt_tfe_2_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK>; + clock-rates = + <0 445000000 0 0 0 0 0>, + <0 567000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe_2_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1026>; + cam_hw_pid = <2 8 18 6>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,csid-lite970"; + reg-names = "csid-lite"; + reg = <0x0ad6d000 0xa00>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,vfe-lite970"; + reg-names = "ife-lite"; + reg = <0x0ad6d000 0x2800>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <19>; + status = "ok"; + }; + + qcom,cam-icp0 { + compatible = "qcom,cam-icp0"; + cell-index = <0>; + compat-hw-name = "qcom,icp0", + "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + qcom,cam-icp1 { + compatible = "qcom,cam-icp1"; + cell-index = <1>; + compat-hw-name = "qcom,icp1", + "qcom,ofe"; + num-icp = <1>; + num-ofe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp0: qcom,icp0@ac05000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0ac06000 0x1000>, + <0x0ac09000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x6000 0x9000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_0_AHB_CLK>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_970"; + ubwc-ipe-fetch-cfg = <0x707B 0x707B>; + ubwc-ipe-write-cfg = <0x161EF 0x161EF>; + qos-val = <0x808>; + fw-pas-id = <33>; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_icp1: qcom,icp1@ac15000 { + cell-index = <1>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0ac16000 0x1000>, + <0x0ac19000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x16000 0x19000>; + interrupt-names = "icp1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_2_mem>; + clock-names = + "icp_1_ahb_clk", + "icp_1_clk_src", + "icp_1_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_1_AHB_CLK>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "icp_1_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_1_970"; + ubwc-ofe-fetch-cfg = <0x707B 0x707B>; + ubwc-ofe-write-cfg = <0x161EF 0x161EF>; + qos-val = <0x808>; + fw-pas-id = <50>; + cam_hw_pid = <10>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0x0ac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_camnoc_nrt_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>; + clock-rates = + <0 0 0 450000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 26 27>; + status = "ok"; + }; + + cam_ofe: qcom,ofe@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam-ofe"; + reg = <0x0ac2a000 0x18000>; + reg-names = "ofe0_top"; + reg-cam-base = <0x2a000>; + regulator-names = "ofe0-vdd"; + ofe0-vdd-supply = <&cam_cc_ofe_gdsc>; + clock-names = + "camnoc_nrt_ofe_anchor", + "camnoc_nrt_ofe_hdr", + "ofe_clk_src", + "ofe_main_clk", + "camnoc_nrt_ofe_main_clk", + "ofe_ahb_clk", + "ofe_anchor_clk", + "ofe_anchor_fast_ahb", + "ofe_hdr_fast_ahb", + "ofe_hdr_clk", + "ofe_main_fast_ahb"; + clocks = + <&camcc CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_OFE_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>, + <&camcc CAM_CC_OFE_AHB_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>; + clock-rates = + <0 0 436000000 0 0 0 0 0 0 0 0>, + <0 0 570000000 0 0 0 0 0 0 0 0>, + <0 0 675000000 0 0 0 0 0 0 0 0>, + <0 0 757000000 0 0 0 0 0 0 0 0>, + <0 0 757000000 0 0 0 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "ofe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <13 28 6>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc_nrt"; + reg = <0x0ac25000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x25000 0x62000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_0_clk", + "jpegenc_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@ac26000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc_nrt"; + reg = <0x0ac26000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x26000 0x62000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_0_clk", + "jpegdma_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +}; From 02bf75d48c03e898dfd27f01953912ae5d78369a Mon Sep 17 00:00:00 2001 From: Mukund Deshmukh Date: Fri, 15 Nov 2024 15:40:22 +0530 Subject: [PATCH 258/274] ARM: dts: msm: Initial camera sensor dtsi files for Kera Initial sensor dtsi files for Kera MTP/CDP/RCM/QRD with: - Peripherals: CCI0/CCI1, - CSIPHY instances: 0 to 4, - Sensors: IMX766/IMX858/JN1/IMX688 nodes, - TPG instances: 1 to 2, - MCLK/RESET GPIO pin controls CRs-Fixed: 3970958. Change-Id: Ieb49cd277e1e3eb7b48344c6098e82b28dee2b20 --- config/sun.mk | 4 + kera-camera-sensor-cdp.dts | 23 + kera-camera-sensor-mtp.dts | 24 ++ kera-camera-sensor-mtp.dtsi | 418 ++++++++++++++++++ kera-camera-sensor-qrd.dts | 23 + kera-camera-sensor-rcm.dts | 24 ++ kera-camera.dtsi | 824 +++++++++++++++++++++++++++++++++++- 7 files changed, 1337 insertions(+), 3 deletions(-) create mode 100644 kera-camera-sensor-cdp.dts create mode 100644 kera-camera-sensor-mtp.dts create mode 100644 kera-camera-sensor-mtp.dtsi create mode 100644 kera-camera-sensor-qrd.dts create mode 100644 kera-camera-sensor-rcm.dts diff --git a/config/sun.mk b/config/sun.mk index 7c40229e..43a8a45f 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -11,3 +11,7 @@ dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera-sensor-mtp.dtbo \ tuna-camera-sensor-qrd.dtbo dtbo-$(CONFIG_ARCH_KERA) += kera-camera.dtbo +dtbo-$(CONFIG_ARCH_KERA) += kera-camera-sensor-mtp.dtbo \ + kera-camera-sensor-cdp.dtbo \ + kera-camera-sensor-qrd.dtbo \ + kera-camera-sensor-rcm.dtbo diff --git a/kera-camera-sensor-cdp.dts b/kera-camera-sensor-cdp.dts new file mode 100644 index 00000000..2c23c69f --- /dev/null +++ b/kera-camera-sensor-cdp.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "kera-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/kera-camera-sensor-mtp.dts b/kera-camera-sensor-mtp.dts new file mode 100644 index 00000000..9a6d1726 --- /dev/null +++ b/kera-camera-sensor-mtp.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "kera-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, + <0x30008 0>, <0x30008 1>; +}; diff --git a/kera-camera-sensor-mtp.dtsi b/kera-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..bf0b5ed9 --- /dev/null +++ b/kera-camera-sensor-mtp.dtsi @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pmxr2230_flash0 &pmxr2230_flash1>; + torch-source = <&pmxr2230_torch0 &pmxr2230_torch1>; + switch-source = <&pmxr2230_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pmxr2230_flash0 &pmxr2230_flash1>; + torch-source = <&pmxr2230_torch0 &pmxr2230_torch1>; + switch-source = <&pmxr2230_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pmxr2230_flash0 &pmxr2230_flash1>; + torch-source = <&pmxr2230_torch0 &pmxr2230_torch1>; + switch-source = <&pmxr2230_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + /* Actuator (UW) */ + actuator_triple_uw: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + status = "ok"; + }; + + /* OIS (W) */ + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5N>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 0>; + rgltr-max-voltage = <1980000 3000000 0>; + rgltr-load-current = <3500 214290 0>; + status = "ok"; + }; + + /* EEPROM (W) */ + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; + rgltr-load-current = <3500 913200 0 91430 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 66 0>, + <&tlmm 124 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* EEPROM (UW) */ + eeprom_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; + rgltr-load-current = <3500 522730 0 107140 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 65 0>, + <&tlmm 123 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* IMX858 (UWide) */ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; + rgltr-load-current = <3500 522730 0 107140 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 65 0>, + <&tlmm 123 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* IMX766 + OIS (Wide) */ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; + rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; + rgltr-load-current = <3500 913200 0 91430 103000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 66 0>, + <&tlmm 124 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + /* Actuator (Tele) */ + actuator_triple_tele: qcom,actuator3 { + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <130000>; + status = "ok"; + }; + + /* EEPROM (Tele) */ + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; + rgltr-load-current = <4000 261000 0 68000 130000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 67 0>, + <&tlmm 125 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* EEPROM (Front) */ + eeprom_front: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; + rgltr-load-current = <5000 453330 0 77500 28890>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 68 0>, + <&tlmm 126 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* IMX688 (Front) */ + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L5N>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + cam_v_custom1-supply = <&L4N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; + rgltr-load-current = <5000 453330 0 77500 28890>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 68 0>, + <&tlmm 126 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + /* JN1 (Tele) */ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; + rgltr-load-current = <4000 261000 0 68000 130000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 67 0>, + <&tlmm 125 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; diff --git a/kera-camera-sensor-qrd.dts b/kera-camera-sensor-qrd.dts new file mode 100644 index 00000000..5b3b5e6c --- /dev/null +++ b/kera-camera-sensor-qrd.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "kera-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/kera-camera-sensor-rcm.dts b/kera-camera-sensor-rcm.dts new file mode 100644 index 00000000..7863cc84 --- /dev/null +++ b/kera-camera-sensor-rcm.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "kera-camera-sensor-mtp.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; + qcom,board-id = <0x10015 0>, <0x20015 0>, <0x30015 0>, <0x10015 1>, + <0x20015 1>, <0x30015 1>; +}; diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 4d0e9a88..790ff951 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -6,6 +6,457 @@ #include #include +&tlmm { + cci_i2c_sda0_active: cci_i2c_sda0_active { + mux { + /* CLK, DATA */ + pins = "gpio70"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio70"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda0_suspend: cci_i2c_sda0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio70"; + function = "cci_i2c_sda0"; + }; + + config { + pins = "gpio70"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl0_active: cci_i2c_scl0_active { + mux { + /* CLK, DATA */ + pins = "gpio71"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio71"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl0_suspend: cci_i2c_scl0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio71"; + function = "cci_i2c_scl0"; + }; + + config { + pins = "gpio71"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda1_active: cci_i2c_sda1_active { + mux { + /* CLK, DATA */ + pins = "gpio72"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio72"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda1_suspend: cci_i2c_sda1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio72"; + function = "cci_i2c_sda1"; + }; + + config { + pins = "gpio72"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl1_active: cci_i2c_scl1_active { + mux { + /* CLK, DATA */ + pins = "gpio73"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio73"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl1_suspend: cci_i2c_scl1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio73"; + function = "cci_i2c_scl1"; + }; + + config { + pins = "gpio73"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda2_active: cci_i2c_sda2_active { + mux { + /* CLK, DATA */ + pins = "gpio74"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio74"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda2_suspend: cci_i2c_sda2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio74"; + function = "cci_i2c_sda2"; + }; + + config { + pins = "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl2_active: cci_i2c_scl2_active { + mux { + /* CLK, DATA */ + pins = "gpio75"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio75"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl2_suspend: cci_i2c_scl2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio75"; + function = "cci_i2c_scl2"; + }; + + config { + pins = "gpio75"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_sda3_active: cci_i2c_sda3_active { + mux { + pins = "gpio76"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio76"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_sda3_suspend: cci_i2c_sda3_suspend { + mux { + pins = "gpio76"; + function = "cci_i2c_sda3"; + }; + + config { + pins = "gpio76"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci_i2c_scl3_active: cci_i2c_scl3_active { + mux { + pins = "gpio77"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio77"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + qcom,i2c_pull; + }; + }; + + cci_i2c_scl3_suspend: cci_i2c_scl3_suspend { + mux { + pins = "gpio77"; + function = "cci_i2c_scl3"; + }; + + config { + pins = "gpio77"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio65"; + function = "cam_mclk"; + }; + + config { + pins = "gpio65"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio66"; + function = "cam_mclk"; + }; + + config { + pins = "gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio67"; + function = "cam_mclk"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio68"; + function = "cam_mclk"; + }; + + config { + pins = "gpio68"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + qcom,apps; + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + qcom,remote; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; &soc { #address-cells = <1>; @@ -21,6 +472,373 @@ compatible = "qcom,cam-sync"; status = "ok"; }; + cam_csiphy0: qcom,csiphy0@ada9000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0ada9000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1a9000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1320000 950000>; + rgltr-load-current = <0 14120 145800>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "svs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@adab000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0adab000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1ab000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1320000 950000>; + rgltr-load-current = <0 14120 145800>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "svs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@adad000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; + reg = <0x0adad000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1ad000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1320000 950000>; + rgltr-load-current = <0 14120 145800>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "svs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@adaf000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + reg = <0x0adaf000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x1af000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L4B>; + csi-vdd-0p9-supply = <&L2B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1320000 950000>; + rgltr-load-current = <0 14120 145800>; + shared-clks = <1 0 0 0>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "cphy_rx_clk_src"; + clock-cntl-level = "lowsvs", "svs", "nominal"; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 400000000 0>, + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac7b000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7b000>; + interrupt-names = "CCI0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvs", "svs"; + src-clock-name = "cci_0_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>; + pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>; + pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>; + pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1@ac7c000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0x0ac7c000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x7c000>; + interrupt-names = "CCI1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>, <37500000 0>; + clock-cntl-level = "lowsvs", "svs"; + src-clock-name = "cci_1_clk_src"; + pctrl-idx-mapping = ; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", + "m1_active", "m1_suspend"; + pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>; + pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>; + pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>; + pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>; + status = "ok"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <1>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_csiphy_tpg13: qcom,tpg13@ad8b000 { + cell-index = <13>; + phy-id = <0>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0x0ad8b000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18b000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "svs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg14: qcom,tpg14@ad8c000 { + cell-index = <14>; + phy-id = <1>; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0x0ad8c000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18c000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "svs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; @@ -391,12 +1209,12 @@ "turbo", "turbo"; client-id-based; client-names = - "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", - "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "cci0", "cci1", "csid0", "csid1", "csid2", "csid3", "ife0", "ife1", "ife2", "ife3", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", - "jpeg-dma0", "jpeg-enc0"; + "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14"; sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; sys-cache-uids = <71 72 73 74 75>; sys-cache-concur = <1 1 1 0 0>; From 4f64ffe81b25caec7f8375ef4a55b1a96cecbb7b Mon Sep 17 00:00:00 2001 From: Mukund Deshmukh Date: Sun, 17 Nov 2024 12:11:32 +0530 Subject: [PATCH 259/274] ARM: dts: msm: Initial camera sensor dtsi files for Kera Updation of sensor dtsi files for Kera MTP/CDP/RCM/QRD with: - Regulator current updated as per latest PG for UW sensor. - Regulator current updated as per latest PG for Front sensor. CRs-Fixed: 3970958. Change-Id: I6074f8858f44da920406d5dd11c165fe2fa8fbd4 --- kera-camera-sensor-mtp.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/kera-camera-sensor-mtp.dtsi b/kera-camera-sensor-mtp.dtsi index bf0b5ed9..bfd880a2 100644 --- a/kera-camera-sensor-mtp.dtsi +++ b/kera-camera-sensor-mtp.dtsi @@ -131,7 +131,7 @@ regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-min-voltage = <1800000 1100000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; rgltr-load-current = <3500 522730 0 107140 103000>; gpio-no-mux = <0>; @@ -174,7 +174,7 @@ regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", "cam_vaf"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; + rgltr-min-voltage = <1800000 1100000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; rgltr-load-current = <3500 522730 0 107140 103000>; gpio-no-mux = <0>; @@ -210,7 +210,7 @@ ois-src = <&ois_wide>; actuator-src = <&actuator_triple_wide>; led-flash-src = <&led_flash_triple_rear_wide>; - cam_vio-supply = <&L5M>; + cam_vio-supply = <&L5N>; cam_vdig-supply = <&L1N>; cam_clk-supply = <&cam_cc_titan_top_gdsc>; cam_vana-supply = <&L6M>; @@ -307,7 +307,7 @@ regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 1104000 0 2800000 1800000>; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; rgltr-load-current = <5000 453330 0 77500 28890>; gpio-no-mux = <0>; @@ -348,7 +348,7 @@ regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 1104000 0 2800000 1800000>; + rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; rgltr-load-current = <5000 453330 0 77500 28890>; gpio-no-mux = <0>; @@ -383,7 +383,7 @@ eeprom-src = <&eeprom_tele>; actuator-src = <&actuator_triple_tele>; led-flash-src = <&led_flash_triple_rear_tele>; - cam_vio-supply = <&L5M>; + cam_vio-supply = <&L5N>; cam_vdig-supply = <&L2M>; cam_clk-supply = <&cam_cc_titan_top_gdsc>; cam_vana-supply = <&L4M>; From 73907947aa0ef9d4297745e11eb4c82fc7316dc5 Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Tue, 29 Oct 2024 12:50:27 +0530 Subject: [PATCH 260/274] ARM: dts: msm: Add new soc id support for Tuna Add APQ SOC ID support for Tuna MTP/CDP. CRs-Fixed: 3961927. Change-Id: I4da667b1646e3351117de000cd3013cc4d4d3430 Signed-off-by: Shadul Shaikh --- tuna-camera-sensor-cdp.dts | 2 +- tuna-camera-sensor-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tuna-camera-sensor-cdp.dts b/tuna-camera-sensor-cdp.dts index 70f3e1c0..b9631c5e 100644 --- a/tuna-camera-sensor-cdp.dts +++ b/tuna-camera-sensor-cdp.dts @@ -17,6 +17,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna CDP/RCM"; compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,cdp", "qcom,rcm", "qcom,tuna-rcm"; - qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>, <694 0x10000>, <694 0x20000>; qcom,board-id = <1 0>, <21 0>, <21 1>; }; diff --git a/tuna-camera-sensor-mtp.dts b/tuna-camera-sensor-mtp.dts index 1f6d39a1..1b06b857 100644 --- a/tuna-camera-sensor-mtp.dts +++ b/tuna-camera-sensor-mtp.dts @@ -17,6 +17,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>; + qcom,msm-id = <655 0x10000>, <655 0x20000>, <681 0x10000>, <681 0x20000>, <694 0x10000>, <694 0x20000>; qcom,board-id = <8 0>, <8 1>, <8 2>, <8 3>, <8 4>; }; From f8853a58724bd8a90f074d3e9369e8f5cda1d92a Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Wed, 30 Oct 2024 17:21:15 +0530 Subject: [PATCH 261/274] ARM: dts: msm: Update sensors load current for Tuna Update VAF load current(uA) of IMX766/JN1 sensors and its sub devices. CRs-Fixed: 3963500. Change-Id: I5ee5a6e41dd5e83908e5545547be8531f98bae32 Signed-off-by: Shadul Shaikh --- tuna-camera-sensor-mtp.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tuna-camera-sensor-mtp.dtsi b/tuna-camera-sensor-mtp.dtsi index 3e2ff6fd..7d5bd2a7 100644 --- a/tuna-camera-sensor-mtp.dtsi +++ b/tuna-camera-sensor-mtp.dtsi @@ -48,7 +48,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103000>; + rgltr-load-current = <118930>; status = "ok"; }; @@ -76,7 +76,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 2800000 0>; rgltr-max-voltage = <1980000 3000000 0>; - rgltr-load-current = <3500 214290 0>; + rgltr-load-current = <3500 220000 0>; status = "ok"; }; @@ -94,7 +94,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -174,7 +174,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -250,7 +250,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103040>; + rgltr-load-current = <130040>; status = "ok"; }; @@ -267,7 +267,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4500 266330 0 69000 103040>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active @@ -310,7 +310,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4500 266330 0 69000 103040>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active From 2d64152f073c74830fdcdb4dd2dec7000d3b8b92 Mon Sep 17 00:00:00 2001 From: Mukund Deshmukh Date: Tue, 3 Dec 2024 10:15:34 +0530 Subject: [PATCH 262/274] ARM: dts: msm: Updation of RST2 config parameters RS2 configuration updation with removal of apps and remote attributes. CRs-Fixed: 3989900. Change-Id: I2b5dc440e1e8979f3e83a7914b6c82f425e8779d --- kera-camera.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 790ff951..44b6cee8 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -411,7 +411,6 @@ pins = "gpio125"; bias-disable; /* No PULL */ drive-strength = <2>; /* 2 MA */ - qcom,apps; }; }; @@ -426,7 +425,6 @@ bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ output-low; - qcom,remote; }; }; From 6276bd54898837ff1d5e837b032d679e8c386067 Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Thu, 21 Nov 2024 15:35:02 +0800 Subject: [PATCH 263/274] ARM: dts: msm: hdk rotate 180 degree for rear camera - HDK roll 180 degree compare to mtp/qrd. - Change dtsi roll degree of hdk. CRs-Fixed: 3979998 Change-Id: I2f067dcf135443a04881257f840bf2ee87298473 Signed-off-by: Pengfei Liu --- config/sun.mk | 1 + sun-camera-sensor-hdk.dts | 24 ++ sun-camera-sensor-hdk.dtsi | 782 +++++++++++++++++++++++++++++++++++++ sun-camera-sensor-qrd.dts | 2 +- 4 files changed, 808 insertions(+), 1 deletion(-) create mode 100644 sun-camera-sensor-hdk.dts create mode 100644 sun-camera-sensor-hdk.dtsi diff --git a/config/sun.mk b/config/sun.mk index 43a8a45f..022fef7e 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -2,6 +2,7 @@ dtbo-$(CONFIG_ARCH_SUN) := sun-camera.dtbo dtbo-$(CONFIG_ARCH_SUN) += sun-camera-sensor-mtp.dtbo \ sun-camera-sensor-rumi.dtbo \ sun-camera-sensor-cdp.dtbo \ + sun-camera-sensor-hdk.dtbo \ sun-camera-sensor-qrd.dtbo dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo diff --git a/sun-camera-sensor-hdk.dts b/sun-camera-sensor-hdk.dts new file mode 100644 index 00000000..2baad661 --- /dev/null +++ b/sun-camera-sensor-hdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "sun-camera-sensor-hdk.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun QRD"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x1001F 0>; +}; diff --git a/sun-camera-sensor-hdk.dtsi b/sun-camera-sensor-hdk.dtsi new file mode 100644 index 00000000..76fa011a --- /dev/null +++ b/sun-camera-sensor-hdk.dtsi @@ -0,0 +1,782 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_asc_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5M>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 220000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c3 { + se-clock-frequency = <64000000>; + i3c-scl-hz = <8300000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_UW_asc_rear: qcom,actuator@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_asc_rear: qcom,eeprom@50 { + cell-index = <6>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_i3c_UltraWide: qcom,eeprom@52 { + cell-index = <1>; + reg = <0x52 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@33,36008580000 { + cell-index = <1>; + reg = <0x33 0x360 0x08580000>; + assigned-address = <0xa>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_UltraWide>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + i3c-target; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_i3cSelect_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_i3cSelect_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_I3CSELECT"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_asc_rear>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_asc_rear>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 7a25dd6f..2c5a52f9 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -20,5 +20,5 @@ qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>, <0x100027f 0x10000>, <0x100027f 0x20000>; - qcom,board-id = <0x1000B 0>, <0x1001F 0>, <0x2000B 0>, <0x3000B 0>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; }; From 64ec3483c81252848079dc9ddc01c53a8dd75c65 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Fri, 13 Dec 2024 15:34:02 +0530 Subject: [PATCH 264/274] ARM: dts: msm: Update UBWC configuration for Kera This change updates UBWC configuration to be used for Kera LP4 device. CRs-Fixed: 4001817 Change-Id: I5dd36264a270564f59ea32b2cbe34f7086e5254c --- kera-camera.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 790ff951..fd1703b7 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -2048,7 +2048,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "tfe_0_clk_src"; clock-control-debugfs = "true"; - ubwc-static-cfg = <0x1026 0x1026>; + ubwc-static-cfg = <0x1016 0x1026>; cam_hw_pid = <0 9 16 4>; status = "ok"; }; @@ -2124,7 +2124,7 @@ "turbo"; src-clock-name = "tfe_1_clk_src"; clock-control-debugfs = "true"; - ubwc-static-cfg = <0x1026 0x1026>; + ubwc-static-cfg = <0x1016 0x1026>; cam_hw_pid = <1 10 17 5>; status = "ok"; }; @@ -2199,7 +2199,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "tfe_2_clk_src"; clock-control-debugfs = "true"; - ubwc-static-cfg = <0x1026 0x1026>; + ubwc-static-cfg = <0x1016 0x1026>; cam_hw_pid = <2 8 18 6>; status = "ok"; }; @@ -2342,8 +2342,8 @@ src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; fw_name = "CAMERA_ICP_970"; - ubwc-ipe-fetch-cfg = <0x707B 0x707B>; - ubwc-ipe-write-cfg = <0x161EF 0x161EF>; + ubwc-ipe-fetch-cfg = <0x7073 0x707B>; + ubwc-ipe-write-cfg = <0x161CF 0x161EF>; qos-val = <0x808>; fw-pas-id = <33>; cam_hw_pid = <11>; @@ -2384,8 +2384,8 @@ src-clock-name = "icp_1_clk_src"; clock-control-debugfs = "true"; fw_name = "CAMERA_ICP_1_970"; - ubwc-ofe-fetch-cfg = <0x707B 0x707B>; - ubwc-ofe-write-cfg = <0x161EF 0x161EF>; + ubwc-ofe-fetch-cfg = <0x7073 0x707B>; + ubwc-ofe-write-cfg = <0x161CF 0x161EF>; qos-val = <0x808>; fw-pas-id = <50>; cam_hw_pid = <10>; From c0a392f34346dba9ebe4671b7e7b4b93c4eb7991 Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Thu, 21 Nov 2024 15:35:02 +0800 Subject: [PATCH 265/274] ARM: dts: msm: hdk rotate 180 degree for rear camera - HDK roll 180 degree compare to mtp/qrd. - Change dtsi roll degree of hdk. CRs-Fixed: 3979998 Change-Id: I2f067dcf135443a04881257f840bf2ee87298473 Signed-off-by: Pengfei Liu (cherry picked from commit a49bf9e65a06b310396786c879737759683f1bef) --- config/sun.mk | 1 + sun-camera-sensor-hdk.dts | 24 ++ sun-camera-sensor-hdk.dtsi | 782 +++++++++++++++++++++++++++++++++++++ sun-camera-sensor-qrd.dts | 2 +- 4 files changed, 808 insertions(+), 1 deletion(-) create mode 100644 sun-camera-sensor-hdk.dts create mode 100644 sun-camera-sensor-hdk.dtsi diff --git a/config/sun.mk b/config/sun.mk index 43a8a45f..022fef7e 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -2,6 +2,7 @@ dtbo-$(CONFIG_ARCH_SUN) := sun-camera.dtbo dtbo-$(CONFIG_ARCH_SUN) += sun-camera-sensor-mtp.dtbo \ sun-camera-sensor-rumi.dtbo \ sun-camera-sensor-cdp.dtbo \ + sun-camera-sensor-hdk.dtbo \ sun-camera-sensor-qrd.dtbo dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo diff --git a/sun-camera-sensor-hdk.dts b/sun-camera-sensor-hdk.dts new file mode 100644 index 00000000..2baad661 --- /dev/null +++ b/sun-camera-sensor-hdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#include "sun-camera-sensor-hdk.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun QRD"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x1001F 0>; +}; diff --git a/sun-camera-sensor-hdk.dtsi b/sun-camera-sensor-hdk.dtsi new file mode 100644 index 00000000..76fa011a --- /dev/null +++ b/sun-camera-sensor-hdk.dtsi @@ -0,0 +1,782 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +&soc { + led_flash_triple_rear_wide: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_tele: qcom,camera-flash2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_ultrawide: qcom,camera-flash3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_asc_rear: qcom,camera-flash4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8550_flash0 &pm8550_flash1>; + torch-source = <&pm8550_torch0 &pm8550_torch1>; + switch-source = <&pm8550_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + + actuator_triple_wide: qcom,actuator2 { + cell-index = <2>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <119000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + ois_wide: qcom,ois0 { + cell-index = <2>; + compatible = "qcom,ois"; + cci-master = ; + cam_vio-supply = <&L5M>; + cam_vaf-supply = <&L7M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio","cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2960000 0>; + rgltr-max-voltage = <1800000 2960000 0>; + rgltr-load-current = <4000 220000 0>; + status = "ok"; + }; + + eeprom_tof1: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_wide>; + ois-src = <&ois_wide>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear_wide>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L3N>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 1800000>; + rgltr-load-current = <4000 913000 0 91400 119000 63100>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 90 0>, + <&tlmm 15 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + cam_v_custom1-supply = <&L6M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_vaf", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 2960000 2800000>; + rgltr-load-current = <6400 850000 0 114500 100000 140000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 89 0>, + <&tlmm 13 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci1 { + actuator_triple_tele: qcom,actuator3{ + cell-index = <3>; + compatible = "qcom,actuator"; + cci-master = ; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_tele>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L2M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L4M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", + "cam_vana", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-max-voltage = <1800000 1056000 0 2800000 2960000>; + rgltr-load-current = <4000 260700 0 67700 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 92 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + +}; + +&cam_cci2 { + eeprom_tof2: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof2>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&S7I>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L5N>; + cam_v_custom1-supply = <&L7N>; + cam_v_custom2-supply = <&DBO3>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3304000 3600000>; + rgltr-max-voltage = <1800000 1340000 0 2800000 3304000 3600000>; + rgltr-load-current = <155000 680000 0 50000 30000 2500000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 94 0>, + <&tlmm 110 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = ; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + qcom,high-perf; + qcom,clk-freq-out = <1000000>; + qcom,pm-ctrl-client; + + eeprom_asc_front: qcom,eeprom1 { + cell-index = <4>; + reg = <0x58>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <4>; + reg = <0x22>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_asc_front>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L2N>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L6N>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1200000 1104000 0 2800000>; + rgltr-max-voltage = <1200000 1104000 0 2800000>; + rgltr-load-current = <3000 283000 0 50000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 93 0>, + <&tlmm 7 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&i3c3 { + se-clock-frequency = <64000000>; + i3c-scl-hz = <8300000>; + dfs-index = <0>; + i2c-scl-hz = <1000000>; + qcom,pm-ctrl-client; + status = "ok"; + + actuator_UW_asc_rear: qcom,actuator@c { + cell-index = <1>; + compatible = "qcom,cam-i2c-actuator"; + reg = <0x0C 0x00 0x10>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2960000>; + rgltr-max-voltage = <2960000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_asc_rear: qcom,eeprom@50 { + cell-index = <6>; + reg = <0x50 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_i3c_UltraWide: qcom,eeprom@52 { + cell-index = <1>; + reg = <0x52 0x00 0x10>; + compatible = "qcom,cam-i2c-eeprom"; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@33,36008580000 { + cell-index = <1>; + reg = <0x33 0x360 0x08580000>; + assigned-address = <0xa>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_i3c_UltraWide>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_triple_rear_ultrawide>; + cam_vio-supply = <&L1I>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + i3c-target; + rgltr-min-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-max-voltage = <1200000 1104000 0 2800000 2960000>; + rgltr-load-current = <3000 355000 0 95000 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_i3cSelect_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_i3cSelect_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 6 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_I3CSELECT"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor@10 { + cell-index = <6>; + reg = <0x10 0x00 0x10>; + compatible = "qcom,cam-i2c-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_asc_rear>; + actuator-src = <&actuator_UW_asc_rear>; + led-flash-src = <&led_flash_asc_rear>; + cam_vio-supply = <&L5M>; + cam_vdig-supply = <&L1M>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&L3M>; + cam_v_custom1-supply = <&L4N>; + cam_vaf-supply = <&L7M>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana", + "cam_v_custom1", "cam_vaf"; + rgltr-cntrl-support; + aon-camera-id = ; + rgltr-min-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-max-voltage = <1800000 1104000 0 2800000 1800000 2960000>; + rgltr-load-current = <6000 454000 0 77900 29400 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2 + &cam_sensor_ponv_rear_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2 + &cam_sensor_ponv_rear_suspend>; + gpios = <&tlmm 91 0>, + <&tlmm 3 0>, + <&tlmm 2 0>; + gpio-reset = <1>; + gpio-standby = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY"; + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/sun-camera-sensor-qrd.dts b/sun-camera-sensor-qrd.dts index 7a25dd6f..2c5a52f9 100644 --- a/sun-camera-sensor-qrd.dts +++ b/sun-camera-sensor-qrd.dts @@ -20,5 +20,5 @@ qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>, <0x100027f 0x10000>, <0x100027f 0x20000>; - qcom,board-id = <0x1000B 0>, <0x1001F 0>, <0x2000B 0>, <0x3000B 0>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; }; From f0fccb156b576880ba3e829562efce2704ac8cc6 Mon Sep 17 00:00:00 2001 From: Mukund Deshmukh Date: Wed, 11 Dec 2024 17:19:28 +0530 Subject: [PATCH 266/274] ARM: dts: msm: Current values updation based on latest PG Current values of regulators for below are modified as per PG - IMX766 - IMX858 - IMX688 - S5KJN1 - PHY CRs-Fixed: 3989900. Change-Id: Id399d21fef2831da3de77248b992017183184da5 --- kera-camera-sensor-mtp.dtsi | 24 +++++++++++----------- kera-camera.dtsi | 41 +++++++++++++++++++++++++++++++------ 2 files changed, 47 insertions(+), 18 deletions(-) diff --git a/kera-camera-sensor-mtp.dtsi b/kera-camera-sensor-mtp.dtsi index bfd880a2..acc3c9d0 100644 --- a/kera-camera-sensor-mtp.dtsi +++ b/kera-camera-sensor-mtp.dtsi @@ -48,7 +48,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103000>; + rgltr-load-current = <118930>; status = "ok"; }; @@ -62,7 +62,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103000>; + rgltr-load-current = <103360>; status = "ok"; }; @@ -78,7 +78,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 2800000 0>; rgltr-max-voltage = <1980000 3000000 0>; - rgltr-load-current = <3500 214290 0>; + rgltr-load-current = <3500 220000 0>; status = "ok"; }; @@ -97,7 +97,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -133,7 +133,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1100000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; - rgltr-load-current = <3500 522730 0 107140 103000>; + rgltr-load-current = <4060 523640 0 107500 103360>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -176,7 +176,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1100000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; - rgltr-load-current = <3500 522730 0 107140 103000>; + rgltr-load-current = <4060 523640 0 107500 103360>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -221,7 +221,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -255,7 +255,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <130000>; + rgltr-load-current = <130040>; status = "ok"; }; @@ -273,7 +273,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4000 261000 0 68000 130000>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active @@ -309,7 +309,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; - rgltr-load-current = <5000 453330 0 77500 28890>; + rgltr-load-current = <5560 454290 0 77860 29440>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active @@ -350,7 +350,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; - rgltr-load-current = <5000 453330 0 77500 28890>; + rgltr-load-current = <5560 454290 0 77860 29440>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active @@ -393,7 +393,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4000 261000 0 68000 130000>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 790ff951..c08f5417 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -487,7 +487,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy0_clk", @@ -521,7 +521,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy1_clk", @@ -555,7 +555,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy2_clk", @@ -576,7 +576,7 @@ cam_csiphy3: qcom,csiphy3@adaf000 { cell-index = <3>; - compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; reg = <0x0adaf000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0x1af000>; @@ -589,7 +589,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy3_clk", @@ -840,6 +840,35 @@ status = "ok"; }; + cam_csiphy_tpg15: qcom,tpg15@ad8c000 { + cell-index = <15>; + phy-id = <1>; + hw-no-ops; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0x0ad8c000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18c000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "svs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; @@ -1214,7 +1243,7 @@ "ife0", "ife1", "ife2", "ife3", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", - "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14"; + "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14", "tpg15"; sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; sys-cache-uids = <71 72 73 74 75>; sys-cache-concur = <1 1 1 0 0>; From dace183b9ef763348f2eeccb115c61c2ffcd90de Mon Sep 17 00:00:00 2001 From: Mukund Deshmukh Date: Tue, 3 Dec 2024 10:15:34 +0530 Subject: [PATCH 267/274] ARM: dts: msm: Updation of RST2 config parameters RS2 configuration updation with removal of apps and remote attributes. CRs-Fixed: 3989900. Change-Id: I2b5dc440e1e8979f3e83a7914b6c82f425e8779d (cherry picked from commit 2d64152f073c74830fdcdb4dd2dec7000d3b8b92) --- kera-camera.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 790ff951..44b6cee8 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -411,7 +411,6 @@ pins = "gpio125"; bias-disable; /* No PULL */ drive-strength = <2>; /* 2 MA */ - qcom,apps; }; }; @@ -426,7 +425,6 @@ bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ output-low; - qcom,remote; }; }; From 5520759749cbcab531c409c18957b629d206ef70 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Fri, 13 Dec 2024 15:34:02 +0530 Subject: [PATCH 268/274] ARM: dts: msm: Update UBWC configuration for Kera This change updates UBWC configuration to be used for Kera LP4 device. CRs-Fixed: 4001817 Change-Id: I5dd36264a270564f59ea32b2cbe34f7086e5254c --- kera-camera.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 790ff951..fd1703b7 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -2048,7 +2048,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "tfe_0_clk_src"; clock-control-debugfs = "true"; - ubwc-static-cfg = <0x1026 0x1026>; + ubwc-static-cfg = <0x1016 0x1026>; cam_hw_pid = <0 9 16 4>; status = "ok"; }; @@ -2124,7 +2124,7 @@ "turbo"; src-clock-name = "tfe_1_clk_src"; clock-control-debugfs = "true"; - ubwc-static-cfg = <0x1026 0x1026>; + ubwc-static-cfg = <0x1016 0x1026>; cam_hw_pid = <1 10 17 5>; status = "ok"; }; @@ -2199,7 +2199,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "tfe_2_clk_src"; clock-control-debugfs = "true"; - ubwc-static-cfg = <0x1026 0x1026>; + ubwc-static-cfg = <0x1016 0x1026>; cam_hw_pid = <2 8 18 6>; status = "ok"; }; @@ -2342,8 +2342,8 @@ src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; fw_name = "CAMERA_ICP_970"; - ubwc-ipe-fetch-cfg = <0x707B 0x707B>; - ubwc-ipe-write-cfg = <0x161EF 0x161EF>; + ubwc-ipe-fetch-cfg = <0x7073 0x707B>; + ubwc-ipe-write-cfg = <0x161CF 0x161EF>; qos-val = <0x808>; fw-pas-id = <33>; cam_hw_pid = <11>; @@ -2384,8 +2384,8 @@ src-clock-name = "icp_1_clk_src"; clock-control-debugfs = "true"; fw_name = "CAMERA_ICP_1_970"; - ubwc-ofe-fetch-cfg = <0x707B 0x707B>; - ubwc-ofe-write-cfg = <0x161EF 0x161EF>; + ubwc-ofe-fetch-cfg = <0x7073 0x707B>; + ubwc-ofe-write-cfg = <0x161CF 0x161EF>; qos-val = <0x808>; fw-pas-id = <50>; cam_hw_pid = <10>; From ca9e46fbf34c4637b023b7a309a521428e5cdae6 Mon Sep 17 00:00:00 2001 From: Mukund Deshmukh Date: Wed, 11 Dec 2024 17:19:28 +0530 Subject: [PATCH 269/274] ARM: dts: msm: Current values updation based on latest PG Current values of regulators for below are modified as per PG - IMX766 - IMX858 - IMX688 - S5KJN1 - PHY CRs-Fixed: 3989900. Change-Id: Id399d21fef2831da3de77248b992017183184da5 --- kera-camera-sensor-mtp.dtsi | 24 +++++++++++----------- kera-camera.dtsi | 41 +++++++++++++++++++++++++++++++------ 2 files changed, 47 insertions(+), 18 deletions(-) diff --git a/kera-camera-sensor-mtp.dtsi b/kera-camera-sensor-mtp.dtsi index bfd880a2..acc3c9d0 100644 --- a/kera-camera-sensor-mtp.dtsi +++ b/kera-camera-sensor-mtp.dtsi @@ -48,7 +48,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103000>; + rgltr-load-current = <118930>; status = "ok"; }; @@ -62,7 +62,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <103000>; + rgltr-load-current = <103360>; status = "ok"; }; @@ -78,7 +78,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 2800000 0>; rgltr-max-voltage = <1980000 3000000 0>; - rgltr-load-current = <3500 214290 0>; + rgltr-load-current = <3500 220000 0>; status = "ok"; }; @@ -97,7 +97,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -133,7 +133,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1100000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; - rgltr-load-current = <3500 522730 0 107140 103000>; + rgltr-load-current = <4060 523640 0 107500 103360>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -176,7 +176,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1100000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000>; - rgltr-load-current = <3500 522730 0 107140 103000>; + rgltr-load-current = <4060 523640 0 107500 103360>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -221,7 +221,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1104000 0 2800000 2800000 1800000>; rgltr-max-voltage = <1980000 1200000 0 2900000 3000000 1900000>; - rgltr-load-current = <3500 913200 0 91430 103000 63100>; + rgltr-load-current = <3500 913200 0 91430 118930 63100>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -255,7 +255,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <3000000>; - rgltr-load-current = <130000>; + rgltr-load-current = <130040>; status = "ok"; }; @@ -273,7 +273,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4000 261000 0 68000 130000>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active @@ -309,7 +309,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; - rgltr-load-current = <5000 453330 0 77500 28890>; + rgltr-load-current = <5560 454290 0 77860 29440>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active @@ -350,7 +350,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 1800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 1900000>; - rgltr-load-current = <5000 453330 0 77500 28890>; + rgltr-load-current = <5560 454290 0 77860 29440>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk3_active @@ -393,7 +393,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <1800000 1056000 0 2800000 2800000>; rgltr-max-voltage = <1980000 1150000 0 2900000 3000000>; - rgltr-load-current = <4000 261000 0 68000 130000>; + rgltr-load-current = <4500 266330 0 69000 130040>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 790ff951..c08f5417 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -487,7 +487,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy0_clk", @@ -521,7 +521,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy1_clk", @@ -555,7 +555,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy2_clk", @@ -576,7 +576,7 @@ cam_csiphy3: qcom,csiphy3@adaf000 { cell-index = <3>; - compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.1", "qcom,csiphy"; reg = <0x0adaf000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0x1af000>; @@ -589,7 +589,7 @@ rgltr-cntrl-support; rgltr-min-voltage = <0 1200000 880000>; rgltr-max-voltage = <0 1320000 950000>; - rgltr-load-current = <0 14120 145800>; + rgltr-load-current = <0 7810 82290>; shared-clks = <1 0 0 0>; clock-names = "cphy_rx_clk_src", "csiphy3_clk", @@ -840,6 +840,35 @@ status = "ok"; }; + cam_csiphy_tpg15: qcom,tpg15@ad8c000 { + cell-index = <15>; + phy-id = <1>; + hw-no-ops; + compatible = "qcom,cam-tpg104"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0x0ad8c000 0x400>, + <0x0ac04000 0x1000>; + reg-cam-base = <0x18c000 0x04000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + shared-clks = <1 0>; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0>, + <400000000 0>, + <480000000 0>; + clock-cntl-level = "lowsvs", "svs", "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; @@ -1214,7 +1243,7 @@ "ife0", "ife1", "ife2", "ife3", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", - "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14"; + "jpeg-dma0", "jpeg-enc0", "tpg13", "tpg14", "tpg15"; sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; sys-cache-uids = <71 72 73 74 75>; sys-cache-concur = <1 1 1 0 0>; From 9144871df1e9ee482ac70c93a530e0c49934b198 Mon Sep 17 00:00:00 2001 From: Dharmender Sharma Date: Wed, 18 Dec 2024 10:58:04 +0530 Subject: [PATCH 270/274] ARM: dts: msm: Add labels to camera nodes Adding labels to nodes help in faster fetching of the nodes. This commit adds labels to missing nodes. CRs-Fixed: 4013261 Change-Id: I088fc1fcd44836e0739c1fdaf7a4c86634f2eb52 Signed-off-by: Dharmender Sharma --- kera-camera.dtsi | 26 +++++++++++++------------- sun-camera.dtsi | 28 ++++++++++++++-------------- tuna-camera.dtsi | 28 ++++++++++++++-------------- 3 files changed, 41 insertions(+), 41 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 0054234b..2b273509 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -461,12 +461,12 @@ #size-cells = <1>; interrupt-parent = <&intc>; - qcom,cam-req-mgr { + cam_req_mgr: qcom,cam-req-mgr { compatible = "qcom,cam-req-mgr"; status = "ok"; }; - qcom,cam-sync { + cam_sync: qcom,cam-sync { compatible = "qcom,cam-sync"; status = "ok"; }; @@ -867,7 +867,7 @@ status = "ok"; }; - qcom,cam_smmu { + cam_smmu: qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; @@ -1125,7 +1125,7 @@ }; }; - qcom,cam-cpas@ac04000 { + cam_cpas: qcom,cam-cpas@ac04000 { cell-index = <0>; compatible = "qcom,cam-cpas"; label = "cpas"; @@ -1888,7 +1888,7 @@ }; }; - qcom,cam-cdm-intf { + cam_cdm_intf: qcom,cam-cdm-intf { compatible = "qcom,cam-cdm-intf"; cell-index = <0>; label = "cam-cdm-intf"; @@ -1899,7 +1899,7 @@ status = "ok"; }; - qcom,rt-cdm0@ac7f000 { + cam_rt_cdm0: qcom,rt-cdm0@ac7f000 { cell-index = <0>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -1924,7 +1924,7 @@ status = "ok"; }; - qcom,rt-cdm1@ac80000 { + cam_rt_cdm1: qcom,rt-cdm1@ac80000 { cell-index = <1>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -1949,7 +1949,7 @@ status = "ok"; }; - qcom,rt-cdm2@ac81000 { + cam_rt_cdm2: qcom,rt-cdm2@ac81000 { cell-index = <2>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -1974,7 +1974,7 @@ status = "ok"; }; - qcom,rt-cdm3@ac82000 { + cam_rt_cdm3: qcom,rt-cdm3@ac82000 { cell-index = <3>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -1999,7 +1999,7 @@ status = "ok"; }; - qcom,cam-isp { + cam_isp: qcom,cam-isp { compatible = "qcom,cam-isp"; arch-compat = "mc_tfe"; status = "ok"; @@ -2308,7 +2308,7 @@ status = "ok"; }; - qcom,cam-icp0 { + icp0: qcom,cam-icp0 { compatible = "qcom,cam-icp0"; cell-index = <0>; compat-hw-name = "qcom,icp0", @@ -2322,7 +2322,7 @@ synx_signaling_en; }; - qcom,cam-icp1 { + icp1: qcom,cam-icp1 { compatible = "qcom,cam-icp1"; cell-index = <1>; compat-hw-name = "qcom,icp1", @@ -2503,7 +2503,7 @@ status = "ok"; }; - qcom,cam-jpeg { + cam_jpeg: qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; diff --git a/sun-camera.dtsi b/sun-camera.dtsi index 7adef2b5..dbd4c592 100644 --- a/sun-camera.dtsi +++ b/sun-camera.dtsi @@ -858,12 +858,12 @@ #size-cells = <1>; interrupt-parent = <&intc>; - qcom,cam-req-mgr { + cam_req_mgr: qcom,cam-req-mgr { compatible = "qcom,cam-req-mgr"; status = "ok"; }; - qcom,cam-sync { + cam_sync: qcom,cam-sync { compatible = "qcom,cam-sync"; status = "ok"; }; @@ -1344,7 +1344,7 @@ }; }; - qcom,cam_smmu { + cam_smmu: qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; @@ -1606,7 +1606,7 @@ }; }; - qcom,cam-cpas@ac13000 { + cam_cpas: qcom,cam-cpas@ac13000 { cell-index = <0>; compatible = "qcom,cam-cpas"; label = "cpas"; @@ -2473,7 +2473,7 @@ }; }; - qcom,cam-cdm-intf { + cam_cdm_intf: qcom,cam-cdm-intf { compatible = "qcom,cam-cdm-intf"; cell-index = <0>; label = "cam-cdm-intf"; @@ -2484,7 +2484,7 @@ status = "ok"; }; - qcom,rt-cdm0@ac7f000 { + cam_rt_cdm0: qcom,rt-cdm0@ac7f000 { cell-index = <0>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2509,7 +2509,7 @@ status = "ok"; }; - qcom,rt-cdm1@ac80000 { + cam_rt_cdm1: qcom,rt-cdm1@ac80000 { cell-index = <1>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2534,7 +2534,7 @@ status = "ok"; }; - qcom,rt-cdm2@ac81000 { + cam_rt_cdm2: qcom,rt-cdm2@ac81000 { cell-index = <2>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2559,7 +2559,7 @@ status = "ok"; }; - qcom,rt-cdm3@ac82000 { + cam_rt_cdm3: qcom,rt-cdm3@ac82000 { cell-index = <3>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2584,7 +2584,7 @@ status = "ok"; }; - qcom,rt-cdm4@ac83000 { + cam_rt_cdm4: qcom,rt-cdm4@ac83000 { cell-index = <4>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2609,7 +2609,7 @@ status = "ok"; }; - qcom,cam-isp { + cam_isp: qcom,cam-isp { compatible = "qcom,cam-isp"; arch-compat = "mc_tfe"; status = "ok"; @@ -3095,7 +3095,7 @@ status = "ok"; }; - qcom,cam-icp0 { + icp0: qcom,cam-icp0 { compatible = "qcom,cam-icp0"; cell-index = <0>; compat-hw-name = "qcom,icp0", @@ -3109,7 +3109,7 @@ synx_signaling_en; }; - qcom,cam-icp1 { + icp1: qcom,cam-icp1 { compatible = "qcom,cam-icp1"; cell-index = <1>; compat-hw-name = "qcom,icp1", @@ -3298,7 +3298,7 @@ status = "ok"; }; - qcom,cam-jpeg { + cam_jpeg: qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; diff --git a/tuna-camera.dtsi b/tuna-camera.dtsi index bc066f1e..e2cf7633 100644 --- a/tuna-camera.dtsi +++ b/tuna-camera.dtsi @@ -491,12 +491,12 @@ #size-cells = <1>; interrupt-parent = <&intc>; - qcom,cam-req-mgr { + cam_req_mgr: qcom,cam-req-mgr { compatible = "qcom,cam-req-mgr"; status = "ok"; }; - qcom,cam-sync { + cam_sync: qcom,cam-sync { compatible = "qcom,cam-sync"; status = "ok"; }; @@ -847,7 +847,7 @@ }; }; - qcom,cam_smmu { + cam_smmu: qcom,cam_smmu { compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; @@ -1109,7 +1109,7 @@ }; }; - qcom,cam-cpas@ac13000 { + cam_cpas: qcom,cam-cpas@ac13000 { cell-index = <0>; compatible = "qcom,cam-cpas"; label = "cpas"; @@ -1932,7 +1932,7 @@ }; }; - qcom,cam-cdm-intf { + cam_cdm_intf: qcom,cam-cdm-intf { compatible = "qcom,cam-cdm-intf"; cell-index = <0>; label = "cam-cdm-intf"; @@ -1943,7 +1943,7 @@ status = "ok"; }; - qcom,rt-cdm0@ac7f000 { + cam_rt_cdm0: qcom,rt-cdm0@ac7f000 { cell-index = <0>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -1968,7 +1968,7 @@ status = "ok"; }; - qcom,rt-cdm1@ac80000 { + cam_rt_cdm1: qcom,rt-cdm1@ac80000 { cell-index = <1>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -1993,7 +1993,7 @@ status = "ok"; }; - qcom,rt-cdm2@ac81000 { + cam_rt_cdm2: qcom,rt-cdm2@ac81000 { cell-index = <2>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2018,7 +2018,7 @@ status = "ok"; }; - qcom,rt-cdm3@ac82000 { + cam_rt_cdm3: qcom,rt-cdm3@ac82000 { cell-index = <3>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2043,7 +2043,7 @@ status = "ok"; }; - qcom,rt-cdm4@ac83000 { + cam_rt_cdm4: qcom,rt-cdm4@ac83000 { cell-index = <4>; compatible = "qcom,cam-rt-cdm2_2"; label = "rt-cdm"; @@ -2068,7 +2068,7 @@ status = "ok"; }; - qcom,cam-isp { + cam_isp: qcom,cam-isp { compatible = "qcom,cam-isp"; arch-compat = "mc_tfe"; status = "ok"; @@ -2554,7 +2554,7 @@ status = "ok"; }; - qcom,cam-icp0 { + icp0: qcom,cam-icp0 { compatible = "qcom,cam-icp0"; cell-index = <0>; compat-hw-name = "qcom,icp0", @@ -2568,7 +2568,7 @@ synx_signaling_en; }; - qcom,cam-icp1 { + icp1: qcom,cam-icp1 { compatible = "qcom,cam-icp1"; cell-index = <1>; compat-hw-name = "qcom,icp1", @@ -2757,7 +2757,7 @@ status = "ok"; }; - qcom,cam-jpeg { + cam_jpeg: qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; From bd5e77ea6b63f25212cd506fec258795f1639cfe Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 31 Dec 2024 13:22:11 +0530 Subject: [PATCH 271/274] ARM: dts: msm: Add support for resource resets for Eliza Add reset support for GCC axi RT/NRT resources. This is HW WA fix for DDR 2.1 Ghz. CRs-Fixed: 4013241 Change-Id: I4158d337ff4f5d83ce1919939ab1d9d3e65c8fcc --- kera-camera.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 0054234b..a1557f07 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -1255,6 +1255,24 @@ rt-wr-highstress-indicator-threshold = <50>; rt-wr-lowstress-indicator-threshold = <0>; rt-wr-bw-ratio-scale-factor = <1>; + + resets = <&gcc GCC_CAMERA_HF_AXI_SLP_STG_ARES>, + <&gcc GCC_CAMERA_SF_AXI_SLP_STG_ARES>, + <&gcc GCC_CAMERA_HF_AXI_SEL_SLP_STG_ARES>, + <&gcc GCC_CAMERA_SF_AXI_SEL_SLP_STG_ARES>, + <&gcc GCC_CAMERA_SF_CLK_EN_SLP_STG>, + <&gcc GCC_CAMERA_SF_CLK_EN_SEL_SLP_STG>, + <&gcc GCC_CAMERA_HF_CLK_EN_SLP_STG>, + <&gcc GCC_CAMERA_HF_CLK_EN_SEL_SLP_STG>; + reset-names = "hf_slp_stg_ares", + "sf_slp_stg_ares", + "hf_sel_slp_stg_ares", + "sf_sel_slp_stg_ares", + "sf_clk_en_slp_stg", + "sf_clk_en_sel_slp_stg", + "hf_clk_en_slp_stg", + "hf_clk_en_sel_slp_stg"; + status = "ok"; camera-bus-nodes { From d0754efdfa55db6812a885f01dab3caa21a6cbdf Mon Sep 17 00:00:00 2001 From: Bhasker Reddy Komatireddy Date: Tue, 7 Jan 2025 15:12:58 +0530 Subject: [PATCH 272/274] ARM: dts: msm: add kera-iot board support for kera CDP platform add camera dts support for kera-iot board on kera CDP platform CRs-Fixed: 4018699. Change-Id: I490956171e6d2f0ef2947e54aa99f3c26e142b8e --- kera-camera-sensor-cdp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kera-camera-sensor-cdp.dts b/kera-camera-sensor-cdp.dts index 2c23c69f..cde5764b 100644 --- a/kera-camera-sensor-cdp.dts +++ b/kera-camera-sensor-cdp.dts @@ -19,5 +19,5 @@ compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", "qcom,cdp"; qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; - qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>, <0x50001 0>; }; From aceed16cd563bd97479a8fae8144fb65ff5bbe1b Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 31 Dec 2024 13:22:11 +0530 Subject: [PATCH 273/274] ARM: dts: msm: Add support for resource resets for Eliza Add reset support for GCC axi RT/NRT resources. This is HW WA fix for DDR 2.1 Ghz. CRs-Fixed: 4013241 Change-Id: I4158d337ff4f5d83ce1919939ab1d9d3e65c8fcc --- kera-camera.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index 0054234b..a1557f07 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -1255,6 +1255,24 @@ rt-wr-highstress-indicator-threshold = <50>; rt-wr-lowstress-indicator-threshold = <0>; rt-wr-bw-ratio-scale-factor = <1>; + + resets = <&gcc GCC_CAMERA_HF_AXI_SLP_STG_ARES>, + <&gcc GCC_CAMERA_SF_AXI_SLP_STG_ARES>, + <&gcc GCC_CAMERA_HF_AXI_SEL_SLP_STG_ARES>, + <&gcc GCC_CAMERA_SF_AXI_SEL_SLP_STG_ARES>, + <&gcc GCC_CAMERA_SF_CLK_EN_SLP_STG>, + <&gcc GCC_CAMERA_SF_CLK_EN_SEL_SLP_STG>, + <&gcc GCC_CAMERA_HF_CLK_EN_SLP_STG>, + <&gcc GCC_CAMERA_HF_CLK_EN_SEL_SLP_STG>; + reset-names = "hf_slp_stg_ares", + "sf_slp_stg_ares", + "hf_sel_slp_stg_ares", + "sf_sel_slp_stg_ares", + "sf_clk_en_slp_stg", + "sf_clk_en_sel_slp_stg", + "hf_clk_en_slp_stg", + "hf_clk_en_sel_slp_stg"; + status = "ok"; camera-bus-nodes { From ff6aa4f63e4eb984c0c2ccda1b8c6f68d0cdd096 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Tue, 25 Mar 2025 03:20:16 +0530 Subject: [PATCH 274/274] ARM: dts: msm: Remove drv clocks from kera This change removes DRV clocks from Kera devicetree. CRs-Fixed: 4099869 Change-Id: Id6ceee898302168f741a04cfe7f9710c210e62b6 --- kera-camera.dtsi | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index ef0845ed..ae12f682 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1150,13 +1150,11 @@ "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", - "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_top_fast_ahb_clk", "camnoc_rt_axi_clk_src", "camnoc_rt_axi_clk", "camnoc_nrt_axi_clk", - "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = @@ -1166,22 +1164,20 @@ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&camcc CAM_CC_CAM_TOP_AHB_CLK>, <&camcc CAM_CC_CORE_AHB_CLK>, - <&camcc CAM_CC_DRV_AHB_CLK>, <&camcc CAM_CC_FAST_AHB_CLK_SRC>, <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, - <&camcc CAM_CC_DRV_XO_CLK>, <&camcc CAM_CC_PLL0>, <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; clock-rates = - <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + <0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 300000000 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0 0 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0 0 0>; clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "camnoc_rt_axi_clk_src";