From 3bb27e105099c0ed90954c46f356306703a0c53f Mon Sep 17 00:00:00 2001 From: Grace An Date: Mon, 23 Oct 2023 13:33:24 -0700 Subject: [PATCH] ARM: dts: msm: mm-drivers: add soccp dtsi properties to sun target Add dtsi properties for HW Fence Driver to access the phandle of the SOCCP driver, receive IPCC interrupts from SOCCP on the sun target, and map memory for SOCCP access. Change-Id: Iaa5e381fcb38dbb33771e6b15f12d0425e2d1b4b Signed-off-by: Grace An --- bindings/hw-fence.txt | 53 +++++++++++++++++++++++++++++++++++--- hw_fence/sun-hw-fence.dtsi | 9 +++++++ 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/bindings/hw-fence.txt b/bindings/hw-fence.txt index fd36a30e..3e4159ff 100644 --- a/bindings/hw-fence.txt +++ b/bindings/hw-fence.txt @@ -8,9 +8,17 @@ Required properties - qcom,ipcc-reg: Registers ranges for ipcc registers. - qcom,hw-fence-table-entries: A u32 indicating number of entries for the hw-fence table - qcom,hw-fence-queue-entries: A u32 indicating default number of entries for the Queues +- hw_fence@1: Carved-out memory-mapping region, to be used for mapping of global tables and queues + used by the hw-fence driver and fence controller running either in secondary vm or + on SOCCP. +Required properties on targets without SOCCP: - hw_fence@0: Doorbell configuration to communicate with secondary vm through hypervisor. -- hw_fence@1: Carved-out emory-mapping region, to be used for mapping of global tables and queues - used by the hw-fence driver and fence controller running in secondary vm. +Required properties on targets with SOCCP: +- soccp_controller: Phandle for the soccp controller. +- interrupts: Interrupt associated with APSS NS0 (to receive interrupts from SOCCP). +- interrupt-controller: Mark the device node as an interrupt controller. +- #interrupt-cells: Should be one. The first cell is interrupt number. +- iommus: Specifies the SID's used by this context bank. Optional properties: - qcom,hw-fence-ipc-ver: A u32 indicating ipc version. If not provided in device-tree, this is read @@ -39,7 +47,44 @@ Optional properties: indexes by payloads instead of default dwords -Example: +Example for target with SOCCP: + msm_hw_fence: qcom,hw-fence { + compatible = "qcom,msm-hw-fence"; + status = "ok"; + + /* SOCCP properties */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x562 0x1>; + soccp_controller = <&soccp_pas>; + + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,hw-fence-table-entries = <8192>; + qcom,hw-fence-queue-entries = <800>; + + /* time register */ + qcom,qtime-reg = <0xC221000 0x1000>; + + /* ipc version */ + qcom,hw-fence-ipc-ver = <0x20003>; + + /* base client queue properties */ + qcom,hw-fence-client-type-dpu = <4 2 128 0>; + qcom,hw-fence-client-type-ife2 = <3 1 64 1>; + + /* extra client queue properties */ + qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>; + + /* haven io-mem specific */ + hw_fence@1 { + compatible = "qcom,msm-hw-fence-mem"; + qcom,master; + shared-buffer = <&hwfence_shbuf>; + }; + }; + +Example for target without SOCCP: msm_hw_fence: qcom,hw-fence { compatible = "qcom,msm-hw-fence"; status = "ok"; @@ -54,7 +99,7 @@ Example: /* ipc version */ qcom,hw-fence-ipc-ver = <0x20003>; - /* client queues: clients_num, queues_num, queue_entries, skip_txq_wr_idx */ + /* base client queue properties */ qcom,hw-fence-client-type-dpu = <4 2 128 0>; qcom,hw-fence-client-type-ife2 = <3 1 64 1>; diff --git a/hw_fence/sun-hw-fence.dtsi b/hw_fence/sun-hw-fence.dtsi index 117980c8..38832617 100644 --- a/hw_fence/sun-hw-fence.dtsi +++ b/hw_fence/sun-hw-fence.dtsi @@ -3,11 +3,20 @@ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + &soc { msm_hw_fence: qcom,hw-fence { compatible = "qcom,msm-hw-fence"; status = "ok"; + /* SOCCP properties */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x562 0x1>; + soccp_controller = <&soccp_pas>; + qcom,hw-fence-table-entries = <8192>; qcom,hw-fence-queue-entries = <800>; qcom,ipcc-reg = <0x400000 0x140000>;