diff --git a/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts b/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts
index aaca3064..059ec876 100644
--- a/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts
+++ b/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts
@@ -16,3 +16,7 @@
 	qcom,msm-id = <686 0x10000>, <659 0x10000>;
 	qcom,board-id = <0x50001 0>;
 };
+
+&pcie1 {
+	status = "ok";
+};
diff --git a/qcom/kera-pcie.dtsi b/qcom/kera-pcie.dtsi
new file mode 100644
index 00000000..7b27993f
--- /dev/null
+++ b/qcom/kera-pcie.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-kera.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&soc {
+	pcie1: qcom,pcie@1c08000 {
+		compatible = "qcom,pci-msm";
+		device_type = "pci";
+
+		reg = <0x1c08000 0x3000>,
+			<0x1c0e000 0x2000>,
+			<0x44000000 0xf1d>,
+			<0x44000F20 0xa8>,
+			<0x44001000 0x1000>,
+			<0x44100000 0x100000>,
+			<0x1c0b000 0x1000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
+
+		cell-index = <1>;
+		linux,pci-domain = <1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x01000000 0x0 0x44200000 0x44200000 0x0 0x100000>,
+			<0x02000000 0x0 0x44300000 0x44300000 0x0 0x3d00000>;
+
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+
+		msi-map = <0x0 &gic_its 0x1400 0x1>,
+			<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
+
+		pinctrl-names = "default", "sleep";
+		perst-gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 53 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&pcie1_clkreq_default
+				&pcie1_perst_default
+				&pcie1_wake_default>;
+		pinctrl-1 = <&pcie1_clkreq_sleep
+				&pcie1_perst_default
+				&pcie1_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
+		gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
+		vreg-1p2-supply = <&L4B>;
+		vreg-0p9-supply = <&L2B>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MX_LEVEL>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 91950>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+			<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
+			<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
+			<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+			<&gcc GCC_PCIE_1_PIPE_DIV2_CLK>,
+			<&pcie_1_pipe_clk>;
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+			"pcie_aux_clk", "pcie_cfg_ahb_clk",
+			"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+			"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
+			"pcie_rate_change_clk",
+			"gcc_ddrss_pcie_sf_qtb_clk",
+			"pcie_aggre_noc_axi_clk",
+			"gcc_cnoc_pcie_sf_axi_clk",
+			"pcie_cfg_noc_pcie_anoc_ahb_clk",
+			"pcie_pipe_clk_mux", "pcie_1_pipe_div2_clk",
+			"pcie_pipe_clk_ext_src";
+		qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
+			<100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
+			<0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_1_BCR>,
+			<&gcc GCC_PCIE_1_PHY_BCR>;
+		reset-names = "pcie_1_core_reset", "pcie_1_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1400>;
+		iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+			<0x100 &apps_smmu 0x1401 0x1>;
+
+		qcom,aux-clk-freq = <20>;
+		qcom,drv-l1ss-timeout-us = <5000>;
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <150>;
+		qcom,ep-latency = <10>;
+
+		qcom,pcie-phy-ver = <112>;
+		qcom,phy-status-offset = <0x0214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x0240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x00c0 0x01 0x0
+				0x00cc 0x62 0x0
+				0x00d0 0x02 0x0
+				0x0060 0xf8 0x0
+				0x0064 0x01 0x0
+				0x0000 0x93 0x0
+				0x0004 0x01 0x0
+				0x00e0 0x90 0x0
+				0x00e4 0x82 0x0
+				0x00f4 0x07 0x0
+				0x0070 0x02 0x0
+				0x0010 0x02 0x0
+				0x0074 0x16 0x0
+				0x0014 0x16 0x0
+				0x0078 0x36 0x0
+				0x0018 0x36 0x0
+				0x0110 0x08 0x0
+				0x00bc 0x0a 0x0
+				0x0120 0x42 0x0
+				0x0080 0x04 0x0
+				0x0084 0x0d 0x0
+				0x0020 0x0a 0x0
+				0x0024 0x1a 0x0
+				0x0088 0x41 0x0
+				0x0028 0x34 0x0
+				0x0090 0xab 0x0
+				0x0094 0xaa 0x0
+				0x0098 0x01 0x0
+				0x0030 0x55 0x0
+				0x0034 0x55 0x0
+				0x0038 0x01 0x0
+				0x0140 0x14 0x0
+				0x0164 0x34 0x0
+				0x003c 0x01 0x0
+				0x001c 0x04 0x0
+				0x0174 0x16 0x0
+				0x01bc 0x0f 0x0
+				0x0170 0xa0 0x0
+				0x11a4 0x38 0x0
+				0x10dc 0x11 0x0
+				0x1160 0xbf 0x0
+				0x1164 0xbf 0x0
+				0x1168 0xb7 0x0
+				0x116c 0xea 0x0
+				0x115c 0x3f 0x0
+				0x1174 0x5c 0x0
+				0x1178 0x9c 0x0
+				0x117c 0x1a 0x0
+				0x1180 0x89 0x0
+				0x1170 0xdc 0x0
+				0x1188 0x94 0x0
+				0x118c 0x5b 0x0
+				0x1190 0x1a 0x0
+				0x1194 0x89 0x0
+				0x10cc 0x00 0x0
+				0x1008 0x09 0x0
+				0x1014 0x05 0x0
+				0x104c 0x08 0x0
+				0x1050 0x08 0x0
+				0x10d8 0x0f 0x0
+				0x1118 0x1c 0x0
+				0x10f8 0x07 0x0
+				0x11f8 0x08 0x0
+				0x1600 0x00 0x0
+				0x0e84 0x15 0x0
+				0x0e90 0x3f 0x0
+				0x0ee4 0x02 0x0
+				0x0e40 0x06 0x0
+				0x0e3c 0x18 0x0
+				0x19a4 0x38 0x0
+				0x18dc 0x11 0x0
+				0x1960 0xbf 0x0
+				0x1964 0xbf 0x0
+				0x1968 0xb7 0x0
+				0x196c 0xea 0x0
+				0x195c 0x3f 0x0
+				0x1974 0x5c 0x0
+				0x1978 0x9c 0x0
+				0x197c 0x1a 0x0
+				0x1980 0x89 0x0
+				0x1970 0xdc 0x0
+				0x1988 0x94 0x0
+				0x198c 0x5b 0x0
+				0x1990 0x1a 0x0
+				0x1994 0x89 0x0
+				0x18cc 0x00 0x0
+				0x1808 0x09 0x0
+				0x1814 0x05 0x0
+				0x184c 0x08 0x0
+				0x1850 0x08 0x0
+				0x18d8 0x0f 0x0
+				0x1918 0x1c 0x0
+				0x18f8 0x07 0x0
+				0x19f8 0x08 0x0
+				0x1684 0x15 0x0
+				0x1690 0x3f 0x0
+				0x16e4 0x02 0x0
+				0x1640 0x06 0x0
+				0x163c 0x18 0x0
+				0x02dc 0x05 0x0
+				0x0388 0x77 0x0
+				0x0398 0x0b 0x0
+				0x06a4 0x1e 0x0
+				0x06f4 0x27 0x0
+				0x03e0 0x0f 0x0
+				0x060c 0x1d 0x0
+				0x0614 0x07 0x0
+				0x0620 0xc1 0x0
+				0x0694 0x00 0x0
+				0x03d0 0x8c 0x0
+				0x0368 0x17 0x0
+				0x0370 0x2e 0x0
+				0x1424 0x00 0x0
+				0x1428 0x00 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie1_rp: pcie1_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie1_msi: qcom,pcie1_msi@17110040 {
+		compatible = "qcom,pci-msi";
+		reg = <0x17110040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 826 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 827 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+};
diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi
index fa5cab6a..ca4cb3ed 100644
--- a/qcom/kera-pinctrl.dtsi
+++ b/qcom/kera-pinctrl.dtsi
@@ -1978,4 +1978,59 @@
 			drive-strength = <2>;
 		};
 	};
+
+	pcie1 {
+		pcie1_perst_default: pcie1_perst_default {
+			mux {
+				pins = "gpio54";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio54";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie1_clkreq_default: pcie1_clkreq_default {
+			mux {
+				pins = "gpio52";
+				function = "pcie1_clk_req_n";
+			};
+
+			config {
+				pins = "gpio52";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie1_wake_default: pcie1_wake_default {
+			mux {
+				pins = "gpio53";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio53";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie1_clkreq_sleep: pcie1_clkreq_sleep {
+			mux {
+				pins = "gpio52";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio52";
+				drive-strength = <2>;
+				bias-pull-up;
+				input-enable;
+			};
+		};
+	};
 };
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index c212d315..72e7e877 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -69,7 +69,7 @@
 	};
 
 	chosen: chosen {
-		bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops page_poison=on cgroup.memory=nokmem,nosocket";
+		bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops page_poison=on cgroup.memory=nokmem,nosocket";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -510,11 +510,21 @@
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
 		interrupt-controller;
+		ranges;
 		#redistributor-regions = <1>;
 		redistributor-stride = <0x0 0x40000>;
 		reg = <0x17100000 0x10000>,	/* GICD */
 		      <0x17180000 0x200000>;	/* GICR * 8 */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gic_its: msi-controller@17140000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x17140000 0x20000>;
+		};
 	};
 
 	qcom,hdcp {
@@ -3351,6 +3361,7 @@
 #include "kera-pmic-overlay.dtsi"
 #include "kera-usb.dtsi"
 #include "kera-qupv3.dtsi"
+#include "kera-pcie.dtsi"
 #include "kera-thermal.dtsi"
 #include "kera-walt.dtsi"
 #include "msm-rdbg.dtsi"