From 3b161ff7716c070650d500203782866b3e535323 Mon Sep 17 00:00:00 2001
From: Xubin Bai <quic_xubibai@quicinc.com>
Date: Tue, 30 May 2023 00:20:18 -0700
Subject: [PATCH] dt-bindings: clock: Add Camcc bindings for Sun

Add Camcc bindings for Sun device.

Change-Id: I5832599d526b66a943d612590794feddd300f428
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
---
 bindings/clock/qcom,camcc-sun.yaml | 73 ++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 bindings/clock/qcom,camcc-sun.yaml

diff --git a/bindings/clock/qcom,camcc-sun.yaml b/bindings/clock/qcom,camcc-sun.yaml
new file mode 100644
index 00000000..31549563
--- /dev/null
+++ b/bindings/clock/qcom,camcc-sun.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,camcc-sun.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding for SUN
+
+maintainers:
+  - Xubin Bai <quic_xubibai@quicinc.com>
+
+description: |
+  Camera clock control module which supports the clocks, resets and
+  power domains on SUN.
+
+  See also:
+  - dt-bindings/clock/qcom,camcc-sun.h
+
+properties:
+  compatible:
+    const: qcom,camcc-sun
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: sleep_clk
+
+  qcom,cam_crm-crmc:
+    description: Phandle pointer to the CESTA crmc node
+
+  vdd_mm-supply:
+    description: Phandle pointer to the vdd_mm logic rail supply
+
+  vdd_mx-supply:
+    description: Phandle pointer to the vdd_mx logic rail supply
+
+  vdd_mxc-supply:
+    description: Phandle pointer to the vdd_mxc logic rail supply
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: "qcom,gcc.yaml#"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    camcc: clock-controller@ade0000 {
+      compatible = "qcom,sun-camcc", "syscon";
+      reg = <0xade0000 0x20000>;
+      reg-name = "cc_base";
+      vdd_mm-supply = <&VDD_MM_LEVEL>;
+      vdd_mx-supply = <&VDD_MX_LEVEL>;
+      vdd_mxc-supply = <&VDD_MXC_LEVEL>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&sleep_clk>;
+      clock-names = "bi_tcxo",
+                    "sleep_clk";
+      qcom,cam_crm-crmc = <&camcc_crmc>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
+...