From 4dbf74429549c78d489a5b2c106ca99af985a02a Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Fri, 31 Jan 2025 18:28:30 +0530 Subject: [PATCH 1/6] ARM: dts: msm: remove hard coded panel clk rate for kera RCM Remove hard coded panel clk rate Kera RCM platform. Change-Id: I1c3c77eed76665e87e9ec0ed0dfc2ba80e97e08e Signed-off-by: Ayushi Makhija Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 42 +++++++++++++++++++++ display/trustedvm-kera-sde-display-cdp.dtsi | 42 +++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 48dcca62..5c971225 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -16,6 +16,24 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_video { @@ -42,6 +60,20 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_120hz_video { @@ -68,6 +100,16 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_90hz_video { diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi index c42cf3a7..fc746e20 100644 --- a/display/trustedvm-kera-sde-display-cdp.dtsi +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -14,6 +14,24 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_video { @@ -36,6 +54,20 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_120hz_video { @@ -58,6 +90,16 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_90hz_video { From e8ba29204b695894d17c7711f357f1696415a899 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 20 Jan 2025 10:50:02 +0530 Subject: [PATCH 2/6] ARM: dts: msm: support 4k sharp panel on Tuna CDP Support 4k sharp panel on Tuna CDP. Change-Id: Ifdc1fa4edfe7ac752e1e4d8ab56d4735427d633b Signed-off-by: Rajeev Nandan Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 18 ++++++++++++ display/tuna-sde-display-common.dtsi | 44 ++++++++++++++++++++++++++++ display/tuna-sde-display.dtsi | 6 +++- 3 files changed, 67 insertions(+), 1 deletion(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 59f78a28..b7f06fd9 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -259,6 +259,24 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + &dsi_sharp_qhd_plus_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 4598c0e4..f47125d1 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -18,6 +18,8 @@ #include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -748,6 +750,48 @@ }; }; +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_qhd_plus_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index b905f813..402b3d07 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -214,6 +214,10 @@ }; }; +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; +}; + &dsi_sim_cmd { qcom,ulps-enabled; qcom,mdss-dsi-display-timings { From 3253c6e1eae380da6751a76381b1da61ae7c718e Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Fri, 3 Jan 2025 12:24:22 +0530 Subject: [PATCH 3/6] ARM: dts: msm: reserve memory region for splash and ramdump Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326 Signed-off-by: Sailesh Reddy Male Signed-off-by: lnxdisplay --- display/kera-sde-display.dtsi | 14 +++++++++++++- display/kera-sde.dtsi | 3 ++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 9404dfd8..ee0d4543 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -14,6 +14,18 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 0b5dc6c9..bb73d70f 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From f78eece0c398d6a207f87d838074e200a645ce7b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 20 Jan 2025 14:07:10 +0530 Subject: [PATCH 4/6] ARM: dts: msm: enable touch support for vtdr panel on tuna Enable touch support for vtdr panel on tuna CDP. Change-Id: I9bec9f15829c789a9f5230cd59811465f87e895e Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index b7f06fd9..88bd993c 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -363,4 +363,15 @@ &dsi_nt37801_amoled_cmd_ddicspr &dsi_nt37801_amoled_video_ddicspr>; }; + + goodix-berlin@5d { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video>; + }; }; From 41793be5f5e7a8501520e99fc19e7eed0f8dce13 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 28 Jan 2025 16:06:54 +0530 Subject: [PATCH 5/6] ARM: dts: msm: update in sharp qhd+ panel GPIO name in Kera Update in Sharp qhd+ panel GPIO name as per recent change from supplier and enablement of its physical panel in Kera. Change-Id: I15115714f5e719eed63e741bc7aef8b2fb608c0d Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 50 ++++++++++++++++++++++++++-- display/kera-sde-display-common.dtsi | 24 +++++++++++++ 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 5c971225..0dca9ffd 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -5,6 +5,49 @@ #include "kera-sde-display.dtsi" +&pmxr2230_gpios { + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio2"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&pm8550vs_g_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio5"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550vs_g_gpios 5 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -178,19 +221,21 @@ }; &dsi_sharp_qhd_plus_dsc_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-bklight-en-gpio = <&pmxr2230_gpios 2 0>; }; &dsi_sharp_qhd_plus_dsc_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-bklight-en-gpio = <&pmxr2230_gpios 2 0>; }; &dsi_sim_cmd { @@ -239,6 +284,7 @@ }; &sde_dsi { + avdd-supply = <&display_panel_avdd>; qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 1392a0c2..bd95e2e8 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -79,6 +79,30 @@ }; }; + dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; From 8aebb5a4919e6613ae0195c0e4383c873cfb734e Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 20 Jan 2025 12:14:52 +0530 Subject: [PATCH 6/6] ARM: dts: msm: add 60hz and 90hz support for VTDR6130 panel on tuna Add 60hz and 90hz support for VTDR6130 panel on tuna target. Change-Id: Iad6d7514f241be42bf2cd8addaefa2d3fb1e89a8 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 56 ++++++++++++++ display/tuna-sde-display-common.dtsi | 108 +++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 88bd993c..e306ac89 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -76,7 +76,9 @@ &dsi_vtdr6130_amoled_120hz_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; @@ -228,7 +230,61 @@ &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index f47125d1..093f5ca4 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -33,6 +33,10 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" @@ -305,6 +309,110 @@ }; }; +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled;