From c068ebe79a7d11d9cb48af19398deaabc74ab1db Mon Sep 17 00:00:00 2001
From: Bavyasritha Alahari <quic_alahari@quicinc.com>
Date: Mon, 17 Jul 2023 11:19:16 -0700
Subject: [PATCH] ARM: dts: msm: Add apps_rsc device tree node for sun

Add apps_rsc device tree node for sun.

Change-Id: I026e45d95b77cce6e01672756f60cdb2751d103f
Signed-off-by: Bavyasritha Alahari <quic_alahari@quicinc.com>
---
 qcom/sun.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 97acaf44..b3f975e8 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/qcom,videocc-sun.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interconnect/qcom,sun.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Sun";
@@ -381,6 +382,31 @@
 		#interconnect-cells = <1>;
 	};
 
+	apps_rsc: rsc@16500000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x16500000 0x10000>,
+		      <0x16510000 0x10000>,
+		      <0x16520000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		qcom,drv-count = <3>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+		apps_rsc_drv2: drv@2 {
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    3>,
+						  <SLEEP_TCS     2>,
+						  <WAKE_TCS      2>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 1>;
+			};
+		};
+	};
+
 	clocks {
 		xo_board: xo_board {
 			compatible = "fixed-clock";