From 39a0276bc2686f3b784b25382c94f7545f3105e1 Mon Sep 17 00:00:00 2001 From: Chintan Kothari Date: Wed, 2 Apr 2025 15:15:59 +0530 Subject: [PATCH 01/27] dt-bindings: thermal: Add legacy tsens driver compatible string Add legacy tsens driver compatible string in sm6150. Change-Id: I52bf27a0af6a1a91ded5caeeecc0dd044cf8c5bf Signed-off-by: Chintan Kothari --- bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/thermal/qcom-tsens.yaml b/bindings/thermal/qcom-tsens.yaml index 99c768ec..cc53a846 100644 --- a/bindings/thermal/qcom-tsens.yaml +++ b/bindings/thermal/qcom-tsens.yaml @@ -53,6 +53,7 @@ properties: - qcom,sc8280xp-tsens - qcom,sdm630-tsens - qcom,sdm845-tsens + - qcom,sm6150-tsens - qcom,sm6350-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens From 7c24cb15cbf51c0d6b11e45bacb8fd9c980dae27 Mon Sep 17 00:00:00 2001 From: "Bao D. Nguyen" Date: Thu, 10 Apr 2025 13:05:42 -0700 Subject: [PATCH 02/27] ARM: dts: msm: Add SD card LS external feedback clock support Add the Level Shifter's external feedback clock entry to support the SD card HS50 mode running at 50MHz. By default, the Sun platforms use the Level Shifter devices with external feedback clock signal connects back to the MSM in order for the HS50 mode to work at 50MHz. Without the external feedback clock, the HS50 mode works at reduced frequency at 37.5MHz. Change-Id: I56c61411d7f792a389fa85661fce7fa5074e2c9f Signed-off-by: Bao D. Nguyen --- qcom/sun-cdp.dtsi | 9 ++++++++- qcom/sun-mtp.dtsi | 9 ++++++++- qcom/sun-qrd.dtsi | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/qcom/sun-cdp.dtsi b/qcom/sun-cdp.dtsi index 28d1a324..e548c260 100644 --- a/qcom/sun-cdp.dtsi +++ b/qcom/sun-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -206,7 +206,14 @@ resets = <&gcc GCC_SDCC2_BCR>; reset-names = "core_reset"; + /* + * By default, the Sun reference platforms use Level Shifter + * devices with its Feedback Clock signal connects to the MSM. + * Without the external feedback clock, the HS50 mode works at + * reduced frequency at 37.5MHz. + */ qcom,uses_level_shifter; + qcom,external-fb-clk; }; &eusb2_phy0 { diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index 22d806c0..6b9b9be8 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -282,7 +282,14 @@ resets = <&gcc GCC_SDCC2_BCR>; reset-names = "core_reset"; + /* + * By default, the Sun reference platforms use Level Shifter + * devices with its Feedback Clock signal connects to the MSM. + * Without the external feedback clock, the HS50 mode works at + * reduced frequency at 37.5MHz. + */ qcom,uses_level_shifter; + qcom,external-fb-clk; }; &pmih010x_eusb2_repeater { diff --git a/qcom/sun-qrd.dtsi b/qcom/sun-qrd.dtsi index d71a76a4..bb420bf0 100644 --- a/qcom/sun-qrd.dtsi +++ b/qcom/sun-qrd.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -219,7 +219,14 @@ resets = <&gcc GCC_SDCC2_BCR>; reset-names = "core_reset"; + /* + * By default, the Sun reference platforms use Level Shifter + * devices with its Feedback Clock signal connects to the MSM. + * Without the external feedback clock, the HS50 mode works at + * reduced frequency at 37.5MHz. + */ qcom,uses_level_shifter; + qcom,external-fb-clk; }; &eusb2_phy0 { From dacefe38a60eb9c14784f119f11808f187671e33 Mon Sep 17 00:00:00 2001 From: Asit Shah Date: Thu, 3 Apr 2025 11:37:53 +0530 Subject: [PATCH 03/27] dt-bindings: arm: Add bindings for sm6150 llcc Add bindings for sm6150 llcc node. Change-Id: I4f239f190c01110e59c1081ccf0a57cb1631fb95 Signed-off-by: Asit Shah (cherry picked from commit 4173e882bd59e39d8b698fed8b92417231c98e4e) --- bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index cb841be8..b2a0a391 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -27,6 +27,7 @@ properties: - qcom,sc8180x-llcc - qcom,sc8280xp-llcc - qcom,sdm845-llcc + - qcom,sm6150-llcc - qcom,sm6350-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc From b5604a5ff71b24816dff899dcc2e6648887e3693 Mon Sep 17 00:00:00 2001 From: Kunal Singh Ranawat Date: Thu, 13 Feb 2025 18:27:16 +0530 Subject: [PATCH 04/27] ARM: dts: msm: Add tlmm pinctrl support for SM6150 Add support for TLMM pinctrl on SM6150 platform. Change-Id: I45dfd3d84900ed4b24ecda47462c2c5178bbb02f Signed-off-by: Kunal Singh Ranawat --- qcom/qcs610-opk.dtsi | 4 ++++ qcom/sm6150-pinctrl.dtsi | 6 ++++++ qcom/sm6150.dtsi | 26 ++++++++++++++++++++++++++ 3 files changed, 36 insertions(+) create mode 100644 qcom/sm6150-pinctrl.dtsi diff --git a/qcom/qcs610-opk.dtsi b/qcom/qcs610-opk.dtsi index 3fda344a..735b5765 100644 --- a/qcom/qcs610-opk.dtsi +++ b/qcom/qcs610-opk.dtsi @@ -12,3 +12,7 @@ compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; qcom,board-id = <32 0>; }; + +&tlmm { + qcom,gpios-reserved = <6 7 8 9>; +}; diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi new file mode 100644 index 00000000..f4da9acb --- /dev/null +++ b/qcom/sm6150-pinctrl.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm {}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 72b62dd6..5be3450d 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -566,6 +566,32 @@ "l3-scu-errirq", "l3-scu-faultirq"; }; + + tlmm: pinctrl@03000000 { + compatible = "qcom,sm6150-pinctrl"; + reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-reserved = <0 1 2 3 6 7 8 9>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; }; #include "sm6150-regulator.dtsi" +#include "sm6150-pinctrl.dtsi" + +&tlmm { + status = "okay"; +}; From 2072106de12854db48955c054fd95c42eb8e639c Mon Sep 17 00:00:00 2001 From: Asit Shah Date: Wed, 5 Mar 2025 20:27:45 +0530 Subject: [PATCH 05/27] ARM: dts: msm: Add smem and syscon support for SM6150 Added smem, syscon and dependent nodes for SM6150. Change-Id: Icb9485e46c8720919310bc0e2560bd51b23f5dec Signed-off-by: Asit Shah --- qcom/sm6150.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 5be3450d..a8482041 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -587,6 +587,28 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; }; #include "sm6150-regulator.dtsi" From 6833986c6f6e6f41dc4c665672fb20ae011dbe0b Mon Sep 17 00:00:00 2001 From: Saranya R Date: Mon, 7 Apr 2025 11:29:26 +0530 Subject: [PATCH 06/27] ARM: dts: msm: Add support for debug info for monaco Reserve debug info region of 4KB for monaco. Change-Id: I9481c9862838cd754a063a351dd02578d2b3dd2f Signed-off-by: Saranya R --- qcom/monaco.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 8caec9be..d94c3916 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -349,6 +349,12 @@ size = <0x0 0x1000000>; linux,cma-default; }; + + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; }; }; @@ -536,6 +542,11 @@ }; }; + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + mini_dump_mode { compatible = "qcom,minidump"; status = "ok"; From 5887bcc216757ab5ed19fef782d03b418fc6b050 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Wed, 26 Feb 2025 12:29:28 +0530 Subject: [PATCH 07/27] ARM: dts: msm: Add ldo-ocp-notifier support for kera Add ldo-ocp-notifier support for kera platforms. Change-Id: I6aac9f6faeda06152647cdb56dc2064eca4a64a6 Signed-off-by: Kavya Nunna --- qcom/kera-atp.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++ qcom/kera-mtp.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++ qcom/kera-qrd.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+) diff --git a/qcom/kera-atp.dtsi b/qcom/kera-atp.dtsi index 1c0ce4c9..b2d36494 100644 --- a/qcom/kera-atp.dtsi +++ b/qcom/kera-atp.dtsi @@ -85,3 +85,58 @@ &pm8550ve_f_die_temp { status = "disabled"; }; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c3-supply = <&L3B_LEVEL>; + periph-1c4-supply = <&L4B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1d2-supply = <&L18B>; + periph-1d3-supply = <&L19B>; + periph-1d4-supply = <&L20B>; + periph-1d5-supply = <&L21B>; + periph-1d6-supply = <&L22B>; + periph-1d7-supply = <&L23B>; + periph-19b-supply = <&S1B>; + periph-19e-supply = <&S2B>; + periph-1a1-supply = <&S3B>; + periph-1a2-supply = <&S4B>; + periph-1e4-supply = <&BOB>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D>; + periph-3c3-supply = <&L3D_LEVEL>; + periph-39b-supply = <&S1D_LEVEL>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a2-supply = <&S4D_LEVEL>; + periph-3a3-supply = <&S5D_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/kera-mtp.dtsi b/qcom/kera-mtp.dtsi index 66d3495a..e50c5703 100644 --- a/qcom/kera-mtp.dtsi +++ b/qcom/kera-mtp.dtsi @@ -93,3 +93,58 @@ &usb0 { qcom,wcd_usbss = <&wcd_usbss>; }; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c3-supply = <&L3B_LEVEL>; + periph-1c4-supply = <&L4B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1d2-supply = <&L18B>; + periph-1d3-supply = <&L19B>; + periph-1d4-supply = <&L20B>; + periph-1d5-supply = <&L21B>; + periph-1d6-supply = <&L22B>; + periph-1d7-supply = <&L23B>; + periph-19b-supply = <&S1B>; + periph-19e-supply = <&S2B>; + periph-1a1-supply = <&S3B>; + periph-1a2-supply = <&S4B>; + periph-1e4-supply = <&BOB>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D>; + periph-3c3-supply = <&L3D_LEVEL>; + periph-39b-supply = <&S1D_LEVEL>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a2-supply = <&S4D_LEVEL>; + periph-3a3-supply = <&S5D_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/kera-qrd.dtsi b/qcom/kera-qrd.dtsi index 67109ccd..ef9c0904 100644 --- a/qcom/kera-qrd.dtsi +++ b/qcom/kera-qrd.dtsi @@ -167,3 +167,58 @@ ssusb_redriver = <&redriver>; }; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c3-supply = <&L3B_LEVEL>; + periph-1c4-supply = <&L4B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1d2-supply = <&L18B>; + periph-1d3-supply = <&L19B>; + periph-1d4-supply = <&L20B>; + periph-1d5-supply = <&L21B>; + periph-1d6-supply = <&L22B>; + periph-1d7-supply = <&L23B>; + periph-19b-supply = <&S1B>; + periph-19e-supply = <&S2B>; + periph-1a1-supply = <&S3B>; + periph-1a2-supply = <&S4B>; + periph-1e4-supply = <&BOB>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D>; + periph-3c3-supply = <&L3D_LEVEL>; + periph-39b-supply = <&S1D_LEVEL>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a2-supply = <&S4D_LEVEL>; + periph-3a3-supply = <&S5D_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; From 8c6f16b12a0313c78c5dfa7c56a5d5cc3b21fde1 Mon Sep 17 00:00:00 2001 From: Aryan Modi Date: Tue, 11 Mar 2025 15:45:13 +0530 Subject: [PATCH 08/27] dt-bindings: interconnect: add interconnect bindings for SM6150 Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: Ic9a21d11bb3ce92ffb0cde91739990441673861d Signed-off-by: Veera Vegivada Signed-off-by: Aryan Modi --- bindings/interconnect/qcom,rpmh.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index bd6e5ae7..f24423e7 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -97,6 +97,15 @@ properties: - qcom,sdxbaagha-pcie_anoc, - qcom,sdxbaagha-mem_noc, - qcom,sdxbaagha-system_noc, + - qcom,sm6150-aggre1_noc + - qcom,sm6150-camnoc_virt + - qcom,sm6150-config_noc + - qcom,sm6150-dc_noc + - qcom,sm6150-gem_noc + - qcom,sm6150-ipa_virt + - qcom,sm6150-mc_virt + - qcom,sm6150-mmss_noc + - qcom,sm6150-system_noc - qcom,sm8150-aggre1-noc - qcom,sm8150-aggre2-noc - qcom,sm8150-camnoc-noc From 807f0331649520aace3005d16a8fed3486162fcc Mon Sep 17 00:00:00 2001 From: Aryan Modi Date: Wed, 16 Apr 2025 11:51:20 +0530 Subject: [PATCH 09/27] dt-bindings: clock: Add rpmh-clk bindings for sm6150 Add rpmh clock bindings for sm6150 platform. Change-Id: I8b330755340363cabe6032edc6aa225b19bc7d94 Signed-off-by: Aryan Modi --- bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index 1b915c27..252fdc2b 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -28,6 +28,7 @@ properties: - qcom,sdx75-rpmh-clk - qcom,sdxbaagha-rpmh-clk - qcom,sm4450-rpmh-clk + - qcom,sm6150-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk From 377e8acc3c8fb04f5a9ef9132fc13cc01b918034 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 15 Apr 2025 16:43:48 +0530 Subject: [PATCH 10/27] FROMLIST: dt-bindings: clock: qcom: Add QCS615 GCC clocks Add device tree bindings for global clock controller on QCS615 SoCs. Change-Id: I112235218ab3e7d9e2a44024db8afcc2a1271111 Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20241016-qcs615-clock-driver-v3-3-bb5d4135db45@quicinc.com/ Signed-off-by: Taniya Das Signed-off-by: Marco Zhang --- bindings/clock/qcom,qcs615-gcc.yaml | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 bindings/clock/qcom,qcs615-gcc.yaml diff --git a/bindings/clock/qcom,qcs615-gcc.yaml b/bindings/clock/qcom,qcs615-gcc.yaml new file mode 100644 index 00000000..243cd9bf --- /dev/null +++ b/bindings/clock/qcom,qcs615-gcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on QCS615. + + See also: include/dt-bindings/clock/qcom,qcs615-gcc.h + +properties: + compatible: + const: qcom,qcs615-gcc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,qcs615-gcc"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + From 39118055b92a677e1e82e2d98b859fb86c927d4e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 15 Apr 2025 16:46:59 +0530 Subject: [PATCH 11/27] FROMLIST: dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller Add DT bindings for the Camera clock on QCS615 platforms. Add the relevant DT include definitions as well. Change-Id: Iccb0ed8449b3efc4f378311513e757a11c72ae06 Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/linux-arm-msm/20250119-qcs615-mm-v4-clockcontroller-v4-2-5d1bdb5a140c@quicinc.com/ Patch-mainline: linux-arm-kernel @ 19/01/25, 15:52 Signed-off-by: Taniya Das Signed-off-by: Dongfang Zhao --- bindings/clock/qcom,qcs615-camcc.yaml | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 bindings/clock/qcom,qcs615-camcc.yaml diff --git a/bindings/clock/qcom,qcs615-camcc.yaml b/bindings/clock/qcom,qcs615-camcc.yaml new file mode 100644 index 00000000..82c4dee5 --- /dev/null +++ b/bindings/clock/qcom,qcs615-camcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on QCS615 + + See also: include/dt-bindings/clock/qcom,qcs615-camcc.h + +properties: + compatible: + const: qcom,qcs615-camcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0xad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + From bb399e6f1151b8e0327feb33767fcbcba4f9c4f4 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 15 Apr 2025 16:53:39 +0530 Subject: [PATCH 12/27] FROMLIST: dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Change-Id: Ia0231c87be0d5217100013c4ab7c3b0a83c3e134 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/linux-arm-msm/20250119-qcs615-mm-v4-clockcontroller-v4-6-5d1bdb5a140c@quicinc.com/ Patch-mainline: linux-arm-kernel @ 19/01/25, 15:52 Signed-off-by: Taniya Das Signed-off-by: Dongfang Zhao --- bindings/clock/qcom,qcs615-gpucc.yaml | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 bindings/clock/qcom,qcs615-gpucc.yaml diff --git a/bindings/clock/qcom,qcs615-gpucc.yaml b/bindings/clock/qcom,qcs615-gpucc.yaml new file mode 100644 index 00000000..1288ff92 --- /dev/null +++ b/bindings/clock/qcom,qcs615-gpucc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h + +properties: + compatible: + const: qcom,qcs615-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 GPUCC div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0x5090000 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + From e9b2fd1e948ed4d42dce98a9e886cddd51465411 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 15 Apr 2025 16:57:37 +0530 Subject: [PATCH 13/27] FROMLIST: dt-bindings: clock: Add Qualcomm QCS615 Video clock controller Add DT bindings for the Video clock on QCS615 platforms. Add the relevant DT include definitions as well. Change-Id: I0279899c5b53b9dbcba9152ac49d70e87011cec9 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/linux-arm-msm/20250119-qcs615-mm-v4-clockcontroller-v4-8-5d1bdb5a140c@quicinc.com/ Patch-mainline: linux-arm-kernel @ 19/01/25, 15:52 Signed-off-by: Taniya Das Signed-off-by: Dongfang Zhao --- bindings/clock/qcom,qcs615-videocc.yaml | 64 +++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 bindings/clock/qcom,qcs615-videocc.yaml diff --git a/bindings/clock/qcom,qcs615-videocc.yaml b/bindings/clock/qcom,qcs615-videocc.yaml new file mode 100644 index 00000000..396cbbcd --- /dev/null +++ b/bindings/clock/qcom,qcs615-videocc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-videocc.h + +properties: + compatible: + const: qcom,qcs615-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0xab00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + From 20b4753cd4fc99536499aa6d605f9f55dca9fe2a Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Fri, 18 Apr 2025 16:27:55 +0530 Subject: [PATCH 14/27] dt-bindings: soc: qcom: Add documentation for ufs-phy-qmp-v3-660 Add documentation for ufs-phy-qmp-v3-660 phy driver used for sm6150 platform. Change-Id: I24ac03261f3c7eb59f928bddf330bcc08c23a4dd Signed-off-by: Monish Chunara --- bindings/ufs/qcom,ufs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/ufs/qcom,ufs.yaml b/bindings/ufs/qcom,ufs.yaml index 83a3a2dc..92631021 100644 --- a/bindings/ufs/qcom,ufs.yaml +++ b/bindings/ufs/qcom,ufs.yaml @@ -38,6 +38,7 @@ properties: - qcom,ufs-phy-qmp-v4-waipio - qcom,ufs-phy-qmp-v4-sun - qcom,ufs-phy-qmp-v4-niobe + - qcom,ufs-phy-qmp-v3-660 - const: qcom,ufshc - const: jedec,ufs-2.0 From 71e75ace0d39aa6b344a39684e78321c032b9ff2 Mon Sep 17 00:00:00 2001 From: Rajkumar Patel Date: Fri, 28 Mar 2025 10:45:10 +0530 Subject: [PATCH 15/27] dt-bindings: Add power-state dt-bindings Add bindings of power-state device in yaml format. Change-Id: I7abd870f0a0f46b5bf293f15d4215fff3e85e70f Signed-off-by: Rajkumar Patel --- bindings/soc/qcom/qcom,power-state.yaml | 41 +++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 bindings/soc/qcom/qcom,power-state.yaml diff --git a/bindings/soc/qcom/qcom,power-state.yaml b/bindings/soc/qcom/qcom,power-state.yaml new file mode 100644 index 00000000..8a786b8a --- /dev/null +++ b/bindings/soc/qcom/qcom,power-state.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,power-state.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Power State Management Device + +maintainers: + - Maulik Shah + +description: | + This binding describes the Qualcomm Technologies, Inc. Power State Management device. + This device helps with various Qualcomm SoC level Power state like deep sleep and + hibernation and user space management for subsystem and SoC low power states. + +properties: + compatible: + const: qcom,power-state + + qcom,subsys-name: + description: subsystem names supported + + qcom,rproc-handle: + description: phandle to subsys defined in subsys-name. + +required: + - compatible + - qcom,subsys-name + - qcom,rproc-handle + +additionalProperties: false + +examples: + - | + qcom,power-state { + compatible = "qcom,power-state"; + qcom,subsys-name = "adsp", "modem"; + qcom,rproc-handle = <&adsp_pas>, <&modem_pas>; + }; +... From 4b66fec2e78eff0dc657896066852a48ae8e15b9 Mon Sep 17 00:00:00 2001 From: Dhaval Radiya Date: Mon, 7 Apr 2025 17:34:54 +0530 Subject: [PATCH 16/27] ARM: dts: msm: Update regulator voltages of qcs610 variants Update the regulator voltages for iot and opk variants of qcs610. Change-Id: I40ceeb873e8be62c5213b978793c33d7d539c747 Signed-off-by: Dhaval Radiya --- qcom/qcs610-iot.dtsi | 32 ++++++++++++++++++++++++++++++++ qcom/qcs610-opk.dtsi | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/qcom/qcs610-iot.dtsi b/qcom/qcs610-iot.dtsi index 26b86790..495af8ae 100644 --- a/qcom/qcs610-iot.dtsi +++ b/qcom/qcs610-iot.dtsi @@ -8,3 +8,35 @@ compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; qcom,board-id = <32 0>; }; + +&L16A { + regulator-max-microvolt = <3304000>; +}; + +&L19A { + regulator-max-microvolt = <3304000>; +}; + +&L4C { + regulator-max-microvolt = <2912000>; +}; + +&L5C { + regulator-max-microvolt = <2912000>; +}; + +&L13A { + regulator-always-on; +}; + +&L7C { + regulator-always-on; +}; + +&L10A { + regulator-always-on; +}; + +&L14A { + regulator-always-on; +}; diff --git a/qcom/qcs610-opk.dtsi b/qcom/qcs610-opk.dtsi index 735b5765..925ef5e3 100644 --- a/qcom/qcs610-opk.dtsi +++ b/qcom/qcs610-opk.dtsi @@ -16,3 +16,35 @@ &tlmm { qcom,gpios-reserved = <6 7 8 9>; }; + +&L16A { + regulator-max-microvolt = <3304000>; +}; + +&L19A { + regulator-max-microvolt = <3304000>; +}; + +&L4C { + regulator-max-microvolt = <2912000>; +}; + +&L5C { + regulator-max-microvolt = <2912000>; +}; + +&L13A { + regulator-always-on; +}; + +&L7C { + regulator-always-on; +}; + +&L10A { + regulator-always-on; +}; + +&L14A { + regulator-always-on; +}; From ef3e0beac6a02c2af42399b28ee95fcc2cba4ac5 Mon Sep 17 00:00:00 2001 From: Dhaval Radiya Date: Thu, 6 Mar 2025 10:06:04 +0530 Subject: [PATCH 17/27] ARM: dts: msm: Add smp2p, qmp_aop and aoss_qmp support for SM6150 Add smp2p, qmp_aop and aoss_qmp device tree node to support SM6150 platform. Change-Id: Iff80c2e40ebecd26f2c649007e79506984bfc35b Signed-off-by: Dhaval Radiya --- qcom/sm6150.dtsi | 145 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a8482041..a2c9e93d 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -588,6 +588,29 @@ wakeup-parent = <&pdc>; }; + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm8150-apss-shared"; + reg = <0x17c00000 0x1000>; + #mbox-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + qmp_aop: qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + apcs: syscon@17c0000c { compatible = "syscon"; reg = <0x17c0000c 0x4>; @@ -609,10 +632,132 @@ memory-region = <&smem_region>; hwlocks = <&tcsr_mutex 3>; }; + + glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom_smp2p_adsp: smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "sm6150-regulator.dtsi" #include "sm6150-pinctrl.dtsi" +#include "msm-rdbg.dtsi" &tlmm { status = "okay"; From 0e84ac98c6a8690dc950a1a1bc369d5dc1844684 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Mon, 21 Apr 2025 11:27:27 +0530 Subject: [PATCH 18/27] ARM: dts: msm: Update iomemory-ranges for parrot-vm Split iomemory-ranges for parrot-vm to be inline with AC aperture settings. Change-Id: I6dbf890bd607d916d2429577af6ad164e3cd51db Signed-off-by: Swetha Chikkaboraiah --- qcom/parrot-vm.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index 953d401c..b2faaafb 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "waipio-vm.dtsi" @@ -15,7 +15,8 @@ iomemory-ranges = <0x0 0x0a28000 0x0 0x0a28000 0x0 0x4000 0x0 0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1 0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1 - 0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1 + 0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1 + 0x0 0xc450000 0x0 0xc450000 0x0 0x70000 0x1 0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; From 357667d318c3169abe9674c09e6ff4f294e94d6b Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 4 Feb 2025 18:00:39 +0530 Subject: [PATCH 19/27] ARM: dts: msm: gunyah: Add test nodes for parrot vm Add test-dbl-tuivm, test-msgq-tuivm and tlmm-vm-test nodes for parrot and parrot vm. Change-Id: I15e3312cf74f9ddae27b93a941e7d6c7df844c9b Signed-off-by: Saranya R --- qcom/parrot-pinctrl.dtsi | 9 ++++++++- qcom/parrot-vm.dtsi | 35 ++++++++++++++++++++++++++++++++++- qcom/parrot.dtsi | 9 +++++++++ qcom/waipio-vm.dtsi | 35 +++++++++++++++++++++++++++++------ 4 files changed, 80 insertions(+), 8 deletions(-) diff --git a/qcom/parrot-pinctrl.dtsi b/qcom/parrot-pinctrl.dtsi index 7d9220df..8bd3f19c 100644 --- a/qcom/parrot-pinctrl.dtsi +++ b/qcom/parrot-pinctrl.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &soc { @@ -1897,4 +1897,11 @@ &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; }; }; + + tlmm-vm-test { + compatible = "qcom,tlmm-vm-test"; + qcom,master; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; + }; }; diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index 953d401c..9a84e930 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "waipio-vm.dtsi" @@ -56,6 +56,39 @@ tlmm: pinctrl@f000000 { compatible = "qcom,parrot-vm-tlmm"; gpios = /bits/ 16 <98 99 10 11 12 13 64 65>; + + qupv3_se11_i2c_active: qupv3_se11_i2c_sda_active { + mux { + pins = "gpio10"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + }; + }; + }; + + tlmm-vm-test { + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; }; tlmm-vm-mem-access { diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index b01a2cc7..557a2e9a 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2618,7 +2618,16 @@ qcom,pipe-attr-ee; }; + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + qcom,primary; + }; thermal_zones: thermal-zones { }; diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index 36ec422f..cf746ca9 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -215,16 +215,25 @@ }; }; - test-dbl { + test-dbl-tuivm { vdevice-type = "doorbell"; - generate = "/hypervisor/test-dbl"; + generate = "/hypervisor/test-dbl-tuivm"; qcom,label = <0x4>; peer-default; }; - test-dbl-source { + test-dbl-tuivm-source { vdevice-type = "doorbell-source"; - generate = "/hypervisor/test-dbl-source"; + generate = "/hypervisor/test-dbl-tuivm-source"; + qcom,label = <0x4>; + peer-default; + }; + + test-msgq-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; qcom,label = <0x4>; peer-default; }; @@ -280,6 +289,13 @@ gpios = /bits/ 16 <64 65 66 67 0 4 86 87 16 17 18 19 20 21>; }; + tlmm-vm-test { + compatible = "qcom,tlmm-vm-test"; + tlmm-vm-gpio-list = <&tlmm 64 0 &tlmm 65 0 &tlmm 66 0 &tlmm 67 0 &tlmm 0 0 + &tlmm 4 0 &tlmm 86 0 &tlmm 87 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 20 0 &tlmm 21 0>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -396,10 +412,17 @@ qcom,support-hypervisor; }; - qcom,test-dbl { + qcom,test-dbl-tuivm { compatible = "qcom,gh-dbl"; qcom,label = <0x4>; }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + affinity = <0>; + }; + }; #include "waipio-vm-dma-heaps.dtsi" From cb98bc6b81aad0009ded5be44ede8ff9964bf445 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 15 Apr 2025 16:50:54 +0530 Subject: [PATCH 20/27] FROMLIST: dt-bindings: clock: Add Qualcomm QCS615 Display clock controller Add DT bindings for the Display clock on QCS615 platforms. Add the relevant DT include definitions as well. Change-Id: If1b30f1badf667bca1728502c01c1de1e5787ce2 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/linux-arm-msm/20250119-qcs615-mm-v4-clockcontroller-v4-4-5d1bdb5a140c@quicinc.com/ Patch-mainline: linux-arm-kernel @ 19/01/25, 15:52 Signed-off-by: Taniya Das Signed-off-by: Dongfang Zhao --- bindings/clock/qcom,qcs615-dispcc.yaml | 73 ++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 bindings/clock/qcom,qcs615-dispcc.yaml diff --git a/bindings/clock/qcom,qcs615-dispcc.yaml b/bindings/clock/qcom,qcs615-dispcc.yaml new file mode 100644 index 00000000..d9622446 --- /dev/null +++ b/bindings/clock/qcom,qcs615-dispcc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on QCS615 + +maintainers: + - Ajit Pandey + - Taniya Das + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on QCS615 + + See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h + +properties: + compatible: + const: qcom,qcs615-dispcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 clock source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Display port PLL link clock + - description: Display port PLL VCO DIV clock + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dp_phy 0>, + <&mdss_dp_vco 0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + From 82fbb9e687d363a89bb57f43ae02fd81be5ea131 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Tue, 21 Jan 2025 22:41:35 +0530 Subject: [PATCH 21/27] ARM: dts: msm: Add pvm_fw_mem region for parrot Add pvm_fw_mem region for parrot SoC. Change-Id: Ibcde4e8c871c9f178d38e87354c7bf75bda01933 Signed-off-by: Swetha Chikkaboraiah --- qcom/parrot-reserved-memory.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/qcom/parrot-reserved-memory.dtsi b/qcom/parrot-reserved-memory.dtsi index 33496207..b2fd59ae 100644 --- a/qcom/parrot-reserved-memory.dtsi +++ b/qcom/parrot-reserved-memory.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &reserved_memory { @@ -69,6 +69,11 @@ reg = <0x0 0x80c00000 0x0 0x1000>; }; + pvm_fw_mem: pvm_fw_region@80c01000 { + no-map; + reg = <0x0 0x80c01000 0x0 0x100000>; + }; + wlan_fw_mem: wlan_fw_region@82a00000 { no-map; reg = <0x0 0x82a00000 0x0 0xc00000>; From 98d685afc7c3003d211206700c1da107b05f972d Mon Sep 17 00:00:00 2001 From: Aryan Modi Date: Wed, 23 Apr 2025 17:14:46 +0530 Subject: [PATCH 22/27] dt-bindings: Add entry for dt-bindings of qpnp-pdphy Add documentation of qpnp-pdphy in yaml format. Change-Id: I1e21a59fad61c856132628dd80dbbb96971b025f Signed-off-by: Aryan Modi --- bindings/usb/qcom,qpnp-pdphy.yaml | 108 ++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 bindings/usb/qcom,qpnp-pdphy.yaml diff --git a/bindings/usb/qcom,qpnp-pdphy.yaml b/bindings/usb/qcom,qpnp-pdphy.yaml new file mode 100644 index 00000000..c76542a3 --- /dev/null +++ b/bindings/usb/qcom,qpnp-pdphy.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,qpnp-pdphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: USB Power Delivery Physical layer + +maintainers: + - Wesley Cheng + +properties: + compatible: + items: + - enum: + - qcom,qpnp-pdphy + + reg: + description: Register Base address of the qpnp pd phy + maxItems: 1 + + vdd-pdphy-supply: + description: phandle to the VDD supply regulator node + + interrupts: + minItems: 1 + maxItems: 7 + + interrupt-names: + minItems: 1 + items: + - const: sig-tx + - const: sig-rx + - const: msg-tx + - const: msg-rx + - const: msg-tx-failed + - const: msg-tx-discarded + - const: msg-rx-discarded + + vbus-supply: + description: Regulator that enables VBUS source output + + vconn-supply: + description: Regulator that enables VCONN source output. This will be supplied + on the USB CC line that is not used for communication when Ra resistance is detected. + + qcom,default-sink-caps: + description: List of 32-bit values representing the nominal sink capabilities in voltage + (millivolts) and current (milliamps) pairs. + items: + items: + - + description: volts + minimum: 0 + maximum: 100000 + + - + description: amps + minimum: 0 + maximum: 100000 + + qcom,no-usb3-dp-concurrency: + description: If present, usb3 and dp concurrency is not supported. + type: boolean + + qcom,pd-20-source-only: + description: If present, only PD2.0 is supported as source. + type: boolean + + qcom,pps-disabled: + description: If defined pps support will be disabled. + Standard PD communication will remain unaffected. + type: boolean + +additionalProperties: false + +examples: + - | + qcom,qpnp-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm8998_l24>; + interrupts = <0x2 0x17 0x1>, + <0x2 0x17 0x2>, + <0x2 0x17 0x3>, + <0x2 0x17 0x4>, + <0x2 0x17 0x5>, + <0x2 0x17 0x6>, + <0x2 0x17 0x7>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded"; + + vbus-supply = <&pm8998_l2>; + vconn-supply = <&pm8998_l3>; + qcom,no-usb3-dp-concurrency; + qcom,pd-20-source-only; + qcom,pps-disabled; + qcom,default-sink-caps = <5000 8000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 9000>; /* 12V @ 9A */ + }; +... From e0116ea45756cfa4d01a377ed5558781c417a09e Mon Sep 17 00:00:00 2001 From: Aryan Modi Date: Thu, 6 Mar 2025 14:19:36 +0530 Subject: [PATCH 23/27] dt-bindings: clock: Add clock controllers compatible for SM6150 Document compatible for GCC/GPUCC/DISPCC/DEBUGCC/VIDEOCC/CAMCC on SM6150 Platform. Change-Id: Id463d7ee9333e65f97a455d511411ac0feb378dd Signed-off-by: Aryan Modi --- bindings/clock/qcom,debugcc.yaml | 1 + bindings/clock/qcom,qcs615-camcc.yaml | 9 +++++++-- bindings/clock/qcom,qcs615-dispcc.yaml | 9 +++++++-- bindings/clock/qcom,qcs615-gcc.yaml | 9 +++++++-- bindings/clock/qcom,qcs615-gpucc.yaml | 9 +++++++-- bindings/clock/qcom,qcs615-videocc.yaml | 9 +++++++-- 6 files changed, 36 insertions(+), 10 deletions(-) diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 1c8b8d47..141e2d72 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,sdx75-debugcc - qcom,sdxbaagha-debugcc - qcom,sm4450-debugcc + - qcom,sm6150-debugcc - qcom,monaco-debugcc - qcom,tuna-debugcc - qcom,kera-debugcc diff --git a/bindings/clock/qcom,qcs615-camcc.yaml b/bindings/clock/qcom,qcs615-camcc.yaml index 82c4dee5..1f0e5387 100644 --- a/bindings/clock/qcom,qcs615-camcc.yaml +++ b/bindings/clock/qcom,qcs615-camcc.yaml @@ -13,11 +13,16 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on QCS615 - See also: include/dt-bindings/clock/qcom,qcs615-camcc.h + See also: + include/dt-bindings/clock/qcom,camcc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-camcc.h properties: compatible: - const: qcom,qcs615-camcc + enum: + - qcom,qcs615-camcc + - qcom,sa6155-camcc + - qcom,sm6150-camcc reg: maxItems: 1 diff --git a/bindings/clock/qcom,qcs615-dispcc.yaml b/bindings/clock/qcom,qcs615-dispcc.yaml index d9622446..ec67c9b8 100644 --- a/bindings/clock/qcom,qcs615-dispcc.yaml +++ b/bindings/clock/qcom,qcs615-dispcc.yaml @@ -14,11 +14,16 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on QCS615 - See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h + See also: + include/dt-bindings/clock/qcom,dispcc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-dispcc.h properties: compatible: - const: qcom,qcs615-dispcc + enum: + - qcom,qcs615-dispcc + - qcom,sa6155-dispcc + - qcom,sm6150-dispcc reg: maxItems: 1 diff --git a/bindings/clock/qcom,qcs615-gcc.yaml b/bindings/clock/qcom,qcs615-gcc.yaml index 243cd9bf..96495a3c 100644 --- a/bindings/clock/qcom,qcs615-gcc.yaml +++ b/bindings/clock/qcom,qcs615-gcc.yaml @@ -13,11 +13,16 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on QCS615. - See also: include/dt-bindings/clock/qcom,qcs615-gcc.h + See also: + include/dt-bindings/clock/qcom,gcc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-gcc.h properties: compatible: - const: qcom,qcs615-gcc + enum: + - qcom,qcs615-gcc + - qcom,sa6155-gcc + - qcom,sm6150-gcc clocks: items: diff --git a/bindings/clock/qcom,qcs615-gpucc.yaml b/bindings/clock/qcom,qcs615-gpucc.yaml index 1288ff92..023fbe16 100644 --- a/bindings/clock/qcom,qcs615-gpucc.yaml +++ b/bindings/clock/qcom,qcs615-gpucc.yaml @@ -13,11 +13,16 @@ description: | Qualcomm graphics clock control module provides clocks, resets and power domains on QCS615 Qualcomm SoCs. - See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h + See also: + include/dt-bindings/clock/qcom,gpucc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-gpucc.h properties: compatible: - const: qcom,qcs615-gpucc + enum: + - qcom,qcs615-gpucc + - qcom,sa6155-gpucc + - qcom,sm6150-gpucc reg: maxItems: 1 diff --git a/bindings/clock/qcom,qcs615-videocc.yaml b/bindings/clock/qcom,qcs615-videocc.yaml index 396cbbcd..5e3f71d9 100644 --- a/bindings/clock/qcom,qcs615-videocc.yaml +++ b/bindings/clock/qcom,qcs615-videocc.yaml @@ -13,11 +13,16 @@ description: | Qualcomm video clock control module provides clocks, resets and power domains on QCS615 Qualcomm SoCs. - See also: include/dt-bindings/clock/qcom,qcs615-videocc.h + See also: + include/dt-bindings/clock/qcom,qcs615-videocc.h + include/dt-bindings/clock/qcom,videocc-sm6150.h properties: compatible: - const: qcom,qcs615-videocc + enum: + - qcom,qcs615-videocc + - qcom,sa6155-videocc + - qcom,sm6150-videocc reg: maxItems: 1 From 63ca55d6666c2f86f2d4a2dd94f382bfb3fc2cd0 Mon Sep 17 00:00:00 2001 From: Chintan Kothari Date: Thu, 6 Mar 2025 13:57:37 +0530 Subject: [PATCH 24/27] ARM: dts: msm: Add support for clock nodes and gdsc's for SM6150 Add support for cpufreq_hw, clock controller nodes and their corresponding gdsc's for SM6150. Change-Id: I7d64cbe80eb7f10277acce0a0c91fb788c3c99dc Signed-off-by: Chintan Kothari --- qcom/sm6150-gdsc.dtsi | 195 +++++++++++++++++++++++++++++++++++ qcom/sm6150.dtsi | 235 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 430 insertions(+) create mode 100644 qcom/sm6150-gdsc.dtsi diff --git a/qcom/sm6150-gdsc.dtsi b/qcom/sm6150-gdsc.dtsi new file mode 100644 index 00000000..4ab74042 --- /dev/null +++ b/qcom/sm6150-gdsc.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + reg = <0x106004 0x4>; + regulator-name = "emac_gdsc"; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + regulator-name = "pcie_0_gdsc"; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + regulator-name = "ufs_phy_gdsc"; + status = "disabled"; + }; + + usb20_sec_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + reg = <0x1a6004 0x4>; + regulator-name = "usb20_sec_gdsc"; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + reg = <0x10f004 0x4>; + regulator-name = "usb30_prim_gdsc"; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + reg = <0x17d040 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + reg = <0x17d044 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + reg = <0x17d048 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + reg = <0x17d04c 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + reg = <0x17d050 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + reg = <0x17d054 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + reg = <0x17d058 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + titan_top_gdsc: qcom,gdsc@ad0b134 { + compatible = "qcom,gdsc"; + reg = <0xad0b134 0x4>; + regulator-name = "titan_top_gdsc"; + status = "disabled"; + }; + + bps_gdsc: qcom,gdsc@ad06004 { + compatible = "qcom,gdsc"; + reg = <0xad06004 0x4>; + regulator-name = "bps_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + reg = <0xad09004 0x4>; + regulator-name = "ife_0_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + reg = <0xad0a004 0x4>; + regulator-name = "ife_1_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + reg = <0xad07004 0x4>; + regulator-name = "ipe_0_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + reg = <0xaf03000 0x4>; + regulator-name = "mdss_core_gdsc"; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "qcom,gdsc"; + reg = <0x509106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "qcom,gdsc"; + reg = <0x509100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + reg = <0xab00874 0x4>; + regulator-name = "vcodec0_gdsc"; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + reg = <0xab00814 0x4>; + regulator-name = "venus_gdsc"; + status = "disabled"; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index a2c9e93d..4dd1255f 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -4,8 +4,14 @@ */ #include +#include +#include +#include +#include +#include #include #include +#include / { model = "Qualcomm Technologies, Inc. SM6150"; @@ -43,6 +49,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -66,6 +73,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -84,6 +92,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -101,6 +110,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -118,6 +128,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -135,6 +146,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -152,6 +164,7 @@ dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1 2>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; @@ -170,6 +183,7 @@ dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1 2>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -427,6 +441,12 @@ , ; }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,sm6150-rpmh-clk"; + #clock-cells = <1>; + status = "okay"; + }; }; }; @@ -540,6 +560,126 @@ }; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,sm6150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + protected-clocks = , + , + , + , + , + , + ; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm6150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sm6150-gpucc", "syscon"; + reg = <0x5090000 0x9000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm6150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm6150-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc>; + qcom,videocc = <&videocc>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <2>; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; @@ -756,9 +896,104 @@ }; #include "sm6150-regulator.dtsi" +#include "sm6150-gdsc.dtsi" #include "sm6150-pinctrl.dtsi" #include "msm-rdbg.dtsi" &tlmm { status = "okay"; }; + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb20_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&titan_top_gdsc { + parent-supply = <&VDD_MX_LEVEL>; + status = "ok"; +}; + +&bps_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + status = "ok"; +}; + +&ife_1_gdsc { + status = "ok"; +}; + +&ipe_0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +}; From ef15bb1154c109e28202ebb613542ba3ab1e8d4f Mon Sep 17 00:00:00 2001 From: Aryan Modi Date: Wed, 23 Apr 2025 21:35:20 +0530 Subject: [PATCH 25/27] dt-bindings: qpnp-qg: Add DT binding for qpnp-qg device Add DT binding documentation for qpnp-qg Qguage device. Change-Id: I5b68e4b12f86bc2953d1369ff51d28aed26752b9 Signed-off-by: Aryan Modi --- bindings/power/supply/qcom/qpnp-qg.yaml | 187 ++++++++++++++++++++++++ 1 file changed, 187 insertions(+) create mode 100644 bindings/power/supply/qcom/qpnp-qg.yaml diff --git a/bindings/power/supply/qcom/qpnp-qg.yaml b/bindings/power/supply/qcom/qpnp-qg.yaml new file mode 100644 index 00000000..c2c8590f --- /dev/null +++ b/bindings/power/supply/qcom/qpnp-qg.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/qpnp-qg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QPNP PMIC QGAUGE (QG) Device + +maintainers: + - Rakesh Kota + - Jishnu Prakash + - Kamal Wadhwa + +description: | + QPNP PMIC QGAUGE device provides the ability to gauge the State-of-Charge + of the battery. It provides an interface to the clients to read various + battery related parameters. + + Required Node Structure: | + Qgauge device must be described in two level of nodes. The first level + describes the properties of the Qgauge device and the second level + describes the peripherals managed/used of the module. + +properties: + compatible: + enum: + - qcom,pm6150-qg + - qcom,qpnp-qg-lite + - qcom,pmi632-qg + - qcom,pm7250b-qg + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + + qcom,vbatt-cutoff-mv: + description: | + The battery voltage threshold (in mV) at which the + the Qgauge algorithm converges to 0 SOC. If not specified + the default value is 3400 mV. + + qcom,vbatt-low-mv: + description: | + The battery voltage threshold (in mV) at which the + the VBAT_LOW interrupt fires. Software can take necessary + the action when this interrupt fires. If not specified + the default value is 3500 mV. + + qcom,vbatt-low-cold-mv: + description: | + The battery voltage threshold (in mV) at which the + the VBAT_LOW interrupt fires. The threshold is only + applied at cold temperature specified by + 'qcom,cold-temp-threshold'. Software can take necessary + the action when this interrupt fires. If not specified + the default value is 3800 mV. + + qcom,vbatt-empty-mv: + description: | + The battery voltage threshold (in mV) at which the + vbatt-empty interrupt fires. The SOC is forced to 0 + when this interrupt fires. If not specified, the + default value is 3200 mV. + + qcom,vbatt-empty-cold-mv: + description: | + The battery voltage threshold (in mV) at which the + vbatt-empty interrupt fires. This threshold is only + applied at cold temperature specified by + 'qcom,cold-temp-threshold'. The SOC is forced to 0 + when this interrupt fires. If not specified, the + default value is 3000 mV. + + qcom,s3-entry-fifo-length: + description: | + The minimum number if FIFO samples which have to qualify the + S3 IBAT entry threshold (qcom,s3-entry-ibat-ua) for QG + to enter into S3 state. + Minimum Value = 1 Maximum Value = 8. The hardware default + is configured to 3. + + io-channels: + description: | + IIO channel specifiers for each name in io-channel-names. + + io-channel-names: + description: | + Names of the IIO channels that are used by QG device. + +additionalProperties: false + +required: + - compatible + - io-channels + - io-channel-names + +patternProperties: + "^qcom,qgauge@[0-9a-f].*$": + type: object + + properties: + reg: + description: Addresses and sizes for the specified peripheral. + + interrupts: + description: Interrupt mapping as per the interrupt encoding. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + additionalProperties: false + + "^qcom,qg-sdam@[0-9a-f].*$": + type: object + + properties: + reg: + description: Addresses and sizes for the specified peripheral. + + required: + - reg + + additionalProperties: false + +examples: + - | + qpnp,qg { + compatible = "qcom,pm6150-qg"; + depends-on-supply = <&pm6150_vadc>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + qcom,vbatt-cutoff-mv = <3200>; + qcom,vbatt-low-mv = <3300>; + qcom,vbatt-low-cold-mv = <3700>; + qcom,vbatt-empty-mv = <3000>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + io-channels = <&pm6150_vadc ADC5_BAT_THERM_100K_PU>, + <&pm6150_vadc ADC5_BAT_ID_100K_PU>, + <&pm6150_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm6150_charger PSY_IIO_RECHARGE_SOC>, + <&pm6150_charger PSY_IIO_FORCE_RECHARGE>, + <&pm6150_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800>; + interrupts = + <0x0 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600>; + }; + }; +... From ed8af40778aa043a77b6f4104bd12c5172a8238b Mon Sep 17 00:00:00 2001 From: Aryan Modi Date: Thu, 24 Apr 2025 17:51:55 +0530 Subject: [PATCH 26/27] dt-bindings: smb1398: dt binding for smb1398-charger device Add DT binding documentation for smb1398-charger device in yaml format. Change-Id: I100c271fbb0965894a3dfb9b2072b60ecfc8f4ad Signed-off-by: Aryan Modi --- .../supply/qcom/smb1390-charger-psy.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 bindings/power/supply/qcom/smb1390-charger-psy.yaml diff --git a/bindings/power/supply/qcom/smb1390-charger-psy.yaml b/bindings/power/supply/qcom/smb1390-charger-psy.yaml new file mode 100644 index 00000000..5e85fcef --- /dev/null +++ b/bindings/power/supply/qcom/smb1390-charger-psy.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/smb1390-charger-psy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SMB1390 Charger + +maintainers: + - Rakesh Kota + - Jishnu Prakash + - Kamal Wadhwa + +description: | + SMB1390 charge pump is paired with QTI family of standalone chargers to + enable a high current, high efficiency Li+ battery charging system. + + Required Node Structure: | + SMB1390 Charger must be described in two levels of device nodes. + +properties: + compatible: + enum: + - qcom,smb1390-charger-psy + - qcom,smb1390-slave + + "#io-channel-cells": + const: 1 + +additionalProperties: false + +required: + - compatible + - "#io-channel-cells" + +patternProperties: + '^qcom,core[0-9a-f].*$': + type: object + + properties: + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - interrupts + - interrupt-names + + additionalProperties: false + +examples: + - | + smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger-psy"; + #io-channel-cells = <1>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "tsd-fault", + "irev-fault", + "vph-ov-hard", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; + }; +... From 8d297483dcadc21a5b609dc9ffaca4f06e9a12e0 Mon Sep 17 00:00:00 2001 From: Chintan Kothari Date: Thu, 6 Mar 2025 14:14:17 +0530 Subject: [PATCH 27/27] ARM: dts: msm: Add interconnect devices for SM6150 Add interconnect devices for camnoc_virt, ipa_virt, mc_virt, dc_noc, gem_noc, config_noc, system_noc, aggre1_noc and mmss_noc. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I8c2eb0b8a63252cbfcfe44355ad9b4421c8aee5c Signed-off-by: Chintan Kothari --- qcom/sm6150.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 4dd1255f..a86e95db 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -442,6 +444,10 @@ ; }; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + rpmhcc: qcom,rpmhclk { compatible = "qcom,sm6150-rpmh-clk"; #clock-cells = <1>; @@ -468,6 +474,11 @@ , ; }; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; }; }; @@ -576,6 +587,78 @@ }; }; + camnoc_virt: interconnect@0 { + compatible = "qcom,sm6150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1 { + compatible = "qcom,sm6150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,sm6150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm6150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3e200>; + compatible = "qcom,sm6150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x5080>; + compatible = "qcom,sm6150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x1f300>; + compatible = "qcom,sm6150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg = <0x1700000 0x3f200>; + compatible = "qcom,sm6150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1c100>; + compatible = "qcom,sm6150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + gcc: clock-controller@100000 { compatible = "qcom,sm6150-gcc", "syscon"; reg = <0x100000 0x1f0000>;