diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index cb841be8..b2a0a391 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -27,6 +27,7 @@ properties: - qcom,sc8180x-llcc - qcom,sc8280xp-llcc - qcom,sdm845-llcc + - qcom,sm6150-llcc - qcom,sm6350-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 1c8b8d47..141e2d72 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,sdx75-debugcc - qcom,sdxbaagha-debugcc - qcom,sm4450-debugcc + - qcom,sm6150-debugcc - qcom,monaco-debugcc - qcom,tuna-debugcc - qcom,kera-debugcc diff --git a/bindings/clock/qcom,qcs615-camcc.yaml b/bindings/clock/qcom,qcs615-camcc.yaml new file mode 100644 index 00000000..1f0e5387 --- /dev/null +++ b/bindings/clock/qcom,qcs615-camcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on QCS615 + + See also: + include/dt-bindings/clock/qcom,camcc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-camcc.h + +properties: + compatible: + enum: + - qcom,qcs615-camcc + - qcom,sa6155-camcc + - qcom,sm6150-camcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0xad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + diff --git a/bindings/clock/qcom,qcs615-dispcc.yaml b/bindings/clock/qcom,qcs615-dispcc.yaml new file mode 100644 index 00000000..ec67c9b8 --- /dev/null +++ b/bindings/clock/qcom,qcs615-dispcc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on QCS615 + +maintainers: + - Ajit Pandey + - Taniya Das + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on QCS615 + + See also: + include/dt-bindings/clock/qcom,dispcc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-dispcc.h + +properties: + compatible: + enum: + - qcom,qcs615-dispcc + - qcom,sa6155-dispcc + - qcom,sm6150-dispcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 clock source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Display port PLL link clock + - description: Display port PLL VCO DIV clock + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dp_phy 0>, + <&mdss_dp_vco 0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + diff --git a/bindings/clock/qcom,qcs615-gcc.yaml b/bindings/clock/qcom,qcs615-gcc.yaml new file mode 100644 index 00000000..96495a3c --- /dev/null +++ b/bindings/clock/qcom,qcs615-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on QCS615. + + See also: + include/dt-bindings/clock/qcom,gcc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-gcc.h + +properties: + compatible: + enum: + - qcom,qcs615-gcc + - qcom,sa6155-gcc + - qcom,sm6150-gcc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,qcs615-gcc"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + diff --git a/bindings/clock/qcom,qcs615-gpucc.yaml b/bindings/clock/qcom,qcs615-gpucc.yaml new file mode 100644 index 00000000..023fbe16 --- /dev/null +++ b/bindings/clock/qcom,qcs615-gpucc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: + include/dt-bindings/clock/qcom,gpucc-sm6150.h + include/dt-bindings/clock/qcom,qcs615-gpucc.h + +properties: + compatible: + enum: + - qcom,qcs615-gpucc + - qcom,sa6155-gpucc + - qcom,sm6150-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 GPUCC div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0x5090000 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + diff --git a/bindings/clock/qcom,qcs615-videocc.yaml b/bindings/clock/qcom,qcs615-videocc.yaml new file mode 100644 index 00000000..5e3f71d9 --- /dev/null +++ b/bindings/clock/qcom,qcs615-videocc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: + include/dt-bindings/clock/qcom,qcs615-videocc.h + include/dt-bindings/clock/qcom,videocc-sm6150.h + +properties: + compatible: + enum: + - qcom,qcs615-videocc + - qcom,sa6155-videocc + - qcom,sm6150-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0xab00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... + diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index 1b915c27..252fdc2b 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -28,6 +28,7 @@ properties: - qcom,sdx75-rpmh-clk - qcom,sdxbaagha-rpmh-clk - qcom,sm4450-rpmh-clk + - qcom,sm6150-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index bd6e5ae7..f24423e7 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -97,6 +97,15 @@ properties: - qcom,sdxbaagha-pcie_anoc, - qcom,sdxbaagha-mem_noc, - qcom,sdxbaagha-system_noc, + - qcom,sm6150-aggre1_noc + - qcom,sm6150-camnoc_virt + - qcom,sm6150-config_noc + - qcom,sm6150-dc_noc + - qcom,sm6150-gem_noc + - qcom,sm6150-ipa_virt + - qcom,sm6150-mc_virt + - qcom,sm6150-mmss_noc + - qcom,sm6150-system_noc - qcom,sm8150-aggre1-noc - qcom,sm8150-aggre2-noc - qcom,sm8150-camnoc-noc diff --git a/bindings/power/supply/qcom/qpnp-qg.yaml b/bindings/power/supply/qcom/qpnp-qg.yaml new file mode 100644 index 00000000..c2c8590f --- /dev/null +++ b/bindings/power/supply/qcom/qpnp-qg.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/qpnp-qg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QPNP PMIC QGAUGE (QG) Device + +maintainers: + - Rakesh Kota + - Jishnu Prakash + - Kamal Wadhwa + +description: | + QPNP PMIC QGAUGE device provides the ability to gauge the State-of-Charge + of the battery. It provides an interface to the clients to read various + battery related parameters. + + Required Node Structure: | + Qgauge device must be described in two level of nodes. The first level + describes the properties of the Qgauge device and the second level + describes the peripherals managed/used of the module. + +properties: + compatible: + enum: + - qcom,pm6150-qg + - qcom,qpnp-qg-lite + - qcom,pmi632-qg + - qcom,pm7250b-qg + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + + qcom,vbatt-cutoff-mv: + description: | + The battery voltage threshold (in mV) at which the + the Qgauge algorithm converges to 0 SOC. If not specified + the default value is 3400 mV. + + qcom,vbatt-low-mv: + description: | + The battery voltage threshold (in mV) at which the + the VBAT_LOW interrupt fires. Software can take necessary + the action when this interrupt fires. If not specified + the default value is 3500 mV. + + qcom,vbatt-low-cold-mv: + description: | + The battery voltage threshold (in mV) at which the + the VBAT_LOW interrupt fires. The threshold is only + applied at cold temperature specified by + 'qcom,cold-temp-threshold'. Software can take necessary + the action when this interrupt fires. If not specified + the default value is 3800 mV. + + qcom,vbatt-empty-mv: + description: | + The battery voltage threshold (in mV) at which the + vbatt-empty interrupt fires. The SOC is forced to 0 + when this interrupt fires. If not specified, the + default value is 3200 mV. + + qcom,vbatt-empty-cold-mv: + description: | + The battery voltage threshold (in mV) at which the + vbatt-empty interrupt fires. This threshold is only + applied at cold temperature specified by + 'qcom,cold-temp-threshold'. The SOC is forced to 0 + when this interrupt fires. If not specified, the + default value is 3000 mV. + + qcom,s3-entry-fifo-length: + description: | + The minimum number if FIFO samples which have to qualify the + S3 IBAT entry threshold (qcom,s3-entry-ibat-ua) for QG + to enter into S3 state. + Minimum Value = 1 Maximum Value = 8. The hardware default + is configured to 3. + + io-channels: + description: | + IIO channel specifiers for each name in io-channel-names. + + io-channel-names: + description: | + Names of the IIO channels that are used by QG device. + +additionalProperties: false + +required: + - compatible + - io-channels + - io-channel-names + +patternProperties: + "^qcom,qgauge@[0-9a-f].*$": + type: object + + properties: + reg: + description: Addresses and sizes for the specified peripheral. + + interrupts: + description: Interrupt mapping as per the interrupt encoding. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + additionalProperties: false + + "^qcom,qg-sdam@[0-9a-f].*$": + type: object + + properties: + reg: + description: Addresses and sizes for the specified peripheral. + + required: + - reg + + additionalProperties: false + +examples: + - | + qpnp,qg { + compatible = "qcom,pm6150-qg"; + depends-on-supply = <&pm6150_vadc>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + qcom,vbatt-cutoff-mv = <3200>; + qcom,vbatt-low-mv = <3300>; + qcom,vbatt-low-cold-mv = <3700>; + qcom,vbatt-empty-mv = <3000>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + io-channels = <&pm6150_vadc ADC5_BAT_THERM_100K_PU>, + <&pm6150_vadc ADC5_BAT_ID_100K_PU>, + <&pm6150_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm6150_charger PSY_IIO_RECHARGE_SOC>, + <&pm6150_charger PSY_IIO_FORCE_RECHARGE>, + <&pm6150_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800>; + interrupts = + <0x0 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600>; + }; + }; +... diff --git a/bindings/power/supply/qcom/smb1390-charger-psy.yaml b/bindings/power/supply/qcom/smb1390-charger-psy.yaml new file mode 100644 index 00000000..5e85fcef --- /dev/null +++ b/bindings/power/supply/qcom/smb1390-charger-psy.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/smb1390-charger-psy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SMB1390 Charger + +maintainers: + - Rakesh Kota + - Jishnu Prakash + - Kamal Wadhwa + +description: | + SMB1390 charge pump is paired with QTI family of standalone chargers to + enable a high current, high efficiency Li+ battery charging system. + + Required Node Structure: | + SMB1390 Charger must be described in two levels of device nodes. + +properties: + compatible: + enum: + - qcom,smb1390-charger-psy + - qcom,smb1390-slave + + "#io-channel-cells": + const: 1 + +additionalProperties: false + +required: + - compatible + - "#io-channel-cells" + +patternProperties: + '^qcom,core[0-9a-f].*$': + type: object + + properties: + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - interrupts + - interrupt-names + + additionalProperties: false + +examples: + - | + smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger-psy"; + #io-channel-cells = <1>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "tsd-fault", + "irev-fault", + "vph-ov-hard", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; + }; +... diff --git a/bindings/soc/qcom/qcom,power-state.yaml b/bindings/soc/qcom/qcom,power-state.yaml new file mode 100644 index 00000000..8a786b8a --- /dev/null +++ b/bindings/soc/qcom/qcom,power-state.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,power-state.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Power State Management Device + +maintainers: + - Maulik Shah + +description: | + This binding describes the Qualcomm Technologies, Inc. Power State Management device. + This device helps with various Qualcomm SoC level Power state like deep sleep and + hibernation and user space management for subsystem and SoC low power states. + +properties: + compatible: + const: qcom,power-state + + qcom,subsys-name: + description: subsystem names supported + + qcom,rproc-handle: + description: phandle to subsys defined in subsys-name. + +required: + - compatible + - qcom,subsys-name + - qcom,rproc-handle + +additionalProperties: false + +examples: + - | + qcom,power-state { + compatible = "qcom,power-state"; + qcom,subsys-name = "adsp", "modem"; + qcom,rproc-handle = <&adsp_pas>, <&modem_pas>; + }; +... diff --git a/bindings/thermal/qcom-tsens.yaml b/bindings/thermal/qcom-tsens.yaml index 99c768ec..cc53a846 100644 --- a/bindings/thermal/qcom-tsens.yaml +++ b/bindings/thermal/qcom-tsens.yaml @@ -53,6 +53,7 @@ properties: - qcom,sc8280xp-tsens - qcom,sdm630-tsens - qcom,sdm845-tsens + - qcom,sm6150-tsens - qcom,sm6350-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens diff --git a/bindings/ufs/qcom,ufs.yaml b/bindings/ufs/qcom,ufs.yaml index 83a3a2dc..92631021 100644 --- a/bindings/ufs/qcom,ufs.yaml +++ b/bindings/ufs/qcom,ufs.yaml @@ -38,6 +38,7 @@ properties: - qcom,ufs-phy-qmp-v4-waipio - qcom,ufs-phy-qmp-v4-sun - qcom,ufs-phy-qmp-v4-niobe + - qcom,ufs-phy-qmp-v3-660 - const: qcom,ufshc - const: jedec,ufs-2.0 diff --git a/bindings/usb/qcom,qpnp-pdphy.yaml b/bindings/usb/qcom,qpnp-pdphy.yaml new file mode 100644 index 00000000..c76542a3 --- /dev/null +++ b/bindings/usb/qcom,qpnp-pdphy.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,qpnp-pdphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: USB Power Delivery Physical layer + +maintainers: + - Wesley Cheng + +properties: + compatible: + items: + - enum: + - qcom,qpnp-pdphy + + reg: + description: Register Base address of the qpnp pd phy + maxItems: 1 + + vdd-pdphy-supply: + description: phandle to the VDD supply regulator node + + interrupts: + minItems: 1 + maxItems: 7 + + interrupt-names: + minItems: 1 + items: + - const: sig-tx + - const: sig-rx + - const: msg-tx + - const: msg-rx + - const: msg-tx-failed + - const: msg-tx-discarded + - const: msg-rx-discarded + + vbus-supply: + description: Regulator that enables VBUS source output + + vconn-supply: + description: Regulator that enables VCONN source output. This will be supplied + on the USB CC line that is not used for communication when Ra resistance is detected. + + qcom,default-sink-caps: + description: List of 32-bit values representing the nominal sink capabilities in voltage + (millivolts) and current (milliamps) pairs. + items: + items: + - + description: volts + minimum: 0 + maximum: 100000 + + - + description: amps + minimum: 0 + maximum: 100000 + + qcom,no-usb3-dp-concurrency: + description: If present, usb3 and dp concurrency is not supported. + type: boolean + + qcom,pd-20-source-only: + description: If present, only PD2.0 is supported as source. + type: boolean + + qcom,pps-disabled: + description: If defined pps support will be disabled. + Standard PD communication will remain unaffected. + type: boolean + +additionalProperties: false + +examples: + - | + qcom,qpnp-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm8998_l24>; + interrupts = <0x2 0x17 0x1>, + <0x2 0x17 0x2>, + <0x2 0x17 0x3>, + <0x2 0x17 0x4>, + <0x2 0x17 0x5>, + <0x2 0x17 0x6>, + <0x2 0x17 0x7>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded"; + + vbus-supply = <&pm8998_l2>; + vconn-supply = <&pm8998_l3>; + qcom,no-usb3-dp-concurrency; + qcom,pd-20-source-only; + qcom,pps-disabled; + qcom,default-sink-caps = <5000 8000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 9000>; /* 12V @ 9A */ + }; +... diff --git a/qcom/kera-atp.dtsi b/qcom/kera-atp.dtsi index 1c0ce4c9..b2d36494 100644 --- a/qcom/kera-atp.dtsi +++ b/qcom/kera-atp.dtsi @@ -85,3 +85,58 @@ &pm8550ve_f_die_temp { status = "disabled"; }; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c3-supply = <&L3B_LEVEL>; + periph-1c4-supply = <&L4B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1d2-supply = <&L18B>; + periph-1d3-supply = <&L19B>; + periph-1d4-supply = <&L20B>; + periph-1d5-supply = <&L21B>; + periph-1d6-supply = <&L22B>; + periph-1d7-supply = <&L23B>; + periph-19b-supply = <&S1B>; + periph-19e-supply = <&S2B>; + periph-1a1-supply = <&S3B>; + periph-1a2-supply = <&S4B>; + periph-1e4-supply = <&BOB>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D>; + periph-3c3-supply = <&L3D_LEVEL>; + periph-39b-supply = <&S1D_LEVEL>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a2-supply = <&S4D_LEVEL>; + periph-3a3-supply = <&S5D_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/kera-mtp.dtsi b/qcom/kera-mtp.dtsi index 66d3495a..e50c5703 100644 --- a/qcom/kera-mtp.dtsi +++ b/qcom/kera-mtp.dtsi @@ -93,3 +93,58 @@ &usb0 { qcom,wcd_usbss = <&wcd_usbss>; }; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c3-supply = <&L3B_LEVEL>; + periph-1c4-supply = <&L4B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1d2-supply = <&L18B>; + periph-1d3-supply = <&L19B>; + periph-1d4-supply = <&L20B>; + periph-1d5-supply = <&L21B>; + periph-1d6-supply = <&L22B>; + periph-1d7-supply = <&L23B>; + periph-19b-supply = <&S1B>; + periph-19e-supply = <&S2B>; + periph-1a1-supply = <&S3B>; + periph-1a2-supply = <&S4B>; + periph-1e4-supply = <&BOB>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D>; + periph-3c3-supply = <&L3D_LEVEL>; + periph-39b-supply = <&S1D_LEVEL>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a2-supply = <&S4D_LEVEL>; + periph-3a3-supply = <&S5D_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/kera-qrd.dtsi b/qcom/kera-qrd.dtsi index 67109ccd..ef9c0904 100644 --- a/qcom/kera-qrd.dtsi +++ b/qcom/kera-qrd.dtsi @@ -167,3 +167,58 @@ ssusb_redriver = <&redriver>; }; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c3-supply = <&L3B_LEVEL>; + periph-1c4-supply = <&L4B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1d2-supply = <&L18B>; + periph-1d3-supply = <&L19B>; + periph-1d4-supply = <&L20B>; + periph-1d5-supply = <&L21B>; + periph-1d6-supply = <&L22B>; + periph-1d7-supply = <&L23B>; + periph-19b-supply = <&S1B>; + periph-19e-supply = <&S2B>; + periph-1a1-supply = <&S3B>; + periph-1a2-supply = <&S4B>; + periph-1e4-supply = <&BOB>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D>; + periph-3c3-supply = <&L3D_LEVEL>; + periph-39b-supply = <&S1D_LEVEL>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a2-supply = <&S4D_LEVEL>; + periph-3a3-supply = <&S5D_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 8caec9be..d94c3916 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -349,6 +349,12 @@ size = <0x0 0x1000000>; linux,cma-default; }; + + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; }; }; @@ -536,6 +542,11 @@ }; }; + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + mini_dump_mode { compatible = "qcom,minidump"; status = "ok"; diff --git a/qcom/qcs610-iot.dtsi b/qcom/qcs610-iot.dtsi index 26b86790..495af8ae 100644 --- a/qcom/qcs610-iot.dtsi +++ b/qcom/qcs610-iot.dtsi @@ -8,3 +8,35 @@ compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; qcom,board-id = <32 0>; }; + +&L16A { + regulator-max-microvolt = <3304000>; +}; + +&L19A { + regulator-max-microvolt = <3304000>; +}; + +&L4C { + regulator-max-microvolt = <2912000>; +}; + +&L5C { + regulator-max-microvolt = <2912000>; +}; + +&L13A { + regulator-always-on; +}; + +&L7C { + regulator-always-on; +}; + +&L10A { + regulator-always-on; +}; + +&L14A { + regulator-always-on; +}; diff --git a/qcom/qcs610-opk.dtsi b/qcom/qcs610-opk.dtsi index 3fda344a..925ef5e3 100644 --- a/qcom/qcs610-opk.dtsi +++ b/qcom/qcs610-opk.dtsi @@ -12,3 +12,39 @@ compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; qcom,board-id = <32 0>; }; + +&tlmm { + qcom,gpios-reserved = <6 7 8 9>; +}; + +&L16A { + regulator-max-microvolt = <3304000>; +}; + +&L19A { + regulator-max-microvolt = <3304000>; +}; + +&L4C { + regulator-max-microvolt = <2912000>; +}; + +&L5C { + regulator-max-microvolt = <2912000>; +}; + +&L13A { + regulator-always-on; +}; + +&L7C { + regulator-always-on; +}; + +&L10A { + regulator-always-on; +}; + +&L14A { + regulator-always-on; +}; diff --git a/qcom/sm6150-gdsc.dtsi b/qcom/sm6150-gdsc.dtsi new file mode 100644 index 00000000..4ab74042 --- /dev/null +++ b/qcom/sm6150-gdsc.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + reg = <0x106004 0x4>; + regulator-name = "emac_gdsc"; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + regulator-name = "pcie_0_gdsc"; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + regulator-name = "ufs_phy_gdsc"; + status = "disabled"; + }; + + usb20_sec_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + reg = <0x1a6004 0x4>; + regulator-name = "usb20_sec_gdsc"; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + reg = <0x10f004 0x4>; + regulator-name = "usb30_prim_gdsc"; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + reg = <0x17d040 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + reg = <0x17d044 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + reg = <0x17d048 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + reg = <0x17d04c 0x4>; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + reg = <0x17d050 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + reg = <0x17d054 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + reg = <0x17d058 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + titan_top_gdsc: qcom,gdsc@ad0b134 { + compatible = "qcom,gdsc"; + reg = <0xad0b134 0x4>; + regulator-name = "titan_top_gdsc"; + status = "disabled"; + }; + + bps_gdsc: qcom,gdsc@ad06004 { + compatible = "qcom,gdsc"; + reg = <0xad06004 0x4>; + regulator-name = "bps_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + reg = <0xad09004 0x4>; + regulator-name = "ife_0_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + reg = <0xad0a004 0x4>; + regulator-name = "ife_1_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + reg = <0xad07004 0x4>; + regulator-name = "ipe_0_gdsc"; + parent-supply = <&titan_top_gdsc>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + reg = <0xaf03000 0x4>; + regulator-name = "mdss_core_gdsc"; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "qcom,gdsc"; + reg = <0x509106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "qcom,gdsc"; + reg = <0x509100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + reg = <0xab00874 0x4>; + regulator-name = "vcodec0_gdsc"; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + reg = <0xab00814 0x4>; + regulator-name = "venus_gdsc"; + status = "disabled"; + }; +}; diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi new file mode 100644 index 00000000..f4da9acb --- /dev/null +++ b/qcom/sm6150-pinctrl.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm {}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 72b62dd6..a86e95db 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -4,8 +4,16 @@ */ #include +#include +#include +#include +#include +#include +#include +#include #include #include +#include / { model = "Qualcomm Technologies, Inc. SM6150"; @@ -43,6 +51,7 @@ cache-size = <0x8000>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -66,6 +75,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -84,6 +94,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -101,6 +112,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -118,6 +130,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -135,6 +148,7 @@ dynamic-power-coefficient = <100>; cache-size = <0x8000>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0 6>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -152,6 +166,7 @@ dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1 2>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; @@ -170,6 +185,7 @@ dynamic-power-coefficient = <404>; cache-size = <0x10000>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1 2>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -427,6 +443,16 @@ , ; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,sm6150-rpmh-clk"; + #clock-cells = <1>; + status = "okay"; + }; }; }; @@ -448,6 +474,11 @@ , ; }; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; }; }; @@ -540,6 +571,198 @@ }; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + camnoc_virt: interconnect@0 { + compatible = "qcom,sm6150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1 { + compatible = "qcom,sm6150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,sm6150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm6150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3e200>; + compatible = "qcom,sm6150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x5080>; + compatible = "qcom,sm6150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x1f300>; + compatible = "qcom,sm6150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg = <0x1700000 0x3f200>; + compatible = "qcom,sm6150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1c100>; + compatible = "qcom,sm6150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,sm6150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + protected-clocks = , + , + , + , + , + , + ; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm6150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sm6150-gpucc", "syscon"; + reg = <0x5090000 0x9000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "bi_tcxo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm6150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm6150-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc>; + qcom,videocc = <&videocc>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <2>; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; @@ -566,6 +789,294 @@ "l3-scu-errirq", "l3-scu-faultirq"; }; + + tlmm: pinctrl@03000000 { + compatible = "qcom,sm6150-pinctrl"; + reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-reserved = <0 1 2 3 6 7 8 9>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm8150-apss-shared"; + reg = <0x17c00000 0x1000>; + #mbox-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + qmp_aop: qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom_smp2p_adsp: smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "sm6150-regulator.dtsi" +#include "sm6150-gdsc.dtsi" +#include "sm6150-pinctrl.dtsi" +#include "msm-rdbg.dtsi" + +&tlmm { + status = "okay"; +}; + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb20_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&titan_top_gdsc { + parent-supply = <&VDD_MX_LEVEL>; + status = "ok"; +}; + +&bps_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + status = "ok"; +}; + +&ife_1_gdsc { + status = "ok"; +}; + +&ipe_0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +}; diff --git a/qcom/sun-cdp.dtsi b/qcom/sun-cdp.dtsi index 28d1a324..e548c260 100644 --- a/qcom/sun-cdp.dtsi +++ b/qcom/sun-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -206,7 +206,14 @@ resets = <&gcc GCC_SDCC2_BCR>; reset-names = "core_reset"; + /* + * By default, the Sun reference platforms use Level Shifter + * devices with its Feedback Clock signal connects to the MSM. + * Without the external feedback clock, the HS50 mode works at + * reduced frequency at 37.5MHz. + */ qcom,uses_level_shifter; + qcom,external-fb-clk; }; &eusb2_phy0 { diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index 22d806c0..6b9b9be8 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -282,7 +282,14 @@ resets = <&gcc GCC_SDCC2_BCR>; reset-names = "core_reset"; + /* + * By default, the Sun reference platforms use Level Shifter + * devices with its Feedback Clock signal connects to the MSM. + * Without the external feedback clock, the HS50 mode works at + * reduced frequency at 37.5MHz. + */ qcom,uses_level_shifter; + qcom,external-fb-clk; }; &pmih010x_eusb2_repeater { diff --git a/qcom/sun-qrd.dtsi b/qcom/sun-qrd.dtsi index d71a76a4..bb420bf0 100644 --- a/qcom/sun-qrd.dtsi +++ b/qcom/sun-qrd.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -219,7 +219,14 @@ resets = <&gcc GCC_SDCC2_BCR>; reset-names = "core_reset"; + /* + * By default, the Sun reference platforms use Level Shifter + * devices with its Feedback Clock signal connects to the MSM. + * Without the external feedback clock, the HS50 mode works at + * reduced frequency at 37.5MHz. + */ qcom,uses_level_shifter; + qcom,external-fb-clk; }; &eusb2_phy0 {