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ARM: dts: msm: Add clock handles to CPU nodes for Sun

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Add clock handles to CPU nodes to enable frequency domains for cpus.

Change-Id: I77dc5dbedbe7704d392c58913647beaa36571872
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
This commit is contained in:
Vivek Aknurwar
2023-09-26 12:04:31 -07:00
parent 8dcf3ae18d
commit 37eecd0a8c
1 changed files with 8 additions and 0 deletions
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8
qcom/sun.dtsi
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@@ -54,6 +54,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
L2_0: l2-cache { L2_0: l2-cache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
cache-level = <2>; cache-level = <2>;
@@ -66,6 +67,7 @@
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU2: cpu@200 { CPU2: cpu@200 {
@@ -74,6 +76,7 @@
reg = <0x0 0x200>; reg = <0x0 0x200>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU3: cpu@300 { CPU3: cpu@300 {
@@ -82,6 +85,7 @@
reg = <0x0 0x300>; reg = <0x0 0x300>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU4: cpu@400 { CPU4: cpu@400 {
@@ -90,6 +94,7 @@
reg = <0x0 0x400>; reg = <0x0 0x400>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU5: cpu@500 { CPU5: cpu@500 {
@@ -98,6 +103,7 @@
reg = <0x0 0x500>; reg = <0x0 0x500>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU6: cpu@10000 { CPU6: cpu@10000 {
@@ -106,6 +112,7 @@
reg = <0x0 0x10000>; reg = <0x0 0x10000>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
clocks = <&scmi_perf 1>;
L2_6: l2-cache { L2_6: l2-cache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
cache-level = <2>; cache-level = <2>;
@@ -118,6 +125,7 @@
reg = <0x0 0x10100>; reg = <0x0 0x10100>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
clocks = <&scmi_perf 1>;
}; };
cpu-map { cpu-map {