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ARM: dts: msm: Add pcie phy settings for sun

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Add pcie phy settings sequence in sun.

Change-Id: I58dfb2ecb586ac4ce4f2e06bbc02a6cb1e803960
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This commit is contained in:
Prudhvi Yarlagadda
2023-11-16 14:50:20 -08:00
parent 3da89570d2
commit 37824f4ca3
1 changed files with 122 additions and 0 deletions
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122
qcom/sun-pcie.dtsi
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@@ -123,10 +123,132 @@
qcom,ep-latency = <10>; qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>; qcom,num-parf-testbus-sel = <0xb9>;
qcom,pcie-phy-ver = <93>;
qcom,phy-status-offset = <0x414>; qcom,phy-status-offset = <0x414>;
qcom,phy-status-bit = <6>; qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x440>; qcom,phy-power-down-offset = <0x440>;
qcom,phy-sequence = <0x0440 0x03 0x0
0x00c0 0x01 0x0
0x00cc 0x62 0x0
0x00d0 0x02 0x0
0x0060 0xf8 0x0
0x0064 0x01 0x0
0x0000 0x93 0x0
0x0004 0x01 0x0
0x00e0 0x90 0x0
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0x00f4 0x07 0x0
0x0070 0x02 0x0
0x0010 0x02 0x0
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0x0078 0x36 0x0
0x0018 0x36 0x0
0x0110 0x08 0x0
0x00bc 0x0a 0x0
0x0120 0x42 0x0
0x0080 0x04 0x0
0x0084 0x0d 0x0
0x0020 0x0a 0x0
0x0024 0x1a 0x0
0x0088 0x41 0x0
0x0028 0x34 0x0
0x0090 0xab 0x0
0x0094 0xaa 0x0
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0x1370 0xd1 0x0
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0x1384 0xd1 0x0
0x12cc 0x00 0x0
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0x1800 0x00 0x0
0x1084 0x35 0x0
0x108c 0x10 0x0
0x1090 0x31 0x0
0x1094 0x7f 0x0
0x10e4 0x02 0x0
0x1040 0x06 0x0
0x103c 0x18 0x0
0x1ba4 0x38 0x0
0x1adc 0x11 0x0
0x1b60 0x12 0x0
0x1b64 0xda 0x0
0x1b68 0x1b 0x0
0x1b6c 0xda 0x0
0x1b5c 0x19 0x0
0x1b74 0x09 0x0
0x1b78 0x49 0x0
0x1b7c 0x1b 0x0
0x1b80 0x9c 0x0
0x1b70 0xd1 0x0
0x1b88 0x09 0x0
0x1b8c 0x49 0x0
0x1b90 0x1b 0x0
0x1b94 0x9c 0x0
0x1b84 0xd1 0x0
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0x1ad8 0x09 0x0
0x1b18 0x1c 0x0
0x1af8 0x07 0x0
0x1bf8 0x08 0x0
0x1884 0x35 0x0
0x188c 0x10 0x0
0x1890 0x31 0x0
0x1894 0x7f 0x0
0x18e4 0x02 0x0
0x1840 0x06 0x0
0x183c 0x18 0x0
0x04dc 0x05 0x0
0x0588 0x77 0x0
0x0598 0x0b 0x0
0x08a4 0x1e 0x0
0x08f4 0x27 0x0
0x05e4 0x0f 0x0
0x080c 0x1d 0x0
0x0814 0x07 0x0
0x0820 0xc1 0x0
0x0894 0x00 0x0
0x05d0 0x8c 0x0
0x0568 0x17 0x0
0x0400 0x00 0x0
0x0444 0x03 0x0>;
pcie0_rp: pcie0_rp { pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>; reg = <0 0 0 0 0>;
}; };