From 36574cc90bf453edf91f557650caebb2e1ada24f Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Wed, 13 Nov 2024 15:18:54 +0530 Subject: [PATCH] ARM: dts: qcom: Add socd and bcl support for pmih010x & pmiv010x Add socd mitigation and bcl support for pmih010x & pmiv010x PMIC. Change-Id: If64fe4d1a22801dda5d1ade4a83ed0955fcadd7b Signed-off-by: Nitesh Kumar Signed-off-by: Priyansh Jain --- qcom/pm7550ba.dtsi | 1 - qcom/pmiv010x.dtsi | 176 +++++++++++++++++++++++++++++++++ qcom/tuna-cdp.dtsi | 1 + qcom/tuna-pm7550ba.dtsi | 57 +++++++++++ qcom/tuna-pmih010x.dtsi | 101 +++++++++++++++++++ qcom/tuna-pmiv0108.dtsi | 57 +++++++++++ qcom/tuna-thermal-overlay.dtsi | 94 ------------------ 7 files changed, 392 insertions(+), 95 deletions(-) diff --git a/qcom/pm7550ba.dtsi b/qcom/pm7550ba.dtsi index d526e3b8..c8f07c97 100644 --- a/qcom/pm7550ba.dtsi +++ b/qcom/pm7550ba.dtsi @@ -221,7 +221,6 @@ }; }; - pm7550ba-bcl-lvl0 { polling-delay-passive = <50>; polling-delay = <0>; diff --git a/qcom/pmiv010x.dtsi b/qcom/pmiv010x.dtsi index d53c0606..a0a9578e 100644 --- a/qcom/pmiv010x.dtsi +++ b/qcom/pmiv010x.dtsi @@ -97,6 +97,24 @@ <0x7 0x7d 0x1 IRQ_TYPE_EDGE_RISING>, <0x7 0x98 0x1 IRQ_TYPE_EDGE_RISING>; }; + + pmiv010x_bcl: bcl@4700 { + compatible = "qcom,pmiv010x-bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x7 0x47 0x0 IRQ_TYPE_NONE>, + <0x7 0x47 0x1 IRQ_TYPE_NONE>, + <0x7 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; }; }; @@ -126,4 +144,162 @@ }; }; }; + + pmiv010x-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmiv010x-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <9000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmiv010x-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmiv010x-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmiv010x-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + vbat { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 2>; + + trips { + vbat_lvl0:vbat-lvl0 { + temperature = <2800>; + hysteresis = <100>; + type = "passive"; + }; + + vbat_lvl1:vbat-lvl1 { + temperature = <2600>; + hysteresis = <100>; + type = "passive"; + }; + + vbat_lvl2:vbat-lvl2 { + temperature = <2300>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index d048ade7..8cc40208 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -4,6 +4,7 @@ */ #include +#include "tuna-thermal-overlay.dtsi" &qupv3_se4_i2c { #address-cells = <1>; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index 341597f4..bb7acad2 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -258,6 +258,63 @@ }; }; }; + + pm7550ba-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_0_gpu { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7550ba-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pm7550ba-bcl-lvl2 { + cooling-maps { + lbat_2_gpu { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; }; &pm7550ba_eusb2_repeater { diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi index e90b1c6e..f2ac1b7d 100644 --- a/qcom/tuna-pmih010x.dtsi +++ b/qcom/tuna-pmih010x.dtsi @@ -197,6 +197,107 @@ }; }; }; + + pmih010x-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <7000>; + }; + }; + }; + + pmih010x-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <9000>; + }; + }; + }; + + pmih010x-2s-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmih010x_bcl 8>; + + trips { + ibat_2s_lvl0: ibat-2s-lvl0 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmih010x-2s-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmih010x_bcl 9>; + + trips { + ibat_2s_lvl1: ibat-2s-lvl1 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmih010x-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmih010x-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pmih010x-bcl-lvl2 { + cooling-maps { + lbat_2_gpu { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; }; &pmih010x_eusb2_repeater { diff --git a/qcom/tuna-pmiv0108.dtsi b/qcom/tuna-pmiv0108.dtsi index fdb246ad..15c2767c 100644 --- a/qcom/tuna-pmiv0108.dtsi +++ b/qcom/tuna-pmiv0108.dtsi @@ -183,6 +183,63 @@ }; }; }; + + pmiv010x-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmiv010x-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pmiv010x-bcl-lvl2 { + cooling-maps { + lbat_2_gpu { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; }; &pmiv010x_eusb2_repeater { diff --git a/qcom/tuna-thermal-overlay.dtsi b/qcom/tuna-thermal-overlay.dtsi index 4d2ebf83..c0f874df 100644 --- a/qcom/tuna-thermal-overlay.dtsi +++ b/qcom/tuna-thermal-overlay.dtsi @@ -25,100 +25,6 @@ }; }; - pmih010x-bcl-lvl0 { - cooling-maps { - lbat_modem0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&modem_bcl 1 1>; - }; - - lbat_gpu0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 1 1>; - }; - }; - }; - - pmih010x-bcl-lvl1 { - cooling-maps { - lbat_modem1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&modem_bcl 2 2>; - }; - - lbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 2 2>; - }; - }; - }; - - pmih010x-bcl-lvl2 { - cooling-maps { - lbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu 3 3>; - }; - }; - }; - - pm7550ba-bcl-lvl0 { - cooling-maps { - vph_0_nr_scg { - trip = <&bcl_lvl0>; - cooling-device = <&modem_nr_scg_dsc 3 3>; - }; - - vph_0_nr { - trip = <&bcl_lvl0>; - cooling-device = <&modem_nr_dsc 6 6>; - }; - - vph_0_mdm_lte { - trip = <&bcl_lvl0>; - cooling-device = <&modem_lte_dsc 8 8>; - }; - - vph_gpu0 { - trip = <&bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - }; - }; - - pm7550ba-bcl-lvl1 { - cooling-maps { - vph_1_nr_scg { - trip = <&bcl_lvl1>; - cooling-device = <&modem_nr_scg_dsc 10 10>; - }; - - vph_1_nr { - trip = <&bcl_lvl1>; - cooling-device = <&modem_nr_dsc 9 9>; - }; - - vph_1_mdm_lte { - trip = <&bcl_lvl1>; - cooling-device = <&modem_lte_dsc 10 10>; - }; - - vph_gpu1 { - trip = <&bcl_lvl1>; - cooling-device = <&msm_gpu 3 3>; - }; - }; - }; - - pm7550ba-bcl-lvl2 { - cooling-maps { - vph_gpu2 { - trip = <&bcl_lvl2>; - cooling-device = <&msm_gpu 7 7>; - }; - }; - }; - pmxr2230-bcl-lvl0 { cooling-maps { lbat_0_nr_scg {