From 92f8a37368ce63686c92a9b7a86783d8408d5986 Mon Sep 17 00:00:00 2001 From: AMAN KUMAR Date: Fri, 7 Feb 2025 14:12:31 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Fix iommu address and size properties for kiwi Currently address and size cell property was set to 1, due to that IOVA range that gets created was out of our expected range. This change fixes size-cells and address-cells properties of cnss_pci node to 2 on Canoe kiwi device tree. Change-Id: I03d193fe50f3a17995c5a4b0eacd13b6c749e9f4 CRs-Fixed: 4048012 --- canoe-kiwi-cnss.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/canoe-kiwi-cnss.dtsi b/canoe-kiwi-cnss.dtsi index 7f6bc1d1..9fcab5ba 100644 --- a/canoe-kiwi-cnss.dtsi +++ b/canoe-kiwi-cnss.dtsi @@ -152,8 +152,8 @@ qcom,iommu-group = <&cnss_pci_iommu_group0>; memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition { /* address-cells =3 size-cells=2 from canoe-pcie.dtsi */ From 41f82402699b437b8adfde73df9c612cca3fda9f Mon Sep 17 00:00:00 2001 From: Srinivas Girigowda Date: Thu, 6 Feb 2025 20:31:25 -0800 Subject: [PATCH 2/2] ARM: dts: msm: Add interconnect voting node for canoe kiwi/peach Add the interconnect voting node for canoe kiwi/peach, used for bus bandwidth voting. Change-Id: I4c1828ec5d6e8e8d2298f51f926338f977283a7e CRs-Fixed: 4036509 --- canoe-kiwi-cnss.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++ canoe-peach-cnss.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 93 insertions(+), 1 deletion(-) diff --git a/canoe-kiwi-cnss.dtsi b/canoe-kiwi-cnss.dtsi index 7f6bc1d1..1f671631 100644 --- a/canoe-kiwi-cnss.dtsi +++ b/canoe-kiwi-cnss.dtsi @@ -108,6 +108,52 @@ vdd-wlan-supply = <&S7G>; qcom,vdd-wlan-config = <952000 1100000 0 0 1>; + interconnects = + <&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <9>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 308000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 308000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 308000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 308000>, + /* very high: > 1200 Mbps snoc/anoc: 403 Mhz */ + <175000 3210000>, + /* ultra high: DBS mode snoc/anoc: 403 Mhz */ + <312500 3210000>, + /* super high: DBS mode snoc/anoc: 533 Mhz */ + <587500 6450000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 1610000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547.2 MHz */ + <2250 2188800>, + /* low: 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>, + /* medium: 60-240 Mbps ddr: 547.2 MHz */ + <30000 2188800>, + /* high: 240-1200 Mbps ddr: 547.2 MHz */ + <100000 2188800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 6220800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 8368000>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 12800000>, + /* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>; + qcom,vreg_pdc_map = "S2J1", "bb", "S1J1", "bb", diff --git a/canoe-peach-cnss.dtsi b/canoe-peach-cnss.dtsi index 17f9d1db..db03cf53 100644 --- a/canoe-peach-cnss.dtsi +++ b/canoe-peach-cnss.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -123,6 +123,52 @@ vdd-wlan-ant-share-supply = <&L3K>; qcom,vdd-wlan-ant-share-config = <1200000 1200000 0 0 1>; + interconnects = + <&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <9>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz */ + <2250 308000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz */ + <7500 308000>, + /* medium: 60-240 Mbps snoc/anoc: 100 Mhz */ + <30000 308000>, + /* high: 240-1200 Mbps snoc/anoc: 100 Mhz */ + <100000 308000>, + /* very high: > 1200 Mbps snoc/anoc: 403 Mhz */ + <175000 3210000>, + /* ultra high: DBS mode snoc/anoc: 403 Mhz */ + <312500 3210000>, + /* super high: DBS mode snoc/anoc: 533 Mhz */ + <587500 6450000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */ + <7500 1610000>, + + /** ICC Path 2 **/ + <0 0>, + /* idle: 0-18 Mbps ddr: 547.2 MHz */ + <2250 2188800>, + /* low: 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>, + /* medium: 60-240 Mbps ddr: 547.2 MHz */ + <30000 2188800>, + /* high: 240-1200 Mbps ddr: 547.2 MHz */ + <100000 2188800>, + /* very high: > 1200 Mbps ddr: 1555 MHz */ + <175000 6220800>, + /* ultra high: DBS mode ddr: 2092 MHz */ + <312500 8368000>, + /* super high: DBS mode ddr: 3.2 GHz */ + <587500 12800000>, + /* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */ + <7500 2188800>; + qcom,vreg_pdc_map = "s1j", "bb", "s2j", "rf",