From 35e3460d12d5468ec5499eda53450ce7351e5fc0 Mon Sep 17 00:00:00 2001
From: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Date: Wed, 20 Dec 2023 15:57:02 +0800
Subject: [PATCH] ARM: dts: msm: correct msr register size on sun

Correct msr register size to 0x78 on sun.

Change-Id: I495c13c6a41fad25ccedae29927daba00a68aaa1
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
---
 qcom/sun-coresight.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/qcom/sun-coresight.dtsi b/qcom/sun-coresight.dtsi
index 368d6452..3a3254a6 100644
--- a/qcom/sun-coresight.dtsi
+++ b/qcom/sun-coresight.dtsi
@@ -19,7 +19,7 @@
 	swao_csr: csr@10b11000 {
 		compatible = "qcom,coresight-csr";
 		reg = <0x10b11000 0x1000>,
-		      <0x10b110f8 0x6c>;
+		      <0x10b110f8 0x78>;
 		reg-names = "csr-base", "msr-base";
 
 		coresight-name = "coresight-swao-csr";