Merge "ARM: dts: qcom: Add SPU related register to sun dtsi"

This commit is contained in:
qctecmdr
2024-01-31 19:30:06 -08:00
committed by Gerrit - the friendly Code Review server
2 changed files with 16 additions and 9 deletions

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@@ -10,7 +10,8 @@ maintainers:
- Nurit Lichtenstein <quic_nuritl@quicinc.com>
description:
This document defines the binding for a component that loads and boots firmware on the QTI Secure Processor.
This document defines the binding for a component that loads
and boots firmware on the QTI Secure Processor.
properties:
compatible:
@@ -29,6 +30,7 @@ properties:
- description: RMB error register
- description: RMB general purpose register
- description: RMB error spare2 register
- description: SP PBL patch version register
reg-names:
items:
@@ -38,9 +40,9 @@ properties:
- const: rmb_err
- const: rmb_general_purpose
- const: rmb_err_spare2
- const: sp_pbl_patch_ver
interrupts:
minItems: 1
items:
- description: Generic interrupt
@@ -78,6 +80,8 @@ required:
- clock-names
- memory-region
additionalProperties: false
examples:
# The following example represents the qcom,spss node on a sun device.
- |
@@ -89,9 +93,11 @@ examples:
<0x1881028 0x4>,
<0x188103c 0x4>,
<0x1881100 0x4>,
<0x1882014 0x4>;
<0x1882014 0x4>,
<0x221C8490 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
"rmb_err", "rmb_general_purpose", "rmb_err_spare2";
"rmb_err", "rmb_general_purpose", "rmb_err_spare2",
"sp_pbl_patch_ver";
interrupts = <0 352 1>;
cx-supply = <&VDD_CX_LEVEL>;

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@@ -1463,9 +1463,10 @@
<0x1881028 0x4>,
<0x188103c 0x4>,
<0x1881100 0x4>,
<0x1882014 0x4>;
<0x1882014 0x4>,
<0x221C8490 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
"rmb_err", "rmb_general_purpose", "rmb_err_spare2";
"rmb_err", "rmb_general_purpose", "rmb_err_spare2", "sp_pbl_patch_ver";
interrupts = <0 352 1>;
cx-supply = <&VDD_CX_LEVEL>;