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ARM: dts: msm: Add USB3 SSPHY DT nodes for sdxkova

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Add QMP USB3 SSPHY device-tree nodes for sdxkova.

Change-Id: I7157198092c703b1c8e9e6b40f984959bfaab89e
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
This commit is contained in:
Prashanth K
2024-08-23 15:37:41 +05:30
parent a42a681f5d
commit 35b268fa14
1 changed files with 157 additions and 1 deletions
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158
qcom/sdxkova-usb.dtsi
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@@ -3,6 +3,7 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-uni.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
&soc {
@@ -45,7 +46,7 @@
compatible = "snps,dwc3";
reg = <0x0 0xa600000 0x0 0xd93c>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb_nop_phy>, <&usb_nop_phy>;
usb-phy = <&usb_nop_phy>, <&usb_qmp_phy>;
snps,has-lpm-erratum;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
@@ -62,6 +63,161 @@
};
/* USB port related QMP USB UNI PHY */
usb_qmp_phy: ssphy@ff6000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0x0 0xff6000 0x0 0x2000>,
<0x0 0xff7400 0x0 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
vdd-supply = <&L4B>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L1B>;
qcom,core-max-load-uA = <15000>;
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&gcc GCC_USB3_PRIM_CLKREF_EN>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk", "ref_clk_src",
"cfg_ahb_clk";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
qcom,qmp-phy-init-seq =
/* <reg_offset, value> */
<QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x9E
QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x06
QSERDES_COM_CP_CTRL_MODE1 0x02
QSERDES_COM_PLL_RCTRL_MODE1 0x16
QSERDES_COM_PLL_CCTRL_MODE1 0x36
QSERDES_COM_CORECLK_DIV_MODE1 0x04
QSERDES_COM_LOCK_CMP1_MODE1 0x2E
QSERDES_COM_LOCK_CMP2_MODE1 0x82
QSERDES_COM_DEC_START_MODE1 0x82
QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
QSERDES_COM_HSCLK_SEL_1 0x01
QSERDES_COM_VCO_TUNE1_MODE1 0x25
QSERDES_COM_VCO_TUNE2_MODE1 0x02
QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xB7
QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xB7
QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x9E
QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x06
QSERDES_COM_CP_CTRL_MODE0 0x02
QSERDES_COM_PLL_RCTRL_MODE0 0x16
QSERDES_COM_PLL_CCTRL_MODE0 0x36
QSERDES_COM_LOCK_CMP1_MODE0 0x12
QSERDES_COM_LOCK_CMP2_MODE0 0x34
QSERDES_COM_DEC_START_MODE0 0x82
QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
QSERDES_COM_VCO_TUNE1_MODE0 0x25
QSERDES_COM_VCO_TUNE2_MODE0 0x02
QSERDES_COM_BG_TIMER 0x0E
QSERDES_COM_SSC_EN_CENTER 0x01
QSERDES_COM_SSC_PER1 0x31
QSERDES_COM_SSC_PER2 0x01
QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
QSERDES_COM_SYSCLK_EN_SEL 0x1A
QSERDES_COM_LOCK_CMP_CFG 0x14
QSERDES_COM_VCO_TUNE_MAP 0x04
QSERDES_COM_CORE_CLK_EN 0x20
QSERDES_COM_CMN_CONFIG_1 0x16
QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B
QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37
QSERDES_COM_ADDITIONAL_MISC 0x0C
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xC4
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x89
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21
PCIE_USB3_UNI_PCS_RX_SIGDET_LVL 0xAA
PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
PCIE_USB3_UNI_PCS_CDR_RESET_TIME 0x0A
PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
PCIE_USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C
PCIE_USB3_UNI_PCS_EQ_CONFIG1 0x4B
PCIE_USB3_UNI_PCS_EQ_CONFIG5 0x10
QSERDES_TX_RES_CODE_LANE_TX 0x00
QSERDES_TX_RES_CODE_LANE_RX 0x00
QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x1F
QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x09
QSERDES_TX_LANE_MODE_1 0xF5
QSERDES_TX_LANE_MODE_3 0x3F
QSERDES_TX_LANE_MODE_4 0x3F
QSERDES_TX_LANE_MODE_5 0x5F
QSERDES_TX_RCV_DETECT_LVL_2 0x12
QSERDES_TX_PI_QEC_CTRL 0x21
QSERDES_RX_UCDR_FO_GAIN 0x0A
QSERDES_RX_UCDR_SO_GAIN 0x06
QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F
QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7F
QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF
QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F
QSERDES_RX_UCDR_PI_CONTROLS 0x99
QSERDES_RX_UCDR_SB2_THRESH1 0x08
QSERDES_RX_UCDR_SB2_THRESH2 0x08
QSERDES_RX_UCDR_SB2_GAIN1 0x00
QSERDES_RX_UCDR_SB2_GAIN2 0x0A
QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0xA0
QSERDES_RX_VGA_CAL_CNTRL1 0x54
QSERDES_RX_VGA_CAL_CNTRL2 0x0F
QSERDES_RX_GM_CAL 0x13
QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F
QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4A
QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A
QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x07
QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
QSERDES_RX_SIGDET_CNTRL 0x04
QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E
QSERDES_RX_RX_MODE_00_LOW 0x3F
QSERDES_RX_RX_MODE_00_HIGH 0xBF
QSERDES_RX_RX_MODE_00_HIGH2 0xFF
QSERDES_RX_RX_MODE_00_HIGH3 0xDF
QSERDES_RX_RX_MODE_00_HIGH4 0xED
QSERDES_RX_RX_MODE_01_LOW 0xDC
QSERDES_RX_RX_MODE_01_HIGH 0x5C
QSERDES_RX_RX_MODE_01_HIGH2 0x9C
QSERDES_RX_RX_MODE_01_HIGH3 0x1D
QSERDES_RX_RX_MODE_01_HIGH4 0x09
QSERDES_RX_DFE_EN_TIMER 0x04
QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
QSERDES_RX_DCC_CTRL1 0x0C
QSERDES_RX_VTH_CODE 0x10
QSERDES_RX_SIGDET_CAL_CTRL1 0x14
QSERDES_RX_SIGDET_CAL_TRIM 0x08
PCIE_USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
PCIE_USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
PCIE_USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
qcom,qmp-phy-reg-offset =
<PCIE_USB3_UNI_PCS_PCS_STATUS1
PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
PCIE_USB3_UNI_PCS_POWER_DOWN_CONTROL
PCIE_USB3_UNI_PCS_SW_RESET
PCIE_USB3_UNI_PCS_START_CONTROL>;
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};