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Revert "ARM: dts: msm: move esync RCG to SDE DSI node"

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This reverts commit 89f184dd38.

Change-Id: Ie469eea85132ee553518a3f3453c2a19c8ce0514
Signed-off-by: Linux Image Build Automation <quic_ibautomat@quicinc.com>
This commit is contained in:
Linux Image Build Automation
2024-07-31 14:25:07 -07:00
parent 54ea574e80
commit 351096e02c
2 changed files with 12 additions and 22 deletions
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22
display/sun-sde-display.dtsi
View File

@@ -92,17 +92,10 @@
* MDP clock nodes, no actual vote shall be added and this * MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements. * change is done just to satisfy sync state requirements.
*/ */
<&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>;
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC0_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0", clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1", "pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk", "esync_clk_rcg"; "mdp_core_clk";
vddio-supply = <&L12B>; vddio-supply = <&L12B>;
vci-supply = <&L13B>; vci-supply = <&L13B>;
vdd-supply = <&L11B>; vdd-supply = <&L11B>;
@@ -128,17 +121,10 @@
* MDP clock nodes, no actual vote shall be added and this * MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements. * change is done just to satisfy sync state requirements.
*/ */
<&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>;
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC1_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0", clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1", "pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk", "esync_clk_rcg"; "mdp_core_clk";
vddio-supply = <&L12B>; vddio-supply = <&L12B>;
vci-supply = <&L13B>; vci-supply = <&L13B>;
vdd-supply = <&L11B>; vdd-supply = <&L11B>;

12
display/sun-sde.dtsi
View File

@@ -313,13 +313,15 @@
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&mdss_dsi_phy0 1>,
<&dispcc DISP_CC_ESYNC0_CLK>, <&dispcc DISP_CC_ESYNC0_CLK>,
<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
"esc_clk", "xo"; "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
}; };
&mdss_dsi1 { &mdss_dsi1 {
@@ -330,13 +332,15 @@
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&mdss_dsi_phy1 1>,
<&dispcc DISP_CC_ESYNC1_CLK>, <&dispcc DISP_CC_ESYNC1_CLK>,
<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
"esc_clk", "xo"; "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
}; };
&mdss_dsi_phy0 { &mdss_dsi_phy0 {