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ARM: dts: msm: enable qsync for csot panel on sun target

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This change enable qsync for csot panel on sun target.

Change-Id: I50068d98a263f28bc68a300b445125ce5ee73dff
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
This commit is contained in:
Jinfeng Gu
2024-03-06 12:00:04 +08:00
parent 3c8a246c1f
commit 344e1a69e9
8 changed files with 671 additions and 3 deletions
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82
display/sun-sde-display-common.dtsi
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@@ -9,6 +9,10 @@
#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi"
#include "dsi-panel-nt37801-dsc-10bit-video.dtsi"
#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi"
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
#include "dsi-panel-sim-cmd-au.dtsi"
@@ -540,6 +544,84 @@
};
};
&dsi_nt37801_amoled_qsync_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
0b 0a 02 04 00 21 0f];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt37801_amoled_qsync_cmd_cphy {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08
19 08 02 04 00 00 00];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt37801_amoled_qsync_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
0b 0a 02 04 00 21 0f];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt37801_amoled_qsync_video_cphy {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08
19 09 02 04 00 00 00];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_4k_dsc_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";