ARM: dts: msm: Add interconnect voting for Debug UART instance in Tuna
Currently, the interconnect path for the debug UART instance
(i.e., qupv3_se7_2uart) is not added, resulting in a NOC error
due to missing QUP voting.
To prevent the NOC error, add the interconnect path for the debug
UART instance.
Fixes: 7cb884c241
("ARM: dts: msm: Add QUPv3 and GPI DT nodes on tuna")
Change-Id: I6a3829638a244c969d274fe118e51cac7fd0f858
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
This commit is contained in:
@@ -390,6 +390,11 @@
|
||||
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
|
||||
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se7_2uart_sleep>;
|
||||
|
Reference in New Issue
Block a user