From 32a0054a706b04c6ab5042543fd7f0d4f03ff480 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Thu, 30 Nov 2023 16:42:32 -0800 Subject: [PATCH] dt-bindings: pci: Remove cesta-l1sub-timeout-ext-int property Remove the qcom,cesta-l1sub-timeout-ext-int property as its no longer required due to recent changes in the pcie driver using the change commit b53d4aa20ee7 ("pci: msm: Add support to enable PCIE CESTA clkreq config"). Initially this property was intended to be used to enable the BIT(3): PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA is enabled and the platform is not pineapple. Currently the pcie driver will by default set this BIT(3) when CESTA is enabled and the qcom,pcie-clkreq-offset property is present. Since the qcom,pcie-clkreq-offset property will not be present when CESTA is enabled on pineapple, pcie driver will not touch the PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register. Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when qcom,pcie-clkreq-offset property is present and CESTA is not present which is the case of pineapple platform when CESTA is enabled. And this case is also taken care of by the pcie driver without the need for qcom,pcie-clkreq-offset property. Below are the required cases that needs to be taken care of by the pcie driver. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | CESTA is enabled | BIT(0) set | BIT(3) set | platform | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | YES | need to set| need to set| non-pineapple | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | YES | set by | Not | pineapple | | | default | applicable | | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | NO | NO | NO | non-pineapple | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | NO | need to | Not | pineapple | | | unset | applicable | | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++. Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset property in the following way. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | CESTA is enabled | qcom,pcie-clkreq-offset | platform | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | YES | YES | non-pineapple | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | YES | NO | pineapple | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | NO | NO | non-pineapple | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | NO | YES | pineapple | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++. Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818 Signed-off-by: Prudhvi Yarlagadda --- bindings/pci/qcom,pcie-msm.yaml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/bindings/pci/qcom,pcie-msm.yaml b/bindings/pci/qcom,pcie-msm.yaml index 25d67cab..e9f46d98 100644 --- a/bindings/pci/qcom,pcie-msm.yaml +++ b/bindings/pci/qcom,pcie-msm.yaml @@ -398,11 +398,6 @@ properties: description: Offset from PCIe PHY base to PCIe CESTA CLKREQ register. $ref: /schemas/types.yaml#/definitions/uint32 - qcom,cesta-l1sub-timeout-ext-int: - description: Sets PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN bit in - PARF L1SUB_CESTA_CTRL register. - type: boolean - qcom,core-preset: description: Determines how aggressive the PCIe PHY equalization is for Gen3 cores. The following are recommended settings. @@ -555,9 +550,6 @@ required: - reset-names - dma-coherent -dependencies: - qcom,cesta-l1sub-timeout-ext-int: [ 'qcom,pcie-sm-seq', 'qcom,pcie-clkreq-offset' ] - allOf: - $ref: "/schemas/pci/pci-bus.yaml#" - if: