From 2f83057496058650d5c55156d85bac495c7af861 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 16 May 2024 17:43:30 +0800 Subject: [PATCH] ARM: dts: msm: add NT37801 dphy mode with bypass DDIC SPR support This change add NT37801 dphy mode with bypass DDIC SPR support. Change-Id: Ie34c339d0406867ecc934e3ce55a19bb580d88ca Signed-off-by: Jinfeng Gu --- ...nel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 125 ++++++++++++++++++ ...l-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 124 +++++++++++++++++ display/sun-sde-display-cdp.dtsi | 30 ++++- display/sun-sde-display-common.dtsi | 42 ++++++ display/sun-sde-display-mtp.dtsi | 30 ++++- 5 files changed, 349 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi new file mode 100644 index 00000000..260dc4a4 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_ddicspr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC and bypass DDIC SPR"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 39 01 00 00 00 00 07 b1 00 10 00 10 00 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi new file mode 100644 index 00000000..212ad8ec --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_video_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_ddicspr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC and bypass DDIC SPR"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 39 01 00 00 00 00 07 b1 00 10 00 10 00 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 7bd984d2..638c2fcb 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -139,6 +139,32 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -253,7 +279,9 @@ &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_qsync_cmd &dsi_nt37801_amoled_qsync_video - &dsi_nt37801_amoled_fhd_plus_cmd>; + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index b5717d38..3af6915a 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -15,6 +15,8 @@ #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -686,6 +688,46 @@ }; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_ext_bridge_1080p { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 4641076d..a9814173 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -127,6 +127,32 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -240,7 +266,9 @@ &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_qsync_cmd &dsi_nt37801_amoled_qsync_video - &dsi_nt37801_amoled_fhd_plus_cmd>; + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; };