From 8a7de6048ab5ac739a12751909203dd789f6966a Mon Sep 17 00:00:00 2001
From: Atul Pant <quic_atulpant@quicinc.com>
Date: Thu, 21 Nov 2024 23:54:44 +0530
Subject: [PATCH] ARM: dts: msm: kera: Add capacity and DPC properties

The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy model which in turn is used by EAS to take
placement decisions.

Change-Id: I6397ed3038d60fde457297fe3e015c2d5aaaa6a8
Signed-off-by: Atul Pant <quic_atulpant@quicinc.com>
---
 qcom/kera.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index 06d8bbc1..f06b7ded 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -101,6 +101,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_0>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <100>;
+			capacity-dmips-mhz = <1024>;
 			L2_0: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;
@@ -122,6 +124,8 @@
 			power-domains = <&CPU_PD1>;
 			power-domain-names = "psci";
 			next-level-cache = <&L2_0>;
+			dynamic-power-coefficient = <100>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -135,6 +139,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_2>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <100>;
+			capacity-dmips-mhz = <1024>;
 			L2_2: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;
@@ -152,6 +158,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_3>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <263>;
+			capacity-dmips-mhz = <1566>;
 			L2_3: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;
@@ -169,6 +177,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_4>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <263>;
+			capacity-dmips-mhz = <1566>;
 			L2_4: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;
@@ -186,6 +196,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_5>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <263>;
+			capacity-dmips-mhz = <1566>;
 			L2_5: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;
@@ -203,6 +215,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_6>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <263>;
+			capacity-dmips-mhz = <1566>;
 			L2_6: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;
@@ -220,6 +234,8 @@
 			power-domain-names = "psci";
 			next-level-cache = <&L2_7>;
 			#cooling-cells = <2>;
+			dynamic-power-coefficient = <289>;
+			capacity-dmips-mhz = <1607>;
 			L2_7: l2-cache {
 			      compatible = "cache";
 			      cache-level = <2>;