samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: Add compatible string for cc nodes monaco

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Add the compatible strings for clk controller nodes in monaco.

Change-Id: I2acb4c9520bb217711a75eb8e79fc75ba98e587f
Signed-off-by: Prerna Singh <quic_prersing@quicinc.com>
This commit is contained in:
Prerna Singh
2024-04-26 16:05:25 +05:30
parent 24e6ec54d7
commit 2f39297be8
1 changed files with 5 additions and 5 deletions
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10
qcom/monaco.dtsi
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@@ -1065,13 +1065,13 @@
};
rpmcc: qcom,rpmcc {
/* compatible = "qcom,rpmcc-monaco"; */
compatible = "qcom,rpmcc-monaco";
#clock-cells = <1>;
#reset-cells = <1>;
};
gcc: clock-controller@1410000 {
/* compatible = "qcom,monaco-gcc", "syscon"; */
compatible = "qcom,monaco-gcc", "syscon";
reg = <0x1400000 0x1e0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1085,7 +1085,7 @@
};
dispcc: clock-controller@5f00000 {
/* compatible = "qcom,monaco-dispcc", "syscon"; */
compatible = "qcom,monaco-dispcc", "syscon";
reg = <0x05f00000 0x20000>;
reg-names = "cc_base";
clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
@@ -1098,7 +1098,7 @@
};
gpucc: clock-controller@5990000 {
/* compatible = "qcom,monaco-gpucc", "syscon"; */
compatible = "qcom,monaco-gpucc", "syscon";
reg = <0x5990000 0x9000>;
reg-names = "cc_base";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
@@ -1122,7 +1122,7 @@
};
debugcc: clock-controller@0 {
/* compatible = "qcom,monaco-debugcc"; */
compatible = "qcom,monaco-debugcc";
qcom,gcc = <&gcc>;
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;