From 2e93118b13741367febf5ddbbb6feae4ca093489 Mon Sep 17 00:00:00 2001
From: Keval Kulkarni <quic_kevalbha@quicinc.com>
Date: Tue, 27 Aug 2024 17:24:22 +0530
Subject: [PATCH] ARM: dts: msm: Add ipcc node for sdxkova

Add ipcc node for sdxkova to enable inter processor
communication controller.

Adjust reg format for tz-log node.

Change-Id: I5519f5b8bfc02b2c85c1654a2f39c4ec61fdee9f
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
---
 qcom/sdxkova.dtsi | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi
index 0e1add5a..d294d268 100644
--- a/qcom/sdxkova.dtsi
+++ b/qcom/sdxkova.dtsi
@@ -9,7 +9,7 @@
 /{
 	qcom_tzlog: tz-log@14680720 {
 		compatible = "qcom,tz-log";
-		reg = <0x14680720 0x3000>;
+		reg = <0x0 0x14680720 0x0 0x3000>;
 		qcom,hyplog-enabled;
 		hyplog-address-offset = <0x410>;
 		hyplog-size-offset = <0x414>;
@@ -357,6 +357,15 @@
 		compatible = "qcom,cpufreq-hw-epss-debug";
 		qcom,freq-hw-domain = <&cpufreq_hw 0>;
 	};
+
+	ipcc_mproc: qcom,ipcc@408000 {
+		compatible = "qcom,ipcc";
+		reg = <0x0 0x408000 0x0 0x1000>;
+		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
 };
 
 &gcc {