From 2e5af8d1100a7adbf4fc6f4ef5b82e8c6d15093b Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 3 Oct 2023 12:18:48 -0700 Subject: [PATCH] ARM: dts: msm: sun: Add node for gic interrupt router Add node for gic interrupt router for sun SoC. Change-Id: Id5690f286f89f6f15051477cf06ad8a390c69c7a Signed-off-by: Melody Olvera --- qcom/sun.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index daaacaf5..4e475428 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -34,7 +34,7 @@ chosen: chosen { - bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 pcie_ports=compat mem-offline.bypass_send_msg=1 cpuidle.off=1"; + bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat mem-offline.bypass_send_msg=1 cpuidle.off=1"; stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; @@ -809,6 +809,14 @@ cap-based-alloc-and-pwr-collapse; }; + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + /* keep a few m cores in class0 only to avoid wakeup of l cores */ + qcom,gic-class0-cpus = <0 1>; + /* keep other cores in class1 */ + qcom,gic-class1-cpus = <2 3 4 5 6 7>; + }; + qcom,secure-buffer { compatible = "qcom,secure-buffer"; qcom,vmid-cp-camera-preview-ro;