From 2c8658563ea6ca61d95cdafcd24a362845da2490 Mon Sep 17 00:00:00 2001
From: Sampurna Bolloju <quic_sampboll@quicinc.com>
Date: Mon, 11 Nov 2024 12:04:28 +0530
Subject: [PATCH] ARM: dts: msm: add display node in trustedvm platform

This change adds display node in trustedvm platform on
Kera target.

Change-Id: Ibe2c60bcb34bdedee75f7b8fa163a8aacb204562
Signed-off-by: Sampurna Bolloju <quic_sampboll@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
---
 display/trustedvm-kera-sde-display.dtsi |  2 +-
 display/trustedvm-kera-sde.dtsi         | 37 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi
index e6420a52..8ec7d0f1 100644
--- a/display/trustedvm-kera-sde-display.dtsi
+++ b/display/trustedvm-kera-sde-display.dtsi
@@ -24,5 +24,5 @@
 };
 
 &mdss_mdp {
-	connectors = <&sde_dsi &sde_dsi1>;
+	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>;
 };
diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi
index 9b88fd38..3740746b 100644
--- a/display/trustedvm-kera-sde.dtsi
+++ b/display/trustedvm-kera-sde.dtsi
@@ -8,9 +8,46 @@
 #include "kera-sde-common.dtsi"
 
 &soc {
+	/* dummy display clock provider */
+	clock_cpucc: qcom,cpucc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "cpucc_clocks";
+		#clock-cells = <1>;
+	};
+
+	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+		compatible = "qcom,smmu_sde_unsec";
+		iommus = <&apps_smmu 0x804 0x2>;
+		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		qcom,iommu-faults = "non-fatal";
+		dma-coherent;
+	};
 };
 
 &mdss_mdp {
+	reg = <0x0ae00000 0x93800>,
+	      <0x0aeb0000 0x2008>,
+	      <0x0af80000 0x7000>,
+	      <0x0ae44000 0x02c>;
+
+	reg-names = "mdp_phys",
+		"vbif_phys",
+		"regdma_phys",
+		"sid_phys";
+
+	qcom,sde-vm-exclude-reg-names = "sid_phys";
+	qcom,sde-hw-version = <0xC0040000>;
+
+	clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
+		<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
+	clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
+			"core_clk", "vsync_clk", "lut_clk";
+	qcom,sde-trusted-vm-env;
 };
 
 &mdss_dsi0 {