diff --git a/qcom/eva/Kbuild b/qcom/eva/Kbuild new file mode 100644 index 00000000..1aebce4e --- /dev/null +++ b/qcom/eva/Kbuild @@ -0,0 +1,25 @@ +ifneq ($(CONFIG_ARCH_QTI_VM), y) + +ifeq ($(CONFIG_ARCH_SUN), y) +dtbo-y += sun-eva.dtbo +dtbo-y += sun-eva-v2.dtbo +endif + +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += tuna-eva.dtbo +endif + +ifeq ($(CONFIG_ARCH_PINEAPPLE), y) +dtbo-y += pineapple-eva.dtbo +endif + +ifeq ($(CONFIG_ARCH_KALAMA), y) +dtbo-y += trustedvm-kalama-eva-mtp.dtbo \ + trustedvm-kalama-eva-qrd.dtbo +endif + +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/qcom/eva/Makefile b/qcom/eva/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/qcom/eva/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/qcom/eva/bindings/msm-eva-bus.yaml b/qcom/eva/bindings/msm-eva-bus.yaml new file mode 100644 index 00000000..8689a577 --- /dev/null +++ b/qcom/eva/bindings/msm-eva-bus.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm-eva-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM CVP BUS + +description: | + Second level nodes - Buses + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,msm-cvp,bus + label: + description: an arbitrary name + qcom,bus-master: + description: + an integer descriptor of the bus master. Refer to arch/arm/\ + boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of + acceptable masters + qcom,bus-slave: + description: + an integer descriptor of the bus slave. Refer to arch/arm/\ + boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of + acceptable slaves + qcom,bus-governor: + description: + governor to use when scaling bus, generally any commonly + found devfreq governor might be used. In addition to those governors, + the custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also + acceptable values. + In the absence of this property the "performance" governor is used. + qcom,bus-rage-kbps: + description: + an array of two items () that indicate the + minimum and maximum acceptable votes for the bus. + In the absence of this property <0 INT_MAX> is used. + qcom,ubwc-10bit: + description: + UBWC 10 bit content has different bus requirements, + this tag will be used to pick the appropriate bus as per the session + profile as shown below in example. + +required: + - compatible + - label + - qcom,bus-master + - qcom,bus-slave + +examples: + - | + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = ; + + /* FIXME: LLCC Info */ + /* cache-slice-names = "vidsc0", "vidsc1"; */ + /* cache-slices = <&llcc 2>, <&llcc 3>; */ + + /* Supply */ + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "gcc_video_axi1", "cvp_clk"; + clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, + <&clock_gcc GCC_VIDEO_AXI1_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", + "cvp_clk"; + + qcom,clock-configs = <0x0 0x0 0x1>; + qcom,allowed-clock-rates = <403000000 520000000 + 549000000 666000000 800000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-cvp,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = <&apps_smmu 0x2120 0x400>; + qcom,iommu-dma = "disabled"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x4b000000 0xe0000000>; + }; + + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; diff --git a/qcom/eva/bindings/msm-eva-cb.yaml b/qcom/eva/bindings/msm-eva-cb.yaml new file mode 100644 index 00000000..a1d8c9b1 --- /dev/null +++ b/qcom/eva/bindings/msm-eva-cb.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm-eva-cb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM CVP CB + +description: | + Second level nodes - Context Banks + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,msm-cvp,context-bank + iommus: + description: + A phandle parsed by smmu driver. Number of entries will vary + + label: + description: + string describing iommu domain usage. + buffer-types: + description: + bitmap of buffer types that can be mapped into the current IOMMU domain. + Buffer types are defined as the following + input = 0x1 + output = 0x2 + output2 = 0x4 + extradata input = 0x8 + extradata output = 0x10 + extradata output2 = 0x20 + internal scratch = 0x40 + internal scratch1 = 0x80 + internal scratch2 = 0x100 + internal persist = 0x200 + internal persist1 = 0x400 + internal cmd queue = 0x800 + virtual-addr-pool: + description: + offset and length of virtual address pool. + qcom,fw-context-bank: + description: + bool indicating firmware context bank. + qcom,secure-context-bank: + description: + bool indicating secure context bank. + +required: + - compatible + - iommus + +examples: + - | + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = ; + + /* FIXME: LLCC Info */ + /* cache-slice-names = "vidsc0", "vidsc1"; */ + /* cache-slices = <&llcc 2>, <&llcc 3>; */ + + /* Supply */ + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "gcc_video_axi1", "cvp_clk"; + clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, + <&clock_gcc GCC_VIDEO_AXI1_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", + "cvp_clk"; + + qcom,clock-configs = <0x0 0x0 0x1>; + qcom,allowed-clock-rates = <403000000 520000000 + 549000000 666000000 800000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-cvp,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = <&apps_smmu 0x2120 0x400>; + qcom,iommu-dma = "disabled"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x4b000000 0xe0000000>; + }; + + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; diff --git a/qcom/eva/bindings/msm-eva-heap.yaml b/qcom/eva/bindings/msm-eva-heap.yaml new file mode 100644 index 00000000..8f047a25 --- /dev/null +++ b/qcom/eva/bindings/msm-eva-heap.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm-eva-heap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM CVP HEAP + +description: | + Second level nodes - Memory Heaps + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,msm-vidc,mem-cdsp + memory-region: + description: + phandle to the memory heap/region. + +required: + - compatible + - memory-region + +examples: + - | + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = ; + + /* FIXME: LLCC Info */ + /* cache-slice-names = "vidsc0", "vidsc1"; */ + /* cache-slices = <&llcc 2>, <&llcc 3>; */ + + /* Supply */ + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "gcc_video_axi1", "cvp_clk"; + clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, + <&clock_gcc GCC_VIDEO_AXI1_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", + "cvp_clk"; + + qcom,clock-configs = <0x0 0x0 0x1>; + qcom,allowed-clock-rates = <403000000 520000000 + 549000000 666000000 800000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-cvp,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = <&apps_smmu 0x2120 0x400>; + qcom,iommu-dma = "disabled"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x4b000000 0xe0000000>; + }; + + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; diff --git a/qcom/eva/bindings/msm-eva.yaml b/qcom/eva/bindings/msm-eva.yaml new file mode 100644 index 00000000..ae42ea6b --- /dev/null +++ b/qcom/eva/bindings/msm-eva.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm-eva.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM CVP + +description: | + Root level node - cvp + +properties: + # A dictionary of DT properties for this binding schema + compatible: + oneOf: + - items: + - enum: + - qcom,msm-cvp + - qcom,sun-cvp + - qcom,pineapple-cvp + - qcom,kalama-cvp + - qcom,waipio-cvp + - qcom,lahaina-cvp + - qcom,kona-cvp + + reg: + description: + offset and length of the CSR register set for the device. + interrupts: + description: + should contain the cvp interrupt. + qcom,reg-presets: + description: + list of offset-value pairs for registers to be written. + The offsets are from the base offset specified in 'reg'. This is mainly + used for QoS, VBIF, etc. presets for video. + qcom,qdss-presets: + description: + list of physical address and memory allocation size pairs. + when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware + messages will be written to QDSS memory. + ‘*-supply’: + description: + A phandle pointing to the appropriate regulator. Number of + regulators vary across targets. + clock-names: + description: + an array of clocks that the driver is supposed to be + manipulating. The clocks names here correspond to the clock names + used in clk_get(). + qcom,clock-configs: + description: + an array of bitmaps of clocks' configurations. The index of the + bitmap corresponds to the clock at the same index in qcom,clock-names. + The bitmaps describes the actions that the device needs to take + regarding the clock (i.e. scale it based on load). + The bitmap is defined as scalable = 0x1 + (if the driver should vary the clock's frequency based on load) + qcom,allowed-clock-rates: + description: + an array of supported clock rates by the chipset. + qcom,use-non-secure-pil: + description: + A bool indicating which type of pil to use to load the fw. + qcom,fw-bias: + description: + The address at which cvp fw is loaded (manually). + +required: + - compatible + +examples: + - | + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = ; + + /* FIXME: LLCC Info */ + /* cache-slice-names = "vidsc0", "vidsc1"; */ + /* cache-slices = <&llcc 2>, <&llcc 3>; */ + + /* Supply */ + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "gcc_video_axi1", "cvp_clk"; + clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, + <&clock_gcc GCC_VIDEO_AXI1_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", + "cvp_clk"; + + qcom,clock-configs = <0x0 0x0 0x1>; + qcom,allowed-clock-rates = <403000000 520000000 + 549000000 666000000 800000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-cvp,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = <&apps_smmu 0x2120 0x400>; + qcom,iommu-dma = "disabled"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x4b000000 0xe0000000>; + }; + + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; diff --git a/qcom/eva/pineapple-eva.dts b/qcom/eva/pineapple-eva.dts new file mode 100644 index 00000000..4a51c91a --- /dev/null +++ b/qcom/eva/pineapple-eva.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include "pineapple-eva.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. pineapple v1,v2 SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <557 0x20000>; + qcom,board-id = <0 0>, <15 0>, <8 0>, <11 0>, <1 0>; +}; diff --git a/qcom/eva/pineapple-eva.dtsi b/qcom/eva/pineapple-eva.dtsi new file mode 100644 index 00000000..9317f2c3 --- /dev/null +++ b/qcom/eva/pineapple-eva.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,pineapple-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = , ; + + /* LLCC Cache */ + cache-slice-names = "cvp"; + + /* Supply */ + cvp-supply = <&video_cc_mvs1c_gdsc>; + cvp-core-supply = <&video_cc_mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", + "video_cc_mvs1_clk_src"; + clock-ids = ; + clocks = <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_SLEEP_CLK>, + <&videocc VIDEO_CC_MVS1C_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK_SRC>; + qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", + "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + + qcom,clock-configs = <0x0 0x0 0x0 0x0 0x1>; + qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>; + + resets = <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_XO_CLK_ARES>, + <&videocc VIDEO_CC_MVS1C_CLK_ARES>; + reset-names = "cvp_axi_reset", "cvp_xo_reset","cvp_core_reset"; + reset-power-status = <0x0 0x1 0x0>; + + qcom,reg-presets = <0xB0088 0x0>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,gcc-reg = <0x110000 0x40000>; + + pas-id = <26>; + memory-region = <&cvp_mem>; + + /* UC region mapping */ + ipclite_mappings = <0xFE500000 0x100000 0x82600000>; + /* DEVICE mapping */ + aon_timer_mappings = <0xFFA00000 0x1000 0xc220000>; + /* DEVICE mapping */ + hwmutex_mappings = <0xFFB00000 0x2000 0x1f4a000>; + /* DEVICE mapping */ + aon_mappings = <0xFF80F000 0x1000 0x0ABE0000>; + + /* CVP Firmware ELF image name */ + cvp,firmware-name = "evass"; + + /* Buses */ + cvp_cnoc { + compatible = "qcom,msm-cvp,bus"; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; + interconnect-names = "eva-cfg"; + }; + + cvp_bus_ddr { + compatible = "qcom,msm-cvp,bus"; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 6533000>; + interconnects = <&mmss_noc MASTER_VIDEO_PROC &mc_virt SLAVE_EBI1>; + interconnect-names = "eva-ddr"; + }; + + /* MMUs */ + /* Camera cb is used to get secure camera buffer IPA */ + cvp_camera_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_camera"; + buffer-types = <0xfff>; + qti,smmu-proxy-cb-id = ; + }; + + non_secure_cb_group: cvp_non_secure_cb_group { + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + qcom,iommu-faults = "non-fatal"; + }; + + cvp_non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = + <&apps_smmu 0x1920 0x0000>; + buffer-types = <0xfff>; + dma-coherent; + qcom,iommu-group = <&non_secure_cb_group>; + }; + + + cvp_secure_nonpixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_nonpixel"; + iommus = + <&apps_smmu 0x1924 0x0000>; + buffer-types = <0x741>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; + qcom,iommu-vmid = <0xB>; + }; + + cvp_secure_pixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_pixel"; + iommus = + <&apps_smmu 0x1923 0x0000>; + buffer-types = <0x106>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-vmid = <0xA>; + }; + + cvp_dsp_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_dsp"; + iommus = + <&apps_smmu 0x1920 0x0000>; + buffer-types = <0xfff>; + qcom,iommu-group = <&non_secure_cb_group>; + }; + + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_eva_mem>; + }; + }; +}; diff --git a/qcom/eva/sun-eva-v2.dts b/qcom/eva/sun-eva-v2.dts new file mode 100644 index 00000000..75e6b2a6 --- /dev/null +++ b/qcom/eva/sun-eva-v2.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include "sun-eva-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun v2 SoC"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x20000>, <639 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>; + qcom,board-id = <0 0>, <15 0>, <8 0>, <11 0>, <1 0>; +}; diff --git a/qcom/eva/sun-eva-v2.dtsi b/qcom/eva/sun-eva-v2.dtsi new file mode 100644 index 00000000..ea98b6bb --- /dev/null +++ b/qcom/eva/sun-eva-v2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-eva.dtsi" + +&msm_cvp { + qcom,allowed-clock-rates = <350000000 400000000 450000000 500000000 550000000>; + soc_ver = <0x20000>; +}; + diff --git a/qcom/eva/sun-eva.dts b/qcom/eva/sun-eva.dts new file mode 100644 index 00000000..c7e3b8c4 --- /dev/null +++ b/qcom/eva/sun-eva.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include "sun-eva.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sun v1 SoC"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <639 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>; + qcom,board-id = <0 0>, <15 0>, <8 0>, <11 0>, <1 0>; +}; diff --git a/qcom/eva/sun-eva.dtsi b/qcom/eva/sun-eva.dtsi new file mode 100644 index 00000000..5b4a1cc8 --- /dev/null +++ b/qcom/eva/sun-eva.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,sun-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = , ; + + /* LLCC Cache */ + cache-slice-names = "cvpfw", "cvp"; + + /* Supply */ + cvp-supply = <&eva_cc_mvs0c_gdsc>; + cvp-core-supply = <&eva_cc_mvs0_gdsc>; + + /* Clocks */ + clock-names = "cvp_axi_clock", "core_axi_clock", "sleep_clk", "cvp_freerun_clk", "core_freerun_clk", + "cvp_clk", "core_clk","eva_cc_mvs0_clk_src"; + clock-ids = ; + clocks = <&gcc GCC_EVA_AXI0C_CLK>, + <&gcc GCC_EVA_AXI0_CLK>, + <&evacc EVA_CC_SLEEP_CLK>, + <&evacc EVA_CC_MVS0C_FREERUN_CLK>, + <&evacc EVA_CC_MVS0_FREERUN_CLK>, + <&evacc EVA_CC_MVS0C_CLK>, + <&evacc EVA_CC_MVS0_CLK>, + <&evacc EVA_CC_MVS0_CLK_SRC>; + qcom,proxy-clock-names = "cvp_axi_clock", "core_axi_clock", "sleep_clk", "cvp_freerun_clk", "core_freerun_clk", + "cvp_clk", "core_clk", "eva_cc_mvs0_clk_src"; + + qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1>; + qcom,allowed-clock-rates = <350000000 400000000 450000000 500000000 550000000>; + + /*To be added - GCC_EVA CLK_ARES and GCC_EVA_AXI0C_CLK_ARES*/ + resets = <&evacc EVA_CC_MVS0C_CLK_ARES>; + reset-names = "cvp_core_reset"; + reset-power-status = <0x0>; + + qcom,reg-presets = <0xB0088 0x0>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,gcc-reg = <0x110000 0x90000>; + + pas-id = <26>; + soc_ver = <0x10000>; + memory-region = <&cvp_mem>; + + /* UC region mapping */ + ipclite_mappings = <0xFE500000 0x100000 0x82600000>; + /* DEVICE mapping */ + aon_timer_mappings = <0xFFA00000 0x1000 0xc220000>; + /* DEVICE mapping */ + hwmutex_mappings = <0xFFB00000 0x2000 0x1f4a000>; + /* DEVICE mapping */ + aon_mappings = <0xFF80F000 0x1000 0x0ABE0000>; + + /* CVP Firmware ELF image name */ + cvp,firmware-name = "evass"; + + /* Buses */ + cvp_cnoc { + compatible = "qcom,msm-cvp,bus"; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_EVA_CFG>; + interconnect-names = "eva-cfg"; + }; + + cvp_bus_ddr { + compatible = "qcom,msm-cvp,bus"; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 6533000>; + interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>; + interconnect-names = "eva-ddr"; + }; + + /* MMUs */ + /* Camera cb is used to get secure camera buffer IPA */ + cvp_camera_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_camera"; + buffer-types = <0xfff>; + qti,smmu-proxy-cb-id = ; + }; + + non_secure_cb_group: cvp_non_secure_cb_group { + qcom,iommu-faults = "non-fatal"; + }; + + cvp_iommu_region_partition: cvp_iommu_region_partition { + /* These IOVA regions are unique per context bank */ + iommu-addresses = <&cvp_non_secure_cb 0x0 0x4b000000>, <&cvp_non_secure_cb 0xdb000000 0x25000000>, + <&cvp_dsp_cb 0x0 0x4b000000>, <&cvp_dsp_cb 0xdb000000 0x25000000>, + <&cvp_secure_nonpixel_cb 0x0 0x01000000>, <&cvp_secure_nonpixel_cb 0x26800000 0xd9800000>, + <&cvp_secure_pixel_cb 0x0 0x26800000>, <&cvp_secure_pixel_cb 0x4b000000 0xb5000000>; + }; + + cvp_non_secure_cb: cvp_non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = + <&apps_smmu 0x1920 0x0020>; + buffer-types = <0xfff>; + dma-coherent; + qcom,iommu-group = <&non_secure_cb_group>; + memory-region = <&cvp_iommu_region_partition>; + }; + + + cvp_secure_nonpixel_cb: cvp_secure_nonpixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_nonpixel"; + iommus = + <&apps_smmu 0x1924 0x0020>; + buffer-types = <0x741>; + qcom,iommu-faults = "non-fatal"; + memory-region = <&cvp_iommu_region_partition>; + qcom,iommu-vmid = <0xB>; + }; + + cvp_secure_pixel_cb: cvp_secure_pixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_pixel"; + iommus = + <&apps_smmu 0x1923 0x0000>; + buffer-types = <0x106>; + qcom,iommu-faults = "non-fatal"; + memory-region = <&cvp_iommu_region_partition>; + qcom,iommu-vmid = <0xA>; + }; + + cvp_dsp_cb: cvp_dsp_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_dsp"; + iommus = + <&apps_smmu 0x1920 0x0020>; + buffer-types = <0xfff>; + qcom,iommu-group = <&non_secure_cb_group>; + memory-region = <&cvp_iommu_region_partition>; + }; + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_eva_mem>; + }; + }; +}; diff --git a/qcom/eva/trustedvm-kalama-eva-mtp.dts b/qcom/eva/trustedvm-kalama-eva-mtp.dts new file mode 100644 index 00000000..f25445d6 --- /dev/null +++ b/qcom/eva/trustedvm-kalama-eva-mtp.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include "trustedvm-kalama-eva.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama MTP"; + compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp"; + qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,board-id = <0x10008 0>; +}; diff --git a/qcom/eva/trustedvm-kalama-eva-qrd.dts b/qcom/eva/trustedvm-kalama-eva-qrd.dts new file mode 100644 index 00000000..5dda7b68 --- /dev/null +++ b/qcom/eva/trustedvm-kalama-eva-qrd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include "trustedvm-kalama-eva.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama QRD"; + compatible = "qcom,kalama-qrd", "qcom,kalama", "qcom,qrd"; + qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/eva/trustedvm-kalama-eva.dtsi b/qcom/eva/trustedvm-kalama-eva.dtsi new file mode 100644 index 00000000..f2c3a9ea --- /dev/null +++ b/qcom/eva/trustedvm-kalama-eva.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,kalama-cvp-tvm"; + status = "ok"; + }; +}; diff --git a/qcom/eva/tuna-eva.dts b/qcom/eva/tuna-eva.dts new file mode 100644 index 00000000..2d1850df --- /dev/null +++ b/qcom/eva/tuna-eva.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include +#include "tuna-eva.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>, <15 0>; +}; diff --git a/qcom/eva/tuna-eva.dtsi b/qcom/eva/tuna-eva.dtsi new file mode 100644 index 00000000..354e26c5 --- /dev/null +++ b/qcom/eva/tuna-eva.dtsi @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,tuna-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = , ; + + /* Supply */ + cvp-supply = <&eva_cc_mvs0c_gdsc>; + cvp-core-supply = <&eva_cc_mvs0_gdsc>; + + /* Clocks */ + clock-names = "cvp_axi_clock", "core_axi_clock", "sleep_clk", "cvp_freerun_clk", + "core_freerun_clk", "cvp_clk", "core_clk","eva_cc_mvs0_clk_src"; + clock-ids = ; + clocks = <&gcc GCC_EVA_AXI0C_CLK>, + <&gcc GCC_EVA_AXI0_CLK>, + <&evacc EVA_CC_SLEEP_CLK>, + <&evacc EVA_CC_MVS0C_FREERUN_CLK>, + <&evacc EVA_CC_MVS0_FREERUN_CLK>, + <&evacc EVA_CC_MVS0C_CLK>, + <&evacc EVA_CC_MVS0_CLK>, + <&evacc EVA_CC_MVS0_CLK_SRC>; + qcom,proxy-clock-names = "cvp_axi_clock", "core_axi_clock", "sleep_clk", + "cvp_freerun_clk", "core_freerun_clk", "cvp_clk", + "core_clk", "eva_cc_mvs0_clk_src"; + + qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1>; + qcom,allowed-clock-rates = <280000000 350000000 450000000 500000000 550000000>; + + /*To be added - GCC_EVA CLK_ARES and GCC_EVA_AXI0C_CLK_ARES*/ + resets = <&evacc EVA_CC_MVS0C_CLK_ARES>; + reset-names = "cvp_core_reset"; + reset-power-status = <0x0>; + + qcom,reg-presets = <0xB0088 0x0>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,gcc-reg = <0x110000 0x90000>; + + pas-id = <26>; + soc_ver = <0x10000>; + memory-region = <&cvp_mem>; + + /* UC region mapping */ + ipclite_mappings = <0xFE500000 0x100000 0x82600000>; + /* DEVICE mapping */ + aon_timer_mappings = <0xFFA00000 0x1000 0xc220000>; + /* DEVICE mapping */ + hwmutex_mappings = <0xFFB00000 0x2000 0x1f4a000>; + /* DEVICE mapping */ + aon_mappings = <0xFF80F000 0x1000 0x0ABE0000>; + + /* CVP Firmware ELF image name */ + cvp,firmware-name = "evass"; + + /* Buses */ + cvp_cnoc { + compatible = "qcom,msm-cvp,bus"; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_EVA_CFG>; + interconnect-names = "eva-cfg"; + }; + + cvp_bus_ddr { + compatible = "qcom,msm-cvp,bus"; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 6533000>; + interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>; + interconnect-names = "eva-ddr"; + }; + + /* MMUs */ + /* Camera cb is used to get secure camera buffer IPA */ + cvp_camera_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_camera"; + buffer-types = <0xfff>; + qti,smmu-proxy-cb-id = ; + }; + + non_secure_cb_group: cvp_non_secure_cb_group { + qcom,iommu-faults = "non-fatal"; + }; + + cvp_iommu_region_partition: cvp_iommu_region_partition { + /* These IOVA regions are unique per context bank */ + iommu-addresses = <&cvp_non_secure_cb 0x0 0x4b000000>, + <&cvp_non_secure_cb 0xdb000000 0x25000000>, + <&cvp_dsp_cb 0x0 0x4b000000>, <&cvp_dsp_cb 0xdb000000 0x25000000>, + <&cvp_secure_nonpixel_cb 0x0 0x01000000>, + <&cvp_secure_nonpixel_cb 0x26800000 0xd9800000>, + <&cvp_secure_pixel_cb 0x0 0x26800000>, + <&cvp_secure_pixel_cb 0x4b000000 0xb5000000>; + }; + + cvp_non_secure_cb: cvp_non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = + <&apps_smmu 0x1920 0x0020>; + buffer-types = <0xfff>; + dma-coherent; + qcom,iommu-group = <&non_secure_cb_group>; + memory-region = <&cvp_iommu_region_partition>; + }; + + + cvp_secure_nonpixel_cb: cvp_secure_nonpixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_nonpixel"; + iommus = + <&apps_smmu 0x1924 0x0020>; + buffer-types = <0x741>; + qcom,iommu-faults = "non-fatal"; + memory-region = <&cvp_iommu_region_partition>; + qcom,iommu-vmid = <0xB>; + }; + + cvp_secure_pixel_cb: cvp_secure_pixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_pixel"; + iommus = + <&apps_smmu 0x1923 0x0000>; + buffer-types = <0x106>; + qcom,iommu-faults = "non-fatal"; + memory-region = <&cvp_iommu_region_partition>; + qcom,iommu-vmid = <0xA>; + }; + + cvp_dsp_cb: cvp_dsp_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_dsp"; + iommus = + <&apps_smmu 0x1920 0x0020>; + buffer-types = <0xfff>; + qcom,iommu-group = <&non_secure_cb_group>; + memory-region = <&cvp_iommu_region_partition>; + }; + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_eva_mem>; + }; + }; +};