From 5d47bd95def275eca1c8d4ca51ea7da17c97a729 Mon Sep 17 00:00:00 2001
From: Namita Nair <quic_namibala@quicinc.com>
Date: Wed, 17 Jan 2024 22:24:23 -0800
Subject: [PATCH] ARM: dts: msm: Add upstream compatible iommu-addresses
 property

Upstream Linux kernel has added a new devicetree property
"iommu-addresses", to replace "qcom,iommu-dma-addr-pool".
The new property defines the address range the device
cannot use, in contrast to the older property which
defines the address range the device can use.

Change-Id: I8fc13e27593193af7be5ca1bcc03c04a25f36c91
CRs-Fixed: 3724373
---
 sun-kiwi-cnss-v8.dtsi  | 11 +++++++----
 sun-kiwi-cnss.dtsi     | 11 +++++++----
 sun-peach-cnss-v8.dtsi | 11 +++++++----
 sun-peach-cnss.dtsi    | 11 +++++++----
 4 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/sun-kiwi-cnss-v8.dtsi b/sun-kiwi-cnss-v8.dtsi
index f70de1e6..7af34953 100644
--- a/sun-kiwi-cnss-v8.dtsi
+++ b/sun-kiwi-cnss-v8.dtsi
@@ -145,20 +145,23 @@
 };
 
 &pcie0_rp {
-	#address-cells = <5>;
-	#size-cells = <0>;
 
 	cnss_pci0: cnss_pci0 {
 		reg = <0 0 0 0 0>;
 		qcom,iommu-group = <&cnss_pci_iommu_group0>;
-		memory-region = <&cnss_wlan_mem>;
+		memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
+			/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
+			iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
+					  <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
+		};
+
 		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
 			qcom,iommu-msi-size = <0x1000>;
-			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
 			qcom,iommu-geometry = <0xa0000000 0x10010000>;
 			qcom,iommu-dma = "fastmap";
 			qcom,iommu-pagetable = "coherent";
diff --git a/sun-kiwi-cnss.dtsi b/sun-kiwi-cnss.dtsi
index 10fb204e..07bf898f 100644
--- a/sun-kiwi-cnss.dtsi
+++ b/sun-kiwi-cnss.dtsi
@@ -147,20 +147,23 @@
 };
 
 &pcie0_rp {
-	#address-cells = <5>;
-	#size-cells = <0>;
 
 	cnss_pci0: cnss_pci0 {
 		reg = <0 0 0 0 0>;
 		qcom,iommu-group = <&cnss_pci_iommu_group0>;
-		memory-region = <&cnss_wlan_mem>;
+		memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
+			/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
+			iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
+					  <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
+			};
+
 		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
 			qcom,iommu-msi-size = <0x1000>;
-			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
 			qcom,iommu-geometry = <0xa0000000 0x10010000>;
 			qcom,iommu-dma = "fastmap";
 			qcom,iommu-pagetable = "coherent";
diff --git a/sun-peach-cnss-v8.dtsi b/sun-peach-cnss-v8.dtsi
index da71a3a9..a7fabba0 100644
--- a/sun-peach-cnss-v8.dtsi
+++ b/sun-peach-cnss-v8.dtsi
@@ -146,20 +146,23 @@
 };
 
 &pcie0_rp {
-	#address-cells = <5>;
-	#size-cells = <0>;
 
 	cnss_pci0: cnss_pci0 {
 		reg = <0 0 0 0 0>;
 		qcom,iommu-group = <&cnss_pci_iommu_group0>;
-		memory-region = <&cnss_wlan_mem>;
+		memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
+			/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
+			iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
+					  <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
+		};
+
 		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
 			qcom,iommu-msi-size = <0x1000>;
-			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
 			qcom,iommu-geometry = <0xa0000000 0x10010000>;
 			qcom,iommu-dma = "fastmap";
 			qcom,iommu-pagetable = "coherent";
diff --git a/sun-peach-cnss.dtsi b/sun-peach-cnss.dtsi
index 4f432360..7a1010e0 100644
--- a/sun-peach-cnss.dtsi
+++ b/sun-peach-cnss.dtsi
@@ -139,20 +139,23 @@
 };
 
 &pcie0_rp {
-	#address-cells = <5>;
-	#size-cells = <0>;
 
 	cnss_pci0: cnss_pci0 {
 		reg = <0 0 0 0 0>;
 		qcom,iommu-group = <&cnss_pci_iommu_group0>;
-		memory-region = <&cnss_wlan_mem>;
+		memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
+			/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
+			iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
+					  <&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
+		};
+
 		cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
 			qcom,iommu-msi-size = <0x1000>;
-			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
 			qcom,iommu-geometry = <0xa0000000 0x10010000>;
 			qcom,iommu-dma = "fastmap";
 			qcom,iommu-pagetable = "coherent";