From 202e2bbd82ce03f58435ca5025365444935b0706 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 23 Jul 2024 16:36:11 +0530 Subject: [PATCH 1/5] ARM: dts: msm: Add support for graphics clock controller on KERA Add support for GPU clock controller and move corresponding gdsc's from dummy to real on Kera platform. While at it, add the clocks property to camera and display gdscs. Change-Id: If3061a7603035e799e7548f0e2a93b7ded0e3005 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d39d3fdf..5d016158 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1845,8 +1845,17 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,kera-gpucc", "syscon"; + reg = <0x3d90000 0xa000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + clock-names = "bi_tcxo", + "gpll0_out_main", + "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -3080,26 +3089,32 @@ #include "ipcc-test-no-slpi.dtsi" &cam_cc_ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_ofe_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_tfe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_tfe_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_tfe_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; interconnect-names = "mmnoc"; parent-supply = <&VDD_CX_LEVEL>; @@ -3107,11 +3122,13 @@ }; &disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; @@ -3161,13 +3178,17 @@ }; &gpu_cc_cx_gdsc { - compatible = "regulator-fixed"; reg = <0x3d99110 0x4>; + parent-supply = <&VDD_CX_LEVEL>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &gpu_cc_gx_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_GFX_LEVEL>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; From 0a06675a87e07787db28fdd9c8c363ed1fa723f2 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 23 Sep 2024 16:36:06 +0530 Subject: [PATCH 2/5] ARM: dts: msm: Add support for RPMHCC and DEBUGCC on Kera platform Add support for rpmh and debug clock controller nodes on Kera platform. While at it, keep rpmhcc node as dummy for KERA rumi platform. Change-Id: Ic11513d45bbc9b3f172a411f854a2348af4bfb94 Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 6 ++++++ qcom/kera.dtsi | 52 +++++++++++++++++++++++++++++++++++++++------ 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 2b8a1e8c..8e1cfa60 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -158,3 +158,9 @@ &APSS_OFF { status = "disabled"; }; + +&rpmhcc { + compatible = "fixed-clock"; + clock-output-names = "rpmh_clocks"; + clock-frequency = <19200000>; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 5d016158..05843866 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -636,6 +636,11 @@ qcom,llcc-bcm-name = "SH5"; }; + + rpmhcc: clock-controller { + compatible = "qcom,tuna-rpmh-clk"; + #clock-cells = <1>; + }; }; }; @@ -1732,13 +1737,6 @@ }; }; - rpmhcc: clock-controller { - compatible = "fixed-clock"; - clock-output-names = "rpmh_clocks"; - clock-frequency = <19200000>; - #clock-cells = <1>; - }; - cambistmclkcc: clock-controller@1760000 { compatible = "qcom,tuna-cambistmclkcc", "syscon"; reg = <0x1760000 0x6000>; @@ -3083,6 +3081,46 @@ qcom,count-unit = <0x10000>; qcom,target-dev = <&qcom_ddr_dcvs_hw>; }; + + apsscc: syscon@17a80000 { + compatible = "syscon"; + reg = <0x17a80000 0x21000>; + }; + + mccc: syscon@240ba000 { + compatible = "syscon"; + reg = <0x240ba000 0x800>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,kera-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,cambistmclkcc = <&cambistmclkcc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,tcsrcc = <&tcsrcc>; + qcom,videocc = <&videocc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&cambistmclkcc 0>, + <&camcc 0>, + <&dispcc 0>, + <&gcc 0>, + <&gpucc 0>, + <&tcsrcc 0>, + <&videocc 0>; + clock-names = "xo_clk_src", + "cambistmclkcc", + "camcc", + "dispcc", + "gcc", + "gpucc", + "tcsrcc", + "videocc"; + #clock-cells = <1>; + }; }; #include "tuna-gdsc.dtsi" From 8d7f1a22a8fd8063710eba9b2740abfa42bf8071 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 25 Sep 2024 12:26:45 +0530 Subject: [PATCH 3/5] ARM: dts: msm: Update videocc clock node as GenPD provider on Kera Mark videocc clock node as GenPD provider and disable the video GDSC regulator nodes for kera platform. While at it, keep the gdsc's as it is on kera-rumi platform. Change-Id: I4a41aacbaa7d144f72db48b9af3a336a92ef95aa Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 8e1cfa60..76d7f98c 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -164,3 +164,11 @@ clock-output-names = "rpmh_clocks"; clock-frequency = <19200000>; }; + +&video_cc_mvs0_gdsc { + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 05843866..4018f135 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1872,6 +1872,7 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_CX_LEVEL>; vdd_mxc-supply = <&VDD_MX_LEVEL>; + vdd_mm_mxc_voter-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, @@ -1882,6 +1883,7 @@ "iface"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; qti,smmu-proxy { @@ -3233,14 +3235,12 @@ &video_cc_mvs0_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0c_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &reserved_memory { From f42efc56a8806138a4bd7d7ff7664a56b0d404c9 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 12 Dec 2024 15:59:26 +0530 Subject: [PATCH 4/5] dt-bindings: clock: qcom: add the DISPCC binding for kera Add DISPCC clock binding for kera platform. Change-Id: I3fd06bb26f5dd2b98653c0be22a2ff742de485ac Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,dispcc-sm8x50.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 0d15434e..4c5564e3 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -32,6 +32,7 @@ properties: - qcom,sun-dispcc - qcom,tuna-dispcc - qcom,tuna-dispcc-v1 + - qcom,kera-dispcc clocks: items: From fc794cac57689fd2829a815b5da54c9a3086e179 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 25 Sep 2024 16:36:41 +0530 Subject: [PATCH 5/5] ARM: dts: msm: Update dispcc clock node as GenPD provider on Kera Mark dispcc clock node as GenPD provider and disable the display GDSC regulator nodes for kera platform. While at it, keep the gdsc's as it is on kera-rumi platform and update the compatible to align with freq plan. Change-Id: If01f876b3d160cf5c1cfe6be13e3e4b42f62cfa6 Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 5 ++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 76d7f98c..e05aabe2 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -172,3 +172,11 @@ &video_cc_mvs0c_gdsc { status = "ok"; }; + +&disp_cc_mdss_core_gdsc { + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 4018f135..68308926 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1798,7 +1798,7 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,tuna-dispcc", "syscon"; + compatible = "qcom,kera-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_CX_LEVEL>; @@ -1814,6 +1814,7 @@ qcom,disp_crm-crmc = <&dispcc_crm>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; gcc: clock-controller@100000 { @@ -3164,13 +3165,11 @@ &disp_cc_mdss_core_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gcc_pcie_0_gdsc {