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Merge "arm64: dts: qcom: Add interconnect nodes for SDX75"

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QCTECMDR Service
2024-07-16 05:36:32 -07:00
committed by Gerrit - the friendly Code Review server
parent 46d907af1c 696610ee27
commit 26c2d81f5a
1 changed files with 52 additions and 0 deletions
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52
qcom/sdx75.dtsi
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@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h> #include <dt-bindings/clock/qcom,sdx75-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sdx75.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
@@ -203,6 +205,19 @@
}; };
}; };
clk_virt: interconnect-0 {
compatible = "qcom,sdx75-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&rpmhcc RPMH_QPIC_CLK>;
};
mc_virt: interconnect-1 {
compatible = "qcom,sdx75-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x80000000 0x0 0x0>; reg = <0x0 0x80000000 0x0 0x0>;
@@ -434,6 +449,9 @@
clock-names = "m-ahb", clock-names = "m-ahb",
"s-ahb"; "s-ahb";
iommus = <&apps_smmu 0xe3 0x0>; iommus = <&apps_smmu 0xe3 0x0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
@@ -444,6 +462,12 @@
reg = <0x0 0x00984000 0x0 0x4000>; reg = <0x0 0x00984000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se"; clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&qupv3_se1_2uart_active>; pinctrl-0 = <&qupv3_se1_2uart_active>;
pinctrl-1 = <&qupv3_se1_2uart_sleep>; pinctrl-1 = <&qupv3_se1_2uart_sleep>;
@@ -453,6 +477,20 @@
}; };
}; };
system_noc: interconnect@1640000 {
compatible = "qcom,sdx75-system-noc";
reg = <0x0 0x01640000 0x0 0x4b400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie_anoc: interconnect@16c0000 {
compatible = "qcom,sdx75-pcie-anoc";
reg = <0x0 0x016c0000 0x0 0x14200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
tcsr_mutex: hwlock@1f40000 { tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex"; compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>; reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -733,6 +771,20 @@
#freq-domain-cells = <1>; #freq-domain-cells = <1>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
dc_noc: interconnect@190e0000 {
compatible = "qcom,sdx75-dc-noc";
reg = <0x0 0x190e0000 0x0 0x8200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@19100000 {
compatible = "qcom,sdx75-gem-noc";
reg = <0x0 0x19100000 0x0 0x34080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
}; };
timer { timer {