From 267917e9cdadf925828e9e778421f8d4232829cc Mon Sep 17 00:00:00 2001
From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Date: Thu, 4 Apr 2024 16:44:01 -0700
Subject: [PATCH] Revert "ARM: dts: msm: Mark GCC clock node as GenPD provider"

This reverts commit c0a6035e47a819e581763724033a65c635618249.

Facing issue where PCIe PHY GDSC is getting turned off when system
suspend is happening. So reverting this change till we find a fix.

Change-Id: Ic4bb32c126e0247688d31e276a9a3f29c373b167
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Signed-off-by: Bruce Levy <quic_blevy@quicinc.com>
---
 qcom/sun.dtsi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index ca84fe38..aeb871e5 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -1773,7 +1773,6 @@
 			      "ufs_phy_tx_symbol_0_clk",
 			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 		#clock-cells = <1>;
-		#power-domain-cells = <1>;
 		#reset-cells = <1>;
 	};
 
@@ -2005,7 +2004,6 @@
 		qcom,no-status-check-on-disable;
 		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
 		qcom,support-cfg-gdscr;
-		status = "disabled";
 	};
 
 	gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
@@ -2017,7 +2015,6 @@
 		qcom,no-status-check-on-disable;
 		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
 		qcom,support-cfg-gdscr;
-		status = "disabled";
 	};
 
 	gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {