From 934446a6ace7e3abcaf69070f037096cac677407 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Mon, 26 Aug 2024 17:50:50 +0530 Subject: [PATCH] ARM: dts: msm: Add support for Tuna GPU Add the devicetree files for the GPU on Tuna devices. Change-Id: I3d651d6e665c2fe40dc4e7bced2ea6bd9dbdd185 Signed-off-by: SIVA MULLATI --- Kbuild | 4 + bindings/adreno.txt | 3 + gpu/tuna-gpu-pwrlevels.dtsi | 115 ++++++++++++++++++++++++ gpu/tuna-gpu.dts | 25 ++++++ gpu/tuna-gpu.dtsi | 173 ++++++++++++++++++++++++++++++++++++ 5 files changed, 320 insertions(+) create mode 100644 gpu/tuna-gpu-pwrlevels.dtsi create mode 100644 gpu/tuna-gpu.dts create mode 100644 gpu/tuna-gpu.dtsi diff --git a/Kbuild b/Kbuild index da849afb..eef19472 100644 --- a/Kbuild +++ b/Kbuild @@ -8,6 +8,10 @@ dtbo-y += gpu/sun-gpu.dtbo \ gpu/sun-v2-gpu.dtbo endif +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += gpu/tuna-gpu.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/bindings/adreno.txt b/bindings/adreno.txt index dd426a95..caaaf7c5 100644 --- a/bindings/adreno.txt +++ b/bindings/adreno.txt @@ -16,6 +16,7 @@ Required properties: Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target. Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target. Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target. + Must include "qcom,adreno-gpu-gen8-6-0" for Tuna target. - reg: Specifies the list of register regions for the device. - reg-names: Resource names used for the register regions specified in reg. @@ -183,6 +184,8 @@ Optional Properties: 1: UBWC 1.0 2: UBWC 2.0 3: UBWC 3.0 + 4: UBWC 4.0 + 5: UBWC 5.0 Based on the ubwc mode, program the appropriate bit into certain protected registers and also pass to the user as a property. diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi new file mode 100644 index 00000000..278d4fca --- /dev/null +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&msm_gpu { + /* Power levels */ + qcom,initial-pwrlevel = <8>; + + qcom,gpu-pwrlevels { + compatible="qcom,gpu-pwrlevels"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <9>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <7>; + qcom,bus-min = <4>; + qcom,bus-max = <8>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <7>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + }; +}; diff --git a/gpu/tuna-gpu.dts b/gpu/tuna-gpu.dts new file mode 100644 index 00000000..0c480c2d --- /dev/null +++ b/gpu/tuna-gpu.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "tuna-gpu.dtsi" +#include "tuna-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna"; + compatible = "qcom,tuna"; + qcom,msm-id = <0x28f 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi new file mode 100644 index 00000000..0034b508 --- /dev/null +++ b/gpu/tuna-gpu.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +/* External feature codes */ +#define FC_UNKNOWN 0x0 + +/* Pcodes */ +#define PCODE_UNKNOWN 0 + +#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) + +&msm_gpu { + compatible = "qcom,adreno-gpu-gen8-6-0", "qcom,kgsl-3d0"; + status = "ok"; + reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>, + <0x3d61000 0x3000>, <0x3d9e000 0x2000>, + <0x10900000 0x80000>, <0x10048000 0x8000>, + <0x10b05000 0x1000>; + reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", + "qdss_gfx", "qdss_etr", "qdss_tmc"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb"; + + qcom,gpu-model = "Adreno825"; + + qcom,chipid = <0x44030000>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <5>; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-cnoc = + <0>, /* Off */ + <100>; /* On */ + + qcom,bus-table-ddr = + , /* index=0 */ + , /* LowSVS index=1 */ + , /* LowSVS index=2 */ + , /* LowSVS index=3 */ + , /* SVS index=4 */ + , /* SVS index=5 */ + , /* SVS index=6 */ + , /* NOM index=7 */ + , /* NOM index=8 */ + , /* TURBO index=9 */ + , /* TURBO_L1 index=10 */ + ; /* TURBO_L3 index=11 */ + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; +}; + +&soc { + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x3da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_lpac: gfx3d_lpac { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x1 0x000>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x000>; + qcom,iommu-dma = "disabled"; + }; + }; + + gmu: qcom,gmu@3d37000 { + compatible = "qcom,gen8-gmu"; + + reg = <0x3d37000 0x68000>, + <0x3d40000 0x10000>; + + reg-names = "gmu", "gmu_ao_blk_dec0"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gx_clkctl_gx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "ahb_clk", "hub_clk"; + + qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + <650000000 RPMH_REGULATOR_LEVEL_SVS>; + qcom,gmu-perf-ddr-bw = ; + + iommus = <&kgsl_smmu 0x5 0x000>; + qcom,iommu-dma = "disabled"; + + qcom,ipc-core = <0x00400000 0x140000>; + + qcom,qmp = <&aoss_qmp>; + }; +};