Merge "ARM: dts: msm: Add RSC and PDC devices for SM6150"
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@@ -4,6 +4,7 @@
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*/
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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/ {
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model = "Qualcomm Technologies, Inc. SM6150";
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model = "Qualcomm Technologies, Inc. SM6150";
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@@ -403,6 +404,52 @@
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method = "smc";
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method = "smc";
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};
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x18200000 0x10000>,
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<0x18210000 0x10000>,
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<0x18220000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,drv-count = <3>;
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0xd00>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 1>,
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<FAST_PATH_TCS 0>;
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};
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};
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};
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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qcom,drv-count = <1>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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disp_rsc_drv0: drv@0 {
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qcom,drv-id = <0>;
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qcom,tcs-offset = <0x1c00>;
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channel@0 {
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qcom,tcs-config = <SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<ACTIVE_TCS 2>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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};
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};
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intc: interrupt-controller@17a00000 {
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#interrupt-cells = <3>;
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@@ -415,6 +462,15 @@
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interrupt-parent = <&intc>;
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interrupt-parent = <&intc>;
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm6150-pdc", "qcom,pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
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qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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timer {
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timer {
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compatible = "arm,armv8-timer";
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compatible = "arm,armv8-timer";
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interrupts = <1 1 0xf08>,
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interrupts = <1 1 0xf08>,
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