From 54a9c53389eba5ac7e6f2e0fa06807d4a11993cc Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Fri, 27 Dec 2024 17:23:23 +0530 Subject: [PATCH 01/26] ARM: dts: msm: Enable idle states for tuna VMs Enable idle states devices for virtual CPU to enter LPMs when idle. Change-Id: I0e03ea5ac0263a385a1ee4e79f16070826d88320 Signed-off-by: Sneh Mankad --- qcom/tuna-oemvm.dtsi | 18 ++++++++++++++---- qcom/tuna-vm.dtsi | 18 ++++++++++++++---- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 2601180b..fe25e5ba 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -40,14 +40,24 @@ }; idle-states { - CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; }; - CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + CLUSTER_PWR_DWN: d4 { /* C4+D4 */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "l3-pc"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x40000044>; + local-timer-stop; }; }; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 93fd4c0c..e8cb6658 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -42,14 +42,24 @@ }; idle-states { - CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; }; - CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + CLUSTER_PWR_DWN: d4 { /* C4+D4 */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "l3-pc"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x40000044>; + local-timer-stop; }; }; From a59ba91bd28b72e8a9d014b910757047c111912e Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Fri, 3 Jan 2025 14:55:00 +0530 Subject: [PATCH 02/26] ARM: dts: msm: Update S1B/S2B/S3B min voltages for tuna Reduce S1B/S2B/S3B min voltages for tuna based on the latest HW recommendations for the rbsc voltage reductions. Change-Id: Id741ce1a66908e6fa2debb5f1867d9e079ee0f33 Signed-off-by: Kavya Nunna --- qcom/tuna-regulators.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index 8071f35e..7c8b670f 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -13,9 +13,9 @@ S1B: pmxr2230_s1: vreg-pmxr2230-s1 { regulator-name = "pmxr2230_s1"; qcom,set = ; - regulator-min-microvolt = <1856000>; + regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2104000>; - qcom,init-voltage = <1856000>; + qcom,init-voltage = <1840000>; }; }; @@ -26,9 +26,9 @@ S2B: pmxr2230_s2: vreg-pmxr2230-s2 { regulator-name = "pmxr2230_s2"; qcom,set = ; - regulator-min-microvolt = <1256000>; + regulator-min-microvolt = <1240000>; regulator-max-microvolt = <1408000>; - qcom,init-voltage = <1256000>; + qcom,init-voltage = <1240000>; }; }; @@ -39,7 +39,7 @@ S3B: pmxr2230_s3: vreg-pmxr2230-s3 { regulator-name = "pmxr2230_s3"; qcom,set = ; - regulator-min-microvolt = <880000>; + regulator-min-microvolt = <864000>; regulator-max-microvolt = <1040000>; qcom,init-voltage = <952000>; }; From f3fae6c2e9bdfd75b2d446012d98e8a099684e33 Mon Sep 17 00:00:00 2001 From: songchai Date: Tue, 7 Jan 2025 02:32:28 -0800 Subject: [PATCH 03/26] ARM: dts: msm: add dcc registers into dt for tuna add dcc registers into dt for tuna. Change-Id: Iba0d519b794ff6337c4045c00626fe7c1fc511a9 Signed-off-by: songchai --- qcom/tuna-debug.dtsi | 1327 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1326 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-debug.dtsi b/qcom/tuna-debug.dtsi index 1baaf8dd..3867c38a 100644 --- a/qcom/tuna-debug.dtsi +++ b/qcom/tuna-debug.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -26,6 +26,1331 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x0>; + + link_list_0 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,ap-qad-override; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_1 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,ap-qad-override; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_2 { + qcom,curr-link-list = <3>; + qcom,data-sink = "sram"; + qcom,ap-qad-override; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; mem_dump { From 60dfb0d6f6e63a98da34cbd02a7b4e05e53cd65c Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 21 Oct 2024 18:59:52 +0530 Subject: [PATCH 04/26] dt-bindings: clock: qcom: Add dispcc_mx bindings on sun Add display mx clock controller bindings on sun device. Change-Id: Ie8c87b285bdf5278585bfee42b0eeff70397ce9d Signed-off-by: Jagadeesh Kona --- bindings/clock/qcom,dispcc-sm8x50.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 4c5564e3..2cb638bd 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -33,6 +33,7 @@ properties: - qcom,tuna-dispcc - qcom,tuna-dispcc-v1 - qcom,kera-dispcc + - qcom,sun-dispcc_mx clocks: items: From c56398560bdccf064351d5b0c73c0c31b3d98564 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 8 Oct 2024 20:19:05 +0530 Subject: [PATCH 05/26] ARM: dts: msm: Add support for dispcc_mx clock controller node Add dispcc_mx clock controller node as a child node of dispcc node to register dispcc mx clocks on sun platform. Change-Id: I1ade67a4f2c09135800b3d5603c8e18a86450de7 Signed-off-by: Jagadeesh Kona --- qcom/sun.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 355323b1..614654ca 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1791,6 +1791,15 @@ #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; + + dispcc_mx: clock-controller@af02000 { + compatible = "qcom,sun-dispcc_mx"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk"; + #clock-cells = <1>; + }; }; evacc: clock-controller@abf0000 { From 07b61ddce66a88d06f21b0cd5874d409e38247d4 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Mon, 13 Jan 2025 16:08:23 +0530 Subject: [PATCH 06/26] ARM: dts: msm: Add support for guest-cpus Add support for offlining CPUs during VM load for Parrot. Change-Id: Id5dad4d40375942a2f8ad671345390ecfc7a3926 Signed-off-by: Swetha Chikkaboraiah --- bindings/arm/msm/qcom,gh-secure-vm-loader.yaml | 6 ++++++ qcom/parrot.dtsi | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,gh-secure-vm-loader.yaml b/bindings/arm/msm/qcom,gh-secure-vm-loader.yaml index 6e56bc68..0ca07836 100644 --- a/bindings/arm/msm/qcom,gh-secure-vm-loader.yaml +++ b/bindings/arm/msm/qcom,gh-secure-vm-loader.yaml @@ -26,6 +26,10 @@ properties: $ref: '/schemas/types.yaml#/definitions/uint32' description: Peripheral authentication ID of the subsystem. + qcom,guest-cpus: + $ref: '/schemas/types.yaml#/definitions/string' + description: Guest CPUs. + qcom,firmware-name: $ref: '/schemas/types.yaml#/definitions/string' description: Virtual machine name. @@ -42,6 +46,7 @@ required: - compatible - qcom,pas-id - qcom,vmid + - qcom,guest-cpus - qcom,firmware-name - memory-region - virtio-backends @@ -54,6 +59,7 @@ examples: compatible = "qcom,gh-secure-vm-loader"; qcom,pas-id = <28>; qcom,vmid = <45>; + qcom,guest-cpus = "5-6"; qcom,firmware-name = "trustedvm"; memory-region = <&trust_ui_vm_mem>; virtio-backends = <&trust_ui_vm_virt_be0>; diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index c0f541fa..1c9b60ba 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2066,6 +2066,7 @@ compatible = "qcom,gh-secure-vm-loader"; qcom,pas-id = <28>; qcom,vmid = <45>; + qcom,guest-cpus = "5-6"; qcom,firmware-name = "trustedvm"; memory-region = <&trust_ui_vm_mem>; virtio-backends = <&trust_ui_vm_virt_be0>; From acfa9db83b6524823e7614dffb935ec889f49fc8 Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Mon, 2 Dec 2024 16:41:43 +0530 Subject: [PATCH 07/26] ARM: dts: msm: Enable PCIe1 for kera This change adds PCIe1 node for kera. Change-Id: I5c5b0b2a1a1654b187b7bcfe031602f6786efb4f Signed-off-by: Sushrut Shree Trivedi --- qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts | 4 + qcom/kera-pcie.dtsi | 298 +++++++++++++++++++++ qcom/kera-pinctrl.dtsi | 55 ++++ qcom/kera.dtsi | 13 +- 4 files changed, 369 insertions(+), 1 deletion(-) create mode 100644 qcom/kera-pcie.dtsi diff --git a/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts b/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts index aaca3064..059ec876 100644 --- a/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts +++ b/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts @@ -16,3 +16,7 @@ qcom,msm-id = <686 0x10000>, <659 0x10000>; qcom,board-id = <0x50001 0>; }; + +&pcie1 { + status = "ok"; +}; diff --git a/qcom/kera-pcie.dtsi b/qcom/kera-pcie.dtsi new file mode 100644 index 00000000..0763fc8d --- /dev/null +++ b/qcom/kera-pcie.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + device_type = "pci"; + + reg = <0x1c08000 0x3000>, + <0x1c0e000 0x2000>, + <0x44000000 0xf1d>, + <0x44000F20 0xa8>, + <0x44001000 0x1000>, + <0x44100000 0x100000>, + <0x1c0b000 0x1000>; + + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x44200000 0x44200000 0x0 0x100000>, + <0x02000000 0x0 0x44300000 0x44300000 0x0 0x3d00000>; + + interrupts = ; + + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */ + + pinctrl-names = "default", "sleep"; + perst-gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + pinctrl-1 = <&pcie1_clkreq_sleep + &pcie1_perst_default + &pcie1_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>; + vreg-1p2-supply = <&L4B>; + vreg-0p9-supply = <&L2B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MX_LEVEL>; + qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>; + qcom,vreg-0p9-voltage-level = <880000 880000 91950>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&tcsrcc TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>, + <&pcie_1_pipe_clk>; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_rate_change_clk", + "gcc_ddrss_pcie_sf_qtb_clk", + "pcie_aggre_noc_axi_clk", + "gcc_cnoc_pcie_sf_axi_clk", + "pcie_cfg_noc_pcie_anoc_ahb_clk", + "pcie_pipe_clk_mux", "pcie_1_pipe_div2_clk", + "pcie_pipe_clk_ext_src"; + qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, + <100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "pcie_1_core_reset", "pcie_1_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1400>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + qcom,aux-clk-freq = <20>; + qcom,drv-l1ss-timeout-us = <5000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,ep-latency = <10>; + + qcom,pcie-phy-ver = <112>; + qcom,phy-status-offset = <0x0214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x0240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x62 0x0 + 0x00d0 0x02 0x0 + 0x0060 0xf8 0x0 + 0x0064 0x01 0x0 + 0x0000 0x93 0x0 + 0x0004 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0a 0x0 + 0x0120 0x42 0x0 + 0x0080 0x04 0x0 + 0x0084 0x0d 0x0 + 0x0020 0x0a 0x0 + 0x0024 0x1a 0x0 + 0x0088 0x41 0x0 + 0x0028 0x34 0x0 + 0x0090 0xab 0x0 + 0x0094 0xaa 0x0 + 0x0098 0x01 0x0 + 0x0030 0x55 0x0 + 0x0034 0x55 0x0 + 0x0038 0x01 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x1600 0x00 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x06f4 0x27 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x0368 0x17 0x0 + 0x0370 0x2e 0x0 + 0x1424 0x00 0x0 + 0x1428 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + status = "disabled"; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17110040 { + compatible = "qcom,pci-msi"; + reg = <0x17110040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi index 3eef2cd5..9c61646a 100644 --- a/qcom/kera-pinctrl.dtsi +++ b/qcom/kera-pinctrl.dtsi @@ -1979,4 +1979,59 @@ drive-strength = <2>; }; }; + + pcie1 { + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio52"; + function = "pcie1_clk_req_n"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_clkreq_sleep: pcie1_clkreq_sleep { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; }; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index cef15bc2..f2630b3f 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -69,7 +69,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops page_poison=on cgroup.memory=nokmem,nosocket"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops page_poison=on cgroup.memory=nokmem,nosocket"; stdout-path = "serial0:115200n8"; }; @@ -502,11 +502,21 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + ranges; #redistributor-regions = <1>; redistributor-stride = <0x0 0x40000>; reg = <0x17100000 0x10000>, /* GICD */ <0x17180000 0x200000>; /* GICR * 8 */ interrupts = ; + + #address-cells = <1>; + #size-cells = <1>; + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x17140000 0x20000>; + }; }; qcom,hdcp { @@ -3313,6 +3323,7 @@ #include "kera-pmic-overlay.dtsi" #include "kera-usb.dtsi" #include "kera-qupv3.dtsi" +#include "kera-pcie.dtsi" #include "kera-thermal.dtsi" #include "kera-walt.dtsi" #include "msm-rdbg.dtsi" From 8b80d83de748583803c7e7b400ad2846cef684e0 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 17 Jan 2025 07:58:03 +0530 Subject: [PATCH 08/26] ARM: dts: msm: Add pcie and display voter devices for KERA Add pcie and display CRM voters for kera. This will allow interconnect providers to target their votes on CESTA DRV for meeting cesta client bandwidth constraints. Change-Id: I16198f67ca4a8f7b2d3704044704b78bd267e2f3 Signed-off-by: Raviteja Laggyshetty --- qcom/kera.dtsi | 127 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 117 insertions(+), 10 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index cbb612cc..4b6f0496 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1982,18 +1982,93 @@ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, <&cpufreq_hw 2>; }; + pcie_crm_hw_0_bcm_voter: bcm_voter@0 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "pcie_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <5>; + }; + + disp_crm_hw_0_bcm_voter: bcm_voter@1 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_1_bcm_voter: bcm_voter@2 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <1>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_2_bcm_voter: bcm_voter@3 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <2>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_3_bcm_voter: bcm_voter@4 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <3>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_4_bcm_voter: bcm_voter@5 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <4>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_5_bcm_voter: bcm_voter@6 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <5>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_sw_0_bcm_voter: bcm_voter@7 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-sw-client; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <1>; + }; + clk_virt: interconnect@0 { compatible = "qcom,kera-clk_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>; }; mc_virt: interconnect@1 { compatible = "qcom,kera-mc_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; config_noc: interconnect@1600000 { @@ -2024,8 +2099,10 @@ compatible = "qcom,kera-pcie_anoc"; reg = <0x16c0000 0x11400>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>; clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; }; @@ -2052,16 +2129,46 @@ compatible = "qcom,kera-mmss_noc"; reg = <0x1780000 0x7d800>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; gem_noc: interconnect@24100000 { compatible = "qcom,kera-gem_noc"; reg = <0x24100000 0x163080>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; nsp_noc: interconnect@320c0000 { From 8edd785e2fa89e54812888fde3316b5a2c2a8270 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 6 Jan 2025 11:45:00 +0530 Subject: [PATCH 09/26] ARM: dts: qcom: Enable UFS MCQ on Kera platforms Enable the UFS MCQ feature on the Kera platforms. Change-Id: I3e6349010c442666bef9a7b7c24dcd22e9d717b4 Signed-off-by: Manish Pandey --- qcom/kera.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index f2630b3f..d28a21ca 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -2579,8 +2579,10 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x18000>; - reg-names = "ufs_mem", "ice"; + <0x1d88000 0x18000>, + <0x1da5000 0x2000>, + <0x1da4000 0x10>; + reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -2588,6 +2590,10 @@ qcom,ice-use-hwkm; + qcom,prime-mask = <0x80>; + qcom,silver-mask = <0x07>; + qcom,esi-affinity-mask = <6 5 5 7 7 7 6 6>; + lanes-per-direction = <2>; clock-names = "core_clk", @@ -2628,7 +2634,9 @@ depends-on-supply = <&apps_smmu>; iommus = <&apps_smmu 0x60 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; + msi-parent = <&gic_its 0x60>; + qcom,iommu-msi-size = <0x1000>; memory-region = <&ufshc_dma_resv>; shared-ice-cfg = <&ice_cfg>; dma-coherent; From 4b3299d7261ad35cb6af9375859416fb892d55c3 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Thu, 9 Jan 2025 14:12:52 +0530 Subject: [PATCH 10/26] ARM: dts: msm: Update qfprom node in kera for speed bin and gaming fuse Define speed bin and gaming fuse in qfprom node for kera gpu. Change-Id: Ic0dd6e1c5c3c753cccc44aa25c3c56e340c675fb Signed-off-by: Kaushal Sanadhya --- qcom/kera.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index cbb612cc..6be8e967 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1649,6 +1649,16 @@ feat_conf6: feat_conf6@0118 { reg = <0x0118 0x4>; }; + + gpu_speed_bin: gpu_speed_bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + + gpu_gaming_bin: gpu_gaming_bin@14b { + reg = <0x14b 0x1>; + bits = <7 1>; + }; }; qfprom_sys: qfprom@0 { From 4c35a7013ad47d05520e38f088fde410cdd32665 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Thu, 16 Jan 2025 11:03:30 +0530 Subject: [PATCH 11/26] ARM: dts: msm: Update cpucp regions for tuna Update cpucp regions for tuna, inline with v2. This removes pdp region and reduces cpucp_scandump region to 1.5MB. Change-Id: I571d8012545c7c547f0115d86e10183964fe7d8f Signed-off-by: Vijayanand Jitta --- qcom/tuna-reserved-memory.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/tuna-reserved-memory.dtsi b/qcom/tuna-reserved-memory.dtsi index 3ee901c5..55f93d2e 100644 --- a/qcom/tuna-reserved-memory.dtsi +++ b/qcom/tuna-reserved-memory.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &reserved_memory { @@ -18,9 +18,9 @@ reg = <0x0 0x80e00000 0x0 0x400000>; }; - cpucp_pdp_mem: cpucp_region@81200000 { + cpucp_mem: cpucp_region@81200000 { no-map; - reg = <0x0 0x81200000 0x0 0x200000>; + reg = <0x0 0x81200000 0x0 0x100000>; }; /* @@ -77,9 +77,9 @@ no-map; }; - cpucp_scandump_mem: cpucp_scandump_region@82000000 { + cpucp_scandump_mem: cpucp_scandump_region@82200000 { no-map; - reg = <0x0 0x82000000 0x0 0x380000>; + reg = <0x0 0x82200000 0x0 0x180000>; }; adsp_mhi_mem: adsp_mhi_region@82380000 { From 61235b8386d36a67f23aa3351588b62086e1b165 Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Mon, 6 Jan 2025 13:17:08 +0530 Subject: [PATCH 12/26] ARM: dts: qcom: Enable qup3 for mtp Enable qup3 for MTP for Kera. Enable wcd_usbss on MTP. Change-Id: I84a9747a14cdc8931f37edf5910f318b23ba1d19 Signed-off-by: Ravulapati Vishnu Vardhan Rao --- qcom/kera-mtp.dtsi | 1 + qcom/kera.dtsi | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/kera-mtp.dtsi b/qcom/kera-mtp.dtsi index 21de6d5f..66d3495a 100644 --- a/qcom/kera-mtp.dtsi +++ b/qcom/kera-mtp.dtsi @@ -34,6 +34,7 @@ interrupt-names = "usb_wcd"; nvmem-cells = <&usb_mode>; nvmem-cell-names = "usb_mode"; + status = "ok"; }; &qupv3_se8_spi { diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index c7f5ccda..248d87f0 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -3505,8 +3505,9 @@ }; &qupv3_se3_i2c { - status = "disabled"; + status = "ok"; wcd_usbss: wcd939x_i2c@e { + status = "disabled"; compatible = "qcom,wcd939x-i2c"; reg = <0xe>; vdd-usb-cp-supply = <&L7B>; From e0754fd7fb9d71634c9ae4a6fb3f65b1b3bcc38a Mon Sep 17 00:00:00 2001 From: songchai Date: Thu, 16 Jan 2025 22:31:03 -0800 Subject: [PATCH 13/26] ARM: dts: msm: add ddr-lpi qmi for tuna add ddr-lpi qmi for tuna. Change-Id: I920f472840195bc6636732eb511abb2e2fbc21c4 Signed-off-by: songchai --- qcom/tuna-coresight.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index 64ad37c5..c99fba1f 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &soc { @@ -2184,12 +2184,24 @@ trace-name = "tracenoc-ddr-lpi"; out-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; tpdm_ddr_lpi_out_funnel_aoss: endpoint { remote-endpoint = <&funnel_aoss_in_tpdm_ddr_lpi>; }; }; + + port@1 { + reg = <1>; + ddr_lpi_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_ddr_lpi>; + }; + }; }; }; @@ -4325,6 +4337,14 @@ <&lpass_audio_out_qmi>; }; }; + + port@5 { + reg = <5>; + qmi_in_ddr_lpi: endpoint { + remote-endpoint = + <&ddr_lpi_out_qmi>; + }; + }; }; }; From c301ec7df25b6d98fdcedc2ee25f01d0ba5171ce Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 20 Jan 2025 15:53:51 +0530 Subject: [PATCH 14/26] ARM: dts: msm: add goodix touch driver device nodes for tuna Add goodix touch driver device nodes on tuna for CDP. Change-Id: I6f4bbfdf8848bf823e6937404c354dce6814e80f Signed-off-by: Abhinav Saurabh --- qcom/tuna-cdp.dtsi | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index d608afe7..483484ee 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -39,6 +39,33 @@ qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; }; + + goodix-berlin@5d { + compatible = "goodix,gt9916"; + reg = <0x5d>; + interrupt-parent = <&tlmm>; + interrupts = <176 0x2008>; + goodix,reset-gpio = <&tlmm 189 0x00>; + goodix,irq-gpio = <&tlmm 176 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_i2c.bin"; + goodix,config-name = "goodix_cfg_group_i2c.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + invert_xy; + avdd-supply = <&L22B>; + iovdd-supply = <&L1D>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + goodix,touch-type = "primary"; + goodix,qts_en; + }; }; &ufsphy_mem { From e2226e200c02d98aaf56ef298789ccab598450d0 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 21 Jan 2025 16:29:43 +0530 Subject: [PATCH 15/26] ARM: dts: msm: Fix the protected clocks for gcc Fix the clock handle entries in the protected clocks for gcc on Kera. Change-Id: I0f7f633b0961fa2dda952fb9b53824aa45968595 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 2b94cf9f..552ffc37 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1866,12 +1866,12 @@ "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; - protected-clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_AUX_CLK_SRC>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, - <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_1_PIPE_DIV2_CLK_SRC>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + protected-clocks = , , + , , + , , + , , + , , + , ; #clock-cells = <1>; #reset-cells = <1>; }; From 425ccfd29a497e4ffa6e68335fc080c5398c9f19 Mon Sep 17 00:00:00 2001 From: Prem Sai Grandhi Date: Fri, 17 Jan 2025 17:43:09 +0530 Subject: [PATCH 16/26] ARM: dts: msm: SLC SCID Heuristics support for tuna Enables HEURISTICS SCID for tuna. Change-Id: Ie88346943ba30dbcdab502b56d20614a3f296118 Signed-off-by: Prem Sai Grandhi --- qcom/tuna.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 9f46b027..97175054 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -666,6 +666,15 @@ clocks = <&aoss_qmp QDSS_CLK>; clock-names = "qdss_clk"; }; + + scid_heuristics { + compatible = "qcom,scid-heuristics"; + qcom,heuristics-scid = <32>; + /* Need to update different value for V2 device */ + qcom,freq-threshold-idx = <10>, <13>, <19>, <19>, <21>; + qcom,frequency-threshold-residency = <1500>, <1500>, <1500>, <1500>, <1500>; + qcom,scid-heuristics-enabled; + }; }; gic-interrupt-router { From 4b87355d272a08f0dd4cbb4e53d19555f3f6b95d Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Fri, 17 Jan 2025 11:15:41 +0530 Subject: [PATCH 17/26] ARM: dts: msm: Add fps entry for kera Add fps entry for kera. Change-Id: I04ff258f3d36345f9c618a3745253371a9e49420 Signed-off-by: Sanskar Omar --- qcom/kera.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0336cdbc..c759ae2b 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1671,6 +1671,10 @@ reg = <0x0118 0x4>; }; + feat_conf18: feat_conf18@0148 { + reg = <0x0148 0x4>; + }; + gpu_speed_bin: gpu_speed_bin@138 { reg = <0x138 0x2>; bits = <0 9>; @@ -1684,8 +1688,8 @@ qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; - nvmem-cells = <&feat_conf6>; - nvmem-cell-names = "feat_conf6"; + nvmem-cells = <&feat_conf6>, <&feat_conf18>; + nvmem-cell-names = "feat_conf6", "feat_conf18"; }; wpss_pas: remoteproc-wpss@97000000 { From fdf5b9c6bd4bb0db5abee2274bb8a97f6f44fc7d Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Thu, 23 Jan 2025 09:47:20 +0530 Subject: [PATCH 18/26] ARM: dts: qcom: Update gpu mitigation level and BCL threshold for tuna Update gpu mitigation level for tuna and BCL threshold based on latest recommendation. Change-Id: I51e9e60d6439439ce76fa4cfbdf7e4d909ef727e Signed-off-by: Priyansh Jain --- qcom/tuna-pm7550ba.dtsi | 19 ++++++++++++++++++- qcom/tuna-pmih010x.dtsi | 6 +++--- qcom/tuna-pmiv0108.dtsi | 19 ++++++++++++++++++- qcom/tuna-thermal.dtsi | 12 ++++++------ 4 files changed, 45 insertions(+), 11 deletions(-) diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index 0a21d8d1..0b022060 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "pm7550ba.dtsi" @@ -231,6 +231,23 @@ }; &thermal_zones { + pm7550ba-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <10000>; + + }; + }; + }; + + pm7550ba-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <11500>; + }; + }; + }; + pm7550ba-2s-ibat-lvl0 { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi index a82a7e84..e9465597 100644 --- a/qcom/tuna-pmih010x.dtsi +++ b/qcom/tuna-pmih010x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "pmih010x.dtsi" @@ -211,7 +211,7 @@ pmih010x-ibat-lvl0 { trips { ibat-lvl0 { - temperature = <7000>; + temperature = <10000>; }; }; }; @@ -219,7 +219,7 @@ pmih010x-ibat-lvl1 { trips { ibat-lvl1 { - temperature = <9000>; + temperature = <11500>; }; }; }; diff --git a/qcom/tuna-pmiv0108.dtsi b/qcom/tuna-pmiv0108.dtsi index 1cfe6696..921bf780 100644 --- a/qcom/tuna-pmiv0108.dtsi +++ b/qcom/tuna-pmiv0108.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -146,6 +146,23 @@ }; &thermal_zones { + pmiv010x-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <10000>; + + }; + }; + }; + + pmiv010x-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <11500>; + }; + }; + }; + sys-therm-7 { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/qcom/tuna-thermal.dtsi b/qcom/tuna-thermal.dtsi index 1a844d48..29406413 100644 --- a/qcom/tuna-thermal.dtsi +++ b/qcom/tuna-thermal.dtsi @@ -1244,7 +1244,7 @@ cooling-maps { gpu0_cdev { trip = <&gpu0_tj_cfg>; - cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 0 6>; }; }; }; @@ -1283,7 +1283,7 @@ cooling-maps { gpu1_cdev { trip = <&gpu1_tj_cfg>; - cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 0 6>; }; }; }; @@ -1322,7 +1322,7 @@ cooling-maps { gpu2_cdev { trip = <&gpu2_tj_cfg>; - cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 0 6>; }; }; }; @@ -1361,7 +1361,7 @@ cooling-maps { gpu3_cdev { trip = <&gpu3_tj_cfg>; - cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 0 6>; }; }; }; @@ -1400,7 +1400,7 @@ cooling-maps { gpu4_cdev { trip = <&gpu4_tj_cfg>; - cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 0 6>; }; }; }; @@ -1439,7 +1439,7 @@ cooling-maps { gpu5_cdev { trip = <&gpu5_tj_cfg>; - cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 0 6>; }; }; }; From 1447a58e8d79fa4790cfd81de0f15f9796e6cb0c Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Thu, 17 Oct 2024 17:34:13 +0530 Subject: [PATCH 19/26] ARM: dts: msm: PCIe CESTA related dt properties for tuna PCIe CESTA related dt properties for tuna. Change-Id: I4bb53ed6378bb6f02600ec8d6109788a2bc84312 Signed-off-by: Paras Sharma --- qcom/tuna-pcie.dtsi | 86 +++++++++++++++++++-------------------------- qcom/tuna.dtsi | 2 +- 2 files changed, 37 insertions(+), 51 deletions(-) diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi index 336c5867..fa026b35 100644 --- a/qcom/tuna-pcie.dtsi +++ b/qcom/tuna-pcie.dtsi @@ -17,8 +17,9 @@ <0x40000f20 0xa8>, <0x40001000 0x1000>, <0x40100000 0x100000>, - <0x1c03000 0x1000>; - reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi"; + <0x1c03000 0x1000>, + <0x01D07000 0x7000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi", "pcie_sm"; cell-index = <0>; linux,pci-domain = <0>; @@ -50,22 +51,8 @@ &pcie0_clkreq_sleep &pcie0_wake_default>; - gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>; gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>; - vreg-1p2-supply = <&L4B>; - vreg-0p9-supply = <&L2B>; - vreg-qref-supply = <&L2B>; - vreg-cx-supply = <&VDD_CX_LEVEL>; - vreg-mx-supply = <&VDD_MXA_LEVEL>; - qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>; - qcom,vreg-0p9-voltage-level = <912000 880000 92070>; - qcom,vreg-qref-voltage-level = <880000 880000 46800>; - qcom,vreg-cx-voltage-level = ; - qcom,vreg-mx-voltage-level = ; - qcom,bw-scale = /* Gen1 */ ; interconnect-names = "icc_path"; - interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, - <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, - <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, - <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, - <&pcie_0_pipe_clk>; - clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", - "pcie_aux_clk", "pcie_cfg_ahb_clk", - "pcie_mstr_axi_clk", "pcie_slv_axi_clk", - "pcie_clkref_en", "pcie_slv_q2a_axi_clk", - "pcie_rate_change_clk", - "gcc_ddrss_pcie_sf_qtb_clk", - "pcie_aggre_noc_axi_clk", - "gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", - "pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux", - "pcie_pipe_clk_ext_src"; - qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, - <100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; - clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, - <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>; + interconnects = <&pcie_noc MASTER_PCIE_0_PCIE_CRM_HW_0 + &mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_PHY_BCR>; @@ -129,8 +86,6 @@ qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,drv-name = "lpass"; - qcom,drv-l1ss-timeout-us = <5000>; qcom,pcie-phy-ver = <112>; qcom,phy-status-offset = <0x214>; @@ -253,6 +208,37 @@ 0x0200 0x00 0x0 0x0244 0x03 0x0>; + qcom,drv-name = "cesta"; + qcom,drv-l1ss-timeout-us = <5000>; + qcom,pcie-clkreq-offset = <0x2c48>; + qcom,pcie-clkreq-pin = <118>; + qcom,pcie-sm-branch-offset = <0x1000>; + qcom,pcie-sm-start-offset = <0x1090>; + + qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>, + <0x28007003>, <0x80804002>, <0x70021c01>, + <0x18002802>, <0x70005000>, <0x10004000>, + <0x80814002>, <0x18001c01>, <0x1c018080>, + <0x0000100>; + + qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>, + <0x0>, <0x0>; + + qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */ + <0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */ + <0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */ + <0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */ + <0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */ + <0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */ + <0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */ + <0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */ + <0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */ + <0x1088>, /* PCIE_SMs_SEQ_PC_VAL */ + <0x1090>, /* PCIE_SMs_SEQ_START */ + <0x1094>, /* PCIE_SMs_CLKREQ_GATE */ + <0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */ + <0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */ + status = "disabled"; pcie0_rp: pcie0_rp { diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 9f46b027..0b726612 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -71,7 +71,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1"; stdout-path = "serial0:115200n8"; }; From 5d6949eaf073291d58a25abc180a0294ff054393 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Fri, 24 Jan 2025 19:34:51 +0530 Subject: [PATCH 20/26] ARM: dts: msm: Update QoS for tuna SDC2 Update tuna SDC QoS cpu mask. Change-Id: I6f925e294ef0e8511f24339e256aafcd3f2fe32d Signed-off-by: Manish Pandey --- qcom/tuna.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 9f46b027..53a5f176 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2457,12 +2457,12 @@ reset-names = "core_reset"; qos0 { - mask = <0xc0>; + mask = <0xf0>; vote = <44>; }; qos1 { - mask = <0x3f>; + mask = <0x0f>; vote = <44>; }; }; From 07d3ff5e66780bbaf78d7ff28f78099df161aede Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Mon, 27 Jan 2025 15:48:02 +0530 Subject: [PATCH 21/26] ARM: dts: qcom: Add interconnect-names in rproc cdsp node for tuna Add interconnect-names in remoteproc cdsp node for tuna. Change-Id: I4551479bc259584728a681962e1a67f32daba29b Signed-off-by: Shivendra Pratap --- qcom/tuna.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index e676d975..e878bdd7 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1034,6 +1034,8 @@ interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 0>, From 729d8161a77a6c0050ca10431e6526b13ba943d8 Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Tue, 31 Dec 2024 07:59:35 +0530 Subject: [PATCH 22/26] ARM: dts: qcom: Correct gpio pins for i2s0_sd0 Update of correct gpio pin for i2s_ds0. Change-Id: I6716bdd61c90909cbbc646638ea97d98ae5b50ba Signed-off-by: Ravulapati Vishnu Vardhan Rao --- qcom/kera-pinctrl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi index 6b0011c4..ca4cb3ed 100644 --- a/qcom/kera-pinctrl.dtsi +++ b/qcom/kera-pinctrl.dtsi @@ -67,12 +67,12 @@ i2s0_sd0 { i2s0_sd0_sleep: i2s0_sd0_sleep { mux { - pins = "gpio62"; + pins = "gpio64"; function = "gpio"; }; config { - pins = "gpio62"; + pins = "gpio64"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* PULL DOWN */ input-enable; @@ -81,12 +81,12 @@ i2s0_sd0_active: i2s0_sd0_active { mux { - pins = "gpio62"; + pins = "gpio64"; function = "i2s0_data0"; }; config { - pins = "gpio62"; + pins = "gpio64"; drive-strength = <8>; /* 8 mA */ bias-disable; /* NO PULL */ output-high; From 727537d0610105ac48e3476e69b3168fca2a9033 Mon Sep 17 00:00:00 2001 From: Sayantan Chakraborty Date: Fri, 31 Jan 2025 15:07:20 +0530 Subject: [PATCH 23/26] ARM: dts: msm: Update initial DCVS devices for Kera Update initial DCVS devices for Kera. This includes frequency and memlat mapping tables. Change-Id: Ie29a3e0d831fe308b9ee843aba34f6484f461933 Signed-off-by: Sayantan Chakraborty --- qcom/kera.dtsi | 52 +++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 639c6bba..8a45cb38 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -3150,7 +3150,7 @@ < 940800 547000 >, < 1190400 1017000 >, < 2208000 1708000 >, - < 2400000 2092000 >; + < 2361600 2092000 >; }; ddr5-tbl { @@ -3161,7 +3161,7 @@ < 1612800 1555000 >, < 1824000 1708000 >, < 2208000 2092000 >, - < 2400000 3196000 >; + < 2361600 4224000 >; }; }; @@ -3175,8 +3175,8 @@ < 960000 547000 >, < 1209600 1017000 >, < 1459200 1555000 >, - < 1804800 1708000 >, - < 2304000 2092000 >; + < 1900800 1708000 >, + < 2630400 2092000 >; }; ddr5-tbl { @@ -3186,8 +3186,8 @@ < 1209600 768000 >, < 1459200 1555000 >, < 1651200 1708000 >, - < 1804800 2092000 >, - < 2304000 3196000 >; + < 1900800 2092000 >, + < 2630400 3196000 >; }; }; @@ -3203,7 +3203,7 @@ < 1190400 768000 >, < 1612800 1017000 >, < 2208000 1708000 >, - < 2400000 2092000 >; + < 2361600 2092000 >; }; ddr5-tbl { @@ -3213,7 +3213,7 @@ < 1190400 768000 >, < 1612800 1555000 >, < 2208000 2092000 >, - < 2400000 3196000 >; + < 2361600 3196000 >; }; }; @@ -3248,9 +3248,9 @@ qcom,cpulist = <&CPU0 &CPU1 &CPU2>; qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = - < 883200 350000 >, - < 1401600 533000 >, - < 2016000 600000 >; + < 902400 350000 >, + < 1497600 533000 >, + < 2054400 600000 >; }; gold { @@ -3262,9 +3262,9 @@ < 1190400 533000 >, < 1401600 600000 >, < 1824000 806000 >, - < 2803200 933000 >, - < 2918400 1066000 >, - < 3014400 1211000 >; + < 2534400 933000 >, + < 2707200 1066000 >, + < 2841600 1211000 >; }; gold-compute { @@ -3296,10 +3296,10 @@ < 1113600 998400 >, < 1228800 1094400 >, < 1344000 1209600 >, - < 1497600 1363200 >, + < 1497600 1344000 >, < 1708800 1497600 >, - < 1804800 1516800 >, - < 2054400 1804800 >; + < 1843200 1593600 >, + < 2054400 1785600 >; }; gold { @@ -3308,14 +3308,14 @@ qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = < 480000 364800 >, - < 940800 556800 >, + < 940800 518400 >, < 1190400 710400 >, < 1286400 902400 >, < 1497600 1209600 >, - < 1708800 1363200 >, + < 1708800 1344000 >, < 2073600 1497600 >, - < 2400000 1516800 >, - < 2707200 1804800 >; + < 2361600 1593600 >, + < 2707200 1785600 >; }; prime { @@ -3324,14 +3324,14 @@ qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = < 480000 364800 >, - < 633600 556800 >, + < 633600 518400 >, < 960000 806400 >, < 1324800 998400 >, < 1651200 1209600 >, - < 1766400 1363200 >, - < 2208000 1497600 >, - < 2496000 1516800 >, - < 2918400 1804800 >; + < 1766400 1344000 >, + < 2150400 1497600 >, + < 2496000 1593600 >, + < 2630400 1785600 >; }; prime-compute { From 47a0cb5019d8d4b5bd86f43676b7834d141975e1 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Thu, 23 Jan 2025 16:01:51 +0530 Subject: [PATCH 24/26] ARM: dts: msm: Update regulator support for tuna Add RET mode support for L2G/L3G for tuna platforms as per the sleep setting recommendation. While at it set init mode as LPM for L3G and L6K regulators. As clients always vote for 0 load, the regulator framework will not apply it and the HPM init-mode will not change, leading to higher power consumption. So update the LPM for L3G and L6K regulators. Change-Id: I5b210ac3e9ffee94889c2390becfaa5eb6c235ab Signed-off-by: Kavya Nunna --- qcom/tuna-regulators.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index 8071f35e..69aa634c 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -953,9 +953,10 @@ qcom,resource-name = "ldog2"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 30000>; + qcom,mode-threshold-currents = <0 10000 30000>; L2G: pm_v6g_l2: vreg-pm_v6g-l2 { regulator-name = "pm_v6g_l2"; @@ -973,9 +974,10 @@ qcom,resource-name = "ldog3"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 30000>; + qcom,mode-threshold-currents = <0 10000 30000>; L3G: pm_v6g_l3: vreg-pm_v6g-l3 { regulator-name = "pm_v6g_l3"; @@ -983,7 +985,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; qcom,init-voltage = <1800000>; - qcom,init-mode = ; + qcom,init-mode = ; }; }; @@ -1123,7 +1125,7 @@ regulator-min-microvolt = <1100000>; regulator-max-microvolt = <2000000>; qcom,init-voltage = <1776000>; - qcom,init-mode = ; + qcom,init-mode = ; }; }; From 2c23f45466a311ad3b994a32201a669b9140b107 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Sun, 19 Jan 2025 12:10:50 +0530 Subject: [PATCH 25/26] ARM: dts: msm: Add mode thresholds for S2B for tuna Add mode voting support for S2B for tuna platforms. Update the retention threshold to 50ma as per the HW recommendations. UFS needs to do mode vote on vccq parent, add mode vote for S2B for tuna. Change-Id: I3101f3f1fb0255bdee94d4b854f7b8c73186a035 Signed-off-by: Kavya Nunna --- qcom/tuna-regulators.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index 1584b18b..32bfa254 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -22,6 +22,10 @@ rpmh-regulator-smpb2 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpb2"; + qcom,regulator-type = "pmic5-ftsmps"; + qcom,supported-modes = ; + qcom,mode-threshold-currents = <0 50000>; S2B: pmxr2230_s2: vreg-pmxr2230-s2 { regulator-name = "pmxr2230_s2"; @@ -29,6 +33,7 @@ regulator-min-microvolt = <1240000>; regulator-max-microvolt = <1408000>; qcom,init-voltage = <1240000>; + qcom,init-mode = ; }; }; From 66e7d8554b61b6d1efedd79f3505c6910a31edc1 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Fri, 24 Jan 2025 12:39:28 +0800 Subject: [PATCH 26/26] ARM: dts: msm: Remove some ocp-notifier supplies from sun HDK platforms Sun HDK platform is expected to work without the GNSS board (which also holds PMR735D) being attached. If the board is not attached, regulator-ocp-notifier probe may fail as it references some regulators on PMR735D which do not get probed. Remove those regulator references from regulator-ocp-notifier as they are not strictly necessary under it. Change-Id: Ie6f35a9c6142fe54d7191f9a392074f2e39b2bee Signed-off-by: Fenglin Wu --- qcom/sunp-hdk.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/qcom/sunp-hdk.dtsi b/qcom/sunp-hdk.dtsi index 1e1bb10a..60abfa25 100644 --- a/qcom/sunp-hdk.dtsi +++ b/qcom/sunp-hdk.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-qrd-sku1-v8.dtsi" @@ -9,6 +9,16 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; }; +®ulator_ocp_notifier { + /delete-property/ periph-ac1-supply; + /delete-property/ periph-ac2-supply; + /delete-property/ periph-ac3-supply; + /delete-property/ periph-ac4-supply; + /delete-property/ periph-ac5-supply; + /delete-property/ periph-ac6-supply; + /delete-property/ periph-ac7-supply; +}; + &qupv3_se4_spi { #address-cells = <1>; #size-cells = <0>;