diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 4c5564e3..2cb638bd 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -33,6 +33,7 @@ properties: - qcom,tuna-dispcc - qcom,tuna-dispcc-v1 - qcom,kera-dispcc + - qcom,sun-dispcc_mx clocks: items: diff --git a/qcom/kera-pcie.dtsi b/qcom/kera-pcie.dtsi index 7b27993f..0763fc8d 100644 --- a/qcom/kera-pcie.dtsi +++ b/qcom/kera-pcie.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 4b59ed17..8a45cb38 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1937,12 +1937,12 @@ "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; - protected-clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_AUX_CLK_SRC>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, - <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_1_PIPE_DIV2_CLK_SRC>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + protected-clocks = , , + , , + , , + , , + , , + , ; #clock-cells = <1>; #reset-cells = <1>; }; @@ -3150,7 +3150,7 @@ < 940800 547000 >, < 1190400 1017000 >, < 2208000 1708000 >, - < 2400000 2092000 >; + < 2361600 2092000 >; }; ddr5-tbl { @@ -3161,7 +3161,7 @@ < 1612800 1555000 >, < 1824000 1708000 >, < 2208000 2092000 >, - < 2400000 3196000 >; + < 2361600 4224000 >; }; }; @@ -3175,8 +3175,8 @@ < 960000 547000 >, < 1209600 1017000 >, < 1459200 1555000 >, - < 1804800 1708000 >, - < 2304000 2092000 >; + < 1900800 1708000 >, + < 2630400 2092000 >; }; ddr5-tbl { @@ -3186,8 +3186,8 @@ < 1209600 768000 >, < 1459200 1555000 >, < 1651200 1708000 >, - < 1804800 2092000 >, - < 2304000 3196000 >; + < 1900800 2092000 >, + < 2630400 3196000 >; }; }; @@ -3203,7 +3203,7 @@ < 1190400 768000 >, < 1612800 1017000 >, < 2208000 1708000 >, - < 2400000 2092000 >; + < 2361600 2092000 >; }; ddr5-tbl { @@ -3213,7 +3213,7 @@ < 1190400 768000 >, < 1612800 1555000 >, < 2208000 2092000 >, - < 2400000 3196000 >; + < 2361600 3196000 >; }; }; @@ -3248,9 +3248,9 @@ qcom,cpulist = <&CPU0 &CPU1 &CPU2>; qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = - < 883200 350000 >, - < 1401600 533000 >, - < 2016000 600000 >; + < 902400 350000 >, + < 1497600 533000 >, + < 2054400 600000 >; }; gold { @@ -3262,9 +3262,9 @@ < 1190400 533000 >, < 1401600 600000 >, < 1824000 806000 >, - < 2803200 933000 >, - < 2918400 1066000 >, - < 3014400 1211000 >; + < 2534400 933000 >, + < 2707200 1066000 >, + < 2841600 1211000 >; }; gold-compute { @@ -3296,10 +3296,10 @@ < 1113600 998400 >, < 1228800 1094400 >, < 1344000 1209600 >, - < 1497600 1363200 >, + < 1497600 1344000 >, < 1708800 1497600 >, - < 1804800 1516800 >, - < 2054400 1804800 >; + < 1843200 1593600 >, + < 2054400 1785600 >; }; gold { @@ -3308,14 +3308,14 @@ qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = < 480000 364800 >, - < 940800 556800 >, + < 940800 518400 >, < 1190400 710400 >, < 1286400 902400 >, < 1497600 1209600 >, - < 1708800 1363200 >, + < 1708800 1344000 >, < 2073600 1497600 >, - < 2400000 1516800 >, - < 2707200 1804800 >; + < 2361600 1593600 >, + < 2707200 1785600 >; }; prime { @@ -3324,14 +3324,14 @@ qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = < 480000 364800 >, - < 633600 556800 >, + < 633600 518400 >, < 960000 806400 >, < 1324800 998400 >, < 1651200 1209600 >, - < 1766400 1363200 >, - < 2208000 1497600 >, - < 2496000 1516800 >, - < 2918400 1804800 >; + < 1766400 1344000 >, + < 2150400 1497600 >, + < 2496000 1593600 >, + < 2630400 1785600 >; }; prime-compute { diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index c55f2555..b6a4dab9 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1791,6 +1791,15 @@ #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; + + dispcc_mx: clock-controller@af02000 { + compatible = "qcom,sun-dispcc_mx"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk"; + #clock-cells = <1>; + }; }; evacc: clock-controller@abf0000 { diff --git a/qcom/sunp-hdk.dtsi b/qcom/sunp-hdk.dtsi index 1e1bb10a..60abfa25 100644 --- a/qcom/sunp-hdk.dtsi +++ b/qcom/sunp-hdk.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-qrd-sku1-v8.dtsi" @@ -9,6 +9,16 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; }; +®ulator_ocp_notifier { + /delete-property/ periph-ac1-supply; + /delete-property/ periph-ac2-supply; + /delete-property/ periph-ac3-supply; + /delete-property/ periph-ac4-supply; + /delete-property/ periph-ac5-supply; + /delete-property/ periph-ac6-supply; + /delete-property/ periph-ac7-supply; +}; + &qupv3_se4_spi { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index d608afe7..483484ee 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -39,6 +39,33 @@ qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; }; + + goodix-berlin@5d { + compatible = "goodix,gt9916"; + reg = <0x5d>; + interrupt-parent = <&tlmm>; + interrupts = <176 0x2008>; + goodix,reset-gpio = <&tlmm 189 0x00>; + goodix,irq-gpio = <&tlmm 176 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_i2c.bin"; + goodix,config-name = "goodix_cfg_group_i2c.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + invert_xy; + avdd-supply = <&L22B>; + iovdd-supply = <&L1D>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + goodix,touch-type = "primary"; + goodix,qts_en; + }; }; &ufsphy_mem { diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index c1a91f0a..54db0ede 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &soc { @@ -2187,12 +2187,24 @@ trace-name = "tracenoc-ddr-lpi"; out-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; tpdm_ddr_lpi_out_funnel_aoss: endpoint { remote-endpoint = <&funnel_aoss_in_tpdm_ddr_lpi>; }; }; + + port@1 { + reg = <1>; + ddr_lpi_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_ddr_lpi>; + }; + }; }; }; @@ -4328,6 +4340,14 @@ <&lpass_audio_out_qmi>; }; }; + + port@5 { + reg = <5>; + qmi_in_ddr_lpi: endpoint { + remote-endpoint = + <&ddr_lpi_out_qmi>; + }; + }; }; }; diff --git a/qcom/tuna-debug.dtsi b/qcom/tuna-debug.dtsi index 1baaf8dd..3867c38a 100644 --- a/qcom/tuna-debug.dtsi +++ b/qcom/tuna-debug.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -26,6 +26,1331 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x0>; + + link_list_0 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,ap-qad-override; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_1 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,ap-qad-override; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_2 { + qcom,curr-link-list = <3>; + qcom,data-sink = "sram"; + qcom,ap-qad-override; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; mem_dump { diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 2601180b..fe25e5ba 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -40,14 +40,24 @@ }; idle-states { - CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; }; - CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + CLUSTER_PWR_DWN: d4 { /* C4+D4 */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "l3-pc"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x40000044>; + local-timer-stop; }; }; diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index fd609de8..32bfa254 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -13,22 +13,27 @@ S1B: pmxr2230_s1: vreg-pmxr2230-s1 { regulator-name = "pmxr2230_s1"; qcom,set = ; - regulator-min-microvolt = <1856000>; + regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2104000>; - qcom,init-voltage = <1856000>; + qcom,init-voltage = <1840000>; }; }; rpmh-regulator-smpb2 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpb2"; + qcom,regulator-type = "pmic5-ftsmps"; + qcom,supported-modes = ; + qcom,mode-threshold-currents = <0 50000>; S2B: pmxr2230_s2: vreg-pmxr2230-s2 { regulator-name = "pmxr2230_s2"; qcom,set = ; - regulator-min-microvolt = <1256000>; + regulator-min-microvolt = <1240000>; regulator-max-microvolt = <1408000>; - qcom,init-voltage = <1256000>; + qcom,init-voltage = <1240000>; + qcom,init-mode = ; }; }; @@ -39,7 +44,7 @@ S3B: pmxr2230_s3: vreg-pmxr2230-s3 { regulator-name = "pmxr2230_s3"; qcom,set = ; - regulator-min-microvolt = <880000>; + regulator-min-microvolt = <864000>; regulator-max-microvolt = <1040000>; qcom,init-voltage = <952000>; }; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 28e6007b..0a463690 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -42,14 +42,24 @@ }; idle-states { - CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; }; - CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + CLUSTER_PWR_DWN: d4 { /* C4+D4 */ compatible = "arm,idle-state"; - status = "disabled"; + idle-state-name = "l3-pc"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x40000044>; + local-timer-stop; }; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index fa379dc5..359ac6b3 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1042,6 +1042,8 @@ interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 0>, @@ -2466,12 +2468,12 @@ reset-names = "core_reset"; qos0 { - mask = <0xc0>; + mask = <0xf0>; vote = <44>; }; qos1 { - mask = <0x3f>; + mask = <0x0f>; vote = <44>; }; };